CN1906744A - 具有柔性电互连和柔性密封件的装置 - Google Patents

具有柔性电互连和柔性密封件的装置 Download PDF

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CN1906744A
CN1906744A CNA2004800409357A CN200480040935A CN1906744A CN 1906744 A CN1906744 A CN 1906744A CN A2004800409357 A CNA2004800409357 A CN A2004800409357A CN 200480040935 A CN200480040935 A CN 200480040935A CN 1906744 A CN1906744 A CN 1906744A
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Q·白
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Avago Technologies International Sales Pte Ltd
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Abstract

包括第一基片(21)、第二基片(24)与柔性件(27，42)的装置。该柔性件包括在此第一与第二基片间的第一种柔性材料，且具有至少以一部分以第二种材料层(33，47)涂覆的侧面。此柔性件随着第一与第二基片压合到一起而呈现变形。在某些实施形式中，此第二种材料为导电性的以使柔性件能在两基片间提供可靠的电连接，在另一些实施形式中，此第二种材料提高了柔性件的气密性使柔性件在两基片间可提供更好的气密封接。

Description

具有柔性电互连和柔性密封件的装置
                      相关技术
在制造微加工式装置时，一般要将电子元件定位到两个结合基片间的密封腔中。在某些应用中，在这样两个结合基片间要求有导电性。例如可在两基片上形成电气元件，而两基片间的电连接则在电气元件间提供了联通。在另一些例子中，两基片间的电连接则可使位于一块基片上的元件能从位于另一块基片上的元件导出电功率。
取决于结合基片的整体构型与尺寸，很难在两基片间实现均匀的结合。不匀的结合尤其广见于高外形的微加工式装置(即具有大厚度的装置)。这种不匀结合可以导致各种制造问题并严重影响生产率。例如，如果两基片不是沿着整个密封周边紧密地结合，则可能损害气密封接。此外，由于结合不均匀，两块基片间的分开距离可能变化。结果两结合基片间的导电接点有可能不会充分地压接到一起为基片之间提供充分的电连接。
共同转让的美国专利No.6090687描述了用于在结合的基片间形成气密封接的改进技术。如专利6090687所描述的，采用柔性材料的垫圈以在两块结合基片间形成气密封接。这种垫圈的柔性能使其在两基片于结合中压到一起时变形。此种变形保证了垫圈的整个周边在结合中紧密地依循两基片的周边，造成更好的密封。但是极少有材料具有良好的柔性与气密性两者，而确实具有这类性质的少数材料常常是昂贵的或不能与许多一般的微加工工艺匹配。
                      发明概述
一般地说，本发明的实施例涉及到具有由柔性接触件连接到一起的结合基片的装置。
依据本发明一典型实施例的制造一种装置的方法包括：提供第一基片与第二基片；在第一基片上形成第一柔性材料的柔性件，此柔性件包括端面和邻接此端面的侧面；用第二材料层涂覆此侧面的至少一部分，将第二基片挤压向柔性件的端面，这种挤压包括使柔性件变形，将此两基片结合到一起。
依据本发明一典型实施例的装置包括第一基片、第二基片与柔性件。此柔性件包括在此第一与第二基片间的第一种柔性材料，并具有至少一部分涂有第二种材料的侧面。此柔性件能显示出与第一基片和已压合到一起的第二侧一致的变形。
在某些实施例中，上述第二材料为导电的能使该柔性件在两基片间提供可靠的电连接。在另一些实施例中，此第二材料能提高该柔性件的气密性，使该柔性件能在两基片间提供更好的气密封接。
                    附图简述
参看下面的附图能更好地理解本发明。附图中的各部件未必相互相对地按比例绘制，目的只在于阐明本发明的原理。此外，在所有附图中以相同的标号指明相应的部件。
图1是依据本发明制造的装置的横剖视图。
图2是示明用于制造装置的典型方法的流程图。
图3是具有在基片表面上形成的柔性柱与柔性垫圈的基片的横剖视图。
图4是图3所示基片的仰视图。
图5是图3所示基片于柔性柱上形成导电层且于其垫圈上形成气密层后的横剖视图。
图6是拟结合到图5所示基片上的基片的顶视图。
图7是图5所示基片在基片表面上形成间隔件后的横剖视图。
图8是图7所示基片的仰视图。
图9是图7所示基片结合了另一基片后的横剖视图。
图10是示明用于制造装置的另一典型方法的流程图。
图11是具有形成在基片表面上柔性柱与柔性垫圈的基片的横剖视图。
图12是图11所示基片于柔性柱上形成导电层后的横剖视图。
图13是图12所示基片结合有图6所示基片的横剖视图。
图14是图13所示基片在位于基片间的垫圈的朝外侧面涂有气密性增强层后的横剖视图。
图15是在批量制造多个类似于图14所示的多个装置时所用到的结合基片的俯视图。
图16是图15中的结合的基片在上部基片已切割后的顶视图。
                    详细说明
本发明的各实施形式总体涉及到用以在结合的基片间提供气密封接或电连接的改进的技术。一般地说，用于在两块结合的基片间形成气密封接或电连接的柔性件(例如垫圈或柱)是形成在两块基片之一上。此种柔性件是由例如聚酰亚胺等柔性材料形成。这种柔性材料至少其一部分涂有选择用来提高其电导率或气密性的材料。
在结合之前或结合过程中，将柔性件压向另一基片。柔性件的柔性使其能变形而符合此基片的表面。结果此柔性件便在结合的基片间形成较好的电连接与气密封接。
图1示明了依据本发明一典型实施形式制造的装置15。如图1所示，装置15有两块基片21与24。在一种实施形式中，各块基片21与24都是由硅组成。但在另一些实施形式中，基片21与24可由其他材料构成。图1所示的装置15有两个在基片21与24之间延伸使它们相互电连接的导电柱27。各个柱27的两相对端分别压向基片21与24。导电柱27上的其他标号可以用于其他实施形式中。
各导电柱27由柔性材料如聚酰亚胺或其他类型的聚合物组成。在传统的微制造式装置中，聚合物通常用作应力消除层或用作结合材料。但聚合物普遍是弱导体且尚未用在微加工式装置基片间提供电连接。
各个柱27涂覆导电材料的薄层33。如以下将详细描述的，在基片21与24结合到一起之前导电柱27便形成在基片21上。在基片24上形成有用于接触导电柱27的导电盘36。盘36通过为各个柱27提供较广的供接触的导电区来完成基片21与24之间的电连接。柱27可以与存在于基片21和/或24上的电路电连接。
垫圈42环绕装置15的周边延伸。垫圈42的两相对端分别压向基片21与24，且为装置15内的腔44提供了气密封接。垫圈42由柔性材料如聚酰亚胺或其他类型柔性聚合物等柔性材料构成。如上所述，在传统的微制造式装置中，聚合物通常用作应力消除层或用作结合材料。但聚合物一般是气密性差的，迄今未用于形成气密封接。
垫圈42用诸如金、铜、玻璃或氮化硅之类薄的材料层41涂覆以提高垫圈42的气密性。在平行于基片21和24主表面的平面上，垫圈24可以取适合于容纳位于腔44中的部件所需的任何形状(例如圆形、方形、矩形等)。可以在基片24上形成一般49来沿着垫圈42的整个周边与垫圈42接触。
为了形成图1的装置15，开始时于基片21的主表面上由柔性材料形成柱27与垫圈42，如图2的框52以及图3与4所示，各种微加工技术如光刻、蚀刻与热固化等可以用来形成柱27与垫圈42。在一典型实施形式中，柱27与垫圈42是通过在基片21上淀积一层聚酰亚胺材料层形成。然后用光刻、蚀刻与热固化形成柱27与垫圈42。图4中所示的柱27具有在平行于基片21的主表面的平面上的大致圆形横剖面。但在其他实施形式中，垫圈42与柱27可以具有其他横剖面形状。此外如图4所示，可以于基片21的表面上形成电路39并与一或多个柱27电耦合。
如图5与图2的框54所示，各个柱27涂有薄的导电层33，而垫圈42涂有增强其气密性的薄层47。可以采用种种微加工技术的溅射、蒸镀、化学汽相淀积(CVD)或电镀来形成层33与47。在一典型实施形式中，为了给柱27涂以层33，采用蒸镀或溅射于基片21的表面(包括柱27与垫圈42)淀积薄的籽晶层。然后用电镀法于此籽晶层上淀积一层导电材料。用光刻与蚀刻从基片21上除柱27以外的所有部分上除去此籽晶层与导电层。结果于柱27上保留有导电材料层33。
此外，为了给垫圈42涂以金层47，例如用蒸镀法或溅射法于此基片的表面(包括柱27与垫圈42)淀积一薄的籽晶层。然后用电镀法在此籽晶层上淀积金层。然后用光刻与蚀刻从基片21上将垫圈42以外的所有部分除去籽晶层与金层，结果在垫圈42上保留了金层47。
在另一些实施例中可以用其他技术形成柱27与垫圈42，以及用金以外的材料来形成层47。如果层33与47是由相同材料构成，则它们可用上述种种技术同时形成。此时，在用电镀于基片21上淀积层33与47的材料后，用光刻与蚀刻从基片21上除去柱27与垫圈42以外的所有部分的材料。
在图5所示的典型实施形式中，各个柱27全涂以层33的材料而垫圈42则完全以层47的材料涂覆。换言之，图4所示柱27的全部暴露区域是由层33的材料覆盖，而图4所示垫圈42的全部暴露区域是以层47的材料覆盖。但在其他实施形式中，则能分别以层33与47部分地覆盖柱27与垫圈42。事实上，在下面的典型实施例中只是垫圈42的面向外的侧面涂以层47的材料。
假若电路39确实是位于基片21的表面上，则此电路39可以在柱27与垫圈42形成之前由淀积到基片21上的电介质层或其他类型的绝缘层覆盖。这样的层将保护电路39在用来形成柱27与垫圈42的处理中不受影响。为了在形成柱27与垫圈42时更好地保护上述电路，应避免超过此电路可接受的温度范围的处理。
图6是基片24的顶视图。基片24的表面上形成有盘36与49。比较图4与6可见，盘36与49在平行于基片24主表面的平面中的形状可以分别与平行基片21主表面的平面中柱27与垫圈42的剖面形状相同。但盘36与49也可以有不同于柱27与垫圈42剖面形状的形状。此外，如图6所示，可在基片24的表面上形成电路51且使之与一或多个盘36电耦合。在这种实施形式中，一旦在基片21与24结合到一起时电路51便通过一或多个柱与基片21的电路39(图4)耦连，这将在以后更详细地述及。
如图2的块56中所述，基片21与24压合到一起并通过将基片24上的柱27、垫圈42和/或其他部件结合到基片24上而结合。特别是，基片21与24对准并压合到一起，使得在基片24上的盘36与49分别和柱27与垫圈42接触。柱27的柔性释放了应力，否则应力将存在于柱27上，因而并因此防止了柱27在基片21与24压合到一起时破裂或折断。此外，基片21与24压合到一起时，垫圈42便压向基片24的盘49。垫圈42的柔性使其能在基片21与24压合到一起时变形。垫圈42的变形释放了不然将存在于其中的应力，从而防止了垫圈42在基片21与24压合到一起时破裂或断开。此基片21与24在压到一起时结合。各种已知的或将来开发的结合技术如低共熔金属结合、热压或胶合都可用来结合基片21与24。
在一典型实施形式中，于垫圈42与盘49之间形成低共熔金属结合。特别是，层47是由金(Au)构成。此外，在盘49上淀积锡(Sn)。然后将基片21与24压合到一起，加热到熔化锡，使锡扩散到金属47的温度。结果在盘49与垫圈42间形成了金-锡(Au-Sn)结合。在另一些实施形式中，可以用其他类型的材料在基片21与24的部件之间形成低共熔金属结合，以及能采用其他类型的结合技术来结合基片21与24。再有，可以通过结合基片21与24的其他部件例如柱27或其他未于图1中标明的其他部件来结合这两基片21和24。
柱27与垫圈42的柔性能使它们即便其高度(沿y方向测量)有稍许变化或是基片21或24的表面形貌有变化，也可与基片24紧密与均匀地接触。例如，要是在微加工过程中的缺陷使得柱27中之一或垫圈42的一部分在另一柱27或垫圈42的另一部分之前与基片42接触，则与基片24接触的柱27或垫圈部分将在基片21与24进一步压合时变形，以在基片24与柱27以及垫圈42的整个周边间形成接触。
注意，装置15不必要包括导电柱27与垫圈42这两者。如上所述垫圈42可以在基片21与24之间提供气密封接而并不使基片21与24间电连接。另外，能够如前所述在基片21与24之间没有垫圈42时提供一或多个电连接件。
再有，柱27和垫圈42的涂层33与47取决于柱27与垫圈42的厚度可分别具有不同的厚度。垫圈42与柱27的柔性应在其压向基片24时足以变形到不会破坏或以其他方式出现机械性断裂。这些部件的柔性一般是由层33与47分别所涂的柔性材料提供。但是可以用来形成层33与47的许多种材料基本上是非柔性的。这样，例如层33与47太厚时，柱27与垫圈42的柔性就会降低到在压向基片24时不能充分地变形。若是层33与47显著地降低了柱件27与垫圈42的柔性，则当基片21与24压合到一起时，柱27与垫圈42便可能发生破坏或其他机构性断裂。此外，装置15一个区域上的柱27或垫圈部分有可能不能充分地变形以使另一柱27或垫圈42的其余部分与基片24接触。
这样，为了避免上述问题，使各个导电层33比其对应的柱27要显著地薄。层33要形成得尽可能地薄以在基片21与24之间提供低电阻电连接。上述问题也可以通过使层47充分地薄于垫圈42而得以避免。层47制备得尽可能地薄但要能为腔44提供规定的气密性。对于厚度约为50μm的绝大多数聚合物柱27与垫圈42而言，约3～5μm厚的导电与气密层33与47通常能达到上述目的。但是，取决于柱27与垫圈42的材料与尺寸以及层33与47的材料，层33与47的合适厚度可以在上述范围之外。
在某些实施形式中，层47是由导电材料(例如与层33相同的材料)构成，这样能使垫圈42除提供气密封接外还可在基片21与24之间形成电连接。当层47由导电材料构成时，垫圈42也可用作为电屏蔽以在腔44中的元件与腔44外面的元件间提供电隔绝。
在上述实施例中，于基片21上形成了柱27与垫圈42两者。但在有需要时也可将柱27与垫圈42形成于不同的基片上。例如可如以前所述，在基片21与24压到一起并结合之前，将柱27形成到基片21上而将垫圈42形成到基片24上。
此外，还能用非柔性隔件来精密地控制基片21与24之间的间隔距离，并在基片21与24压合到一起时控制柔性件27与42的形成。图7与8例示了在基片21上形成了四个非柔性隔件68，而在另一些实施形式中是可以有其他个数的隔件68的，再有，虽然各隔件68是位于垫圈42的周边之外，因而在图7与8所示例子中是在腔44之外面，但也能将一或多个隔件68设于垫圈周边之内，因而在另一些实施形式中是在腔44之内。
图7与8中的各个隔件68具有(沿y方向测量的)相同高度。此高度小到足以使基片24在接触到隔件68之前在最小公差条件下接触到所有柱27与垫圈42。这样，当基片21与24紧密地压合到一起时，柱27与垫圈42便如上所述与基片24接触然后变形。隔件68也短到足以使柱27与垫圈42充分地变形，而如上所述能在基片21与24之间提供低电阻连接并为腔44提供特定的气密性。当基片24接触隔件68后，如图9所示，隔件68阻止了基片移近到一起。这样，通过将基片21与24以图9中所示位置结合，基片21与24所分开的距离便能精确地与隔件68的高度相匹配。
图10示明了可用来在根据本发明一实施形式制造的装置内形成电连接与气密封接的另一典型方法。在图10所示的方法中，垫圈42在基片21与24结合后涂以不同材料的层84。结果，腔44中的元件(例如电路39与51)在给垫圈42涂层时便不会暴露而因此得到保护。
如图11与图10的框72所示，柱27与垫圈42是由柔性材料形成于基片21的主表面上。然后如图12与图10的框74所示，各个柱27涂以导电材料层33。如图13与图10的框76所示，此时的基片21压向另一基片24并与之结合。特别是此基片21与24对准并压合到一起，使得柱27与盘36接触而垫圈42与盘49接触。柱27与垫圈42的柔性使它们能在基片21与24相压合时变形。这样，基于上述理由，在此两基片结合过程，柱27与垫圈42的柔性便有助于保证垫圈42的周边和各个柱27紧密与均匀地同基片24的部件(例如盘36和49)接触。结果，柱27在基片21与24间形成了更好的电连接，而垫圈42则在基片21与24间形成了更好的气密封接。
在批量生产中，对于各个装置用单一晶片作为基片21再用单一晶片作为基片24，能在同时对数干个装置进行微加工。在这一实施形式中，在将基片21切割之前或在形成有通过基片21厚度的通孔(未示明)之前，不大可能对任何一个装置的垫圈42进行涂覆涂层。这样，当在图10的框76中基片21与24结合后，便沿着图13所示的虚线切割基片21，提供到垫圈42的通道，如图10的框82所示。这种通道可使垫圈42用常规的微加工技术如电镀或化学汽相淀积(CVD)涂以层84。这样，在图10的框82中切割基片21后，垫圈42的外侧面便可涂以材料(例如金)层84，提高垫圈42的气密封接性，如图14与图10的框88所示。在图14所示的装置92中，各个已涂覆的柱27在基片21与24间提供电连接，而已涂覆的垫圈42则给腔44提供了气密封接。
为了进一步阐明以上所述种种，参考图15，它是图10的框76中基片21与24已结合后的基片21的顶视图。在图15所示的实施例中，有九个垫圈42设于基片21与24之间并以虚线表示，实际上它们在图中是无法看见的。图15中的垫圈42不容易接近以涂覆涂层。
在图10的框82中，基片21如图16所示作了切割。因此，除去了垫圈42之间的基片21部分。这样，在进行图10框88中的电镀或CVD时，材料便可在基片21的余剩部分之间经过而给各个垫圈42的外侧面涂覆涂层。然后可切割基片24形成九个独立的如图14所示的装置92。在另一实施形式中，能够依类似方式通过切割基片24而不是基片21，提供到垫圈42的通路。

Claims (10)

1.制造装置(15)的方法，此方法包括：
提供第一基片(21)与第二基片(24)；
于上述第一基片上形成第一种柔性材料的第一柔性件(21，24)，此柔性件包括端面和与此端面邻接的侧面；
用第二种材料的层(33，47)涂覆上述侧面的至少一部分；
向第二基片挤压向中述柔性件的所述端面，所述挤压包括使所述柔性件变形；
将上述两基片结合在一起。
2.权利要求1的方法，其中所述第一种材料包括聚合物。
3.权利要求1的方法，其中所述第一种材料包括聚酰亚胺。
4.权利要求1的方法，其中所述涂覆包括将所述第二种材料选择为这样一种材料，使其能比所述第一种材料单独时给上述柔性件提供更高电导性。
5.权利要求1的方法，其中所述涂覆包括将上述第二种材料选择为这样一种材料，使其能比所述第一种材料单独时给上述柔性件提供更高气密性。
6.权利要求1的方法，它还包括在所述两基片中之一上形成非柔性隔件(68)，其中所述挤压包括将所述第一与第二基片压紧到一起，直至这两基片之一接触所述隔件。
7.一种装置(15)，它包括：
第一基片(21)；
第二基片(24)；以及
在此第一与第二基片间的第一种柔性材料的柔性件(27，42)，此柔性件包括至少是部分地涂以第二种材料层(33，47)的侧面，此柔性件呈现出与已经被压合到一起的所述第一基片与第二基片一致的变形。
8.权利要求7的装置，其中所述第一种材料包括聚酰亚胺。
9.权利要求7的装置，其中所述第一种材料比所述第一种材料单独时能给所述柔性件提供更高的电导性。
10.权利要求17的装置，其中，所述第二种材料能比所述第一种材料给所述柔性件提供更高的气密性。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102066109A (zh) * 2008-06-20 2011-05-18 阿尔卡特朗讯美国公司 热传递结构

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7275292B2 (en) * 2003-03-07 2007-10-02 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Method for fabricating an acoustical resonator on a substrate
US6946928B2 (en) * 2003-10-30 2005-09-20 Agilent Technologies, Inc. Thin-film acoustically-coupled transformer
US7388454B2 (en) 2004-10-01 2008-06-17 Avago Technologies Wireless Ip Pte Ltd Acoustic resonator performance enhancement using alternating frame structure
US8981876B2 (en) 2004-11-15 2015-03-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Piezoelectric resonator structures and electrical filters having frame elements
US7202560B2 (en) 2004-12-15 2007-04-10 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Wafer bonding of micro-electro mechanical systems to active circuitry
US7791434B2 (en) 2004-12-22 2010-09-07 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Acoustic resonator performance enhancement using selective metal etch and having a trench in the piezoelectric
US7369013B2 (en) 2005-04-06 2008-05-06 Avago Technologies Wireless Ip Pte Ltd Acoustic resonator performance enhancement using filled recessed region
WO2007034240A2 (en) 2005-09-20 2007-03-29 Bae Systems Plc Sensor device with backside contacts
JP4834369B2 (ja) * 2005-10-07 2011-12-14 ルネサスエレクトロニクス株式会社 半導体装置
US7525398B2 (en) 2005-10-18 2009-04-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustically communicating data signals across an electrical isolation barrier
US7737807B2 (en) 2005-10-18 2010-06-15 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Acoustic galvanic isolator incorporating series-connected decoupled stacked bulk acoustic resonators
US7746677B2 (en) 2006-03-09 2010-06-29 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. AC-DC converter circuit and power supply
US7479685B2 (en) 2006-03-10 2009-01-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Electronic device on substrate with cavity and mitigated parasitic leakage path
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8133762B2 (en) * 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US20080164606A1 (en) * 2007-01-08 2008-07-10 Christoffer Graae Greisen Spacers for wafer bonding
US7530814B2 (en) * 2007-09-25 2009-05-12 Intel Corporation Providing variable sized contacts for coupling with a semiconductor device
US7855618B2 (en) 2008-04-30 2010-12-21 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Bulk acoustic resonator electrical impedance transformers
US7732977B2 (en) 2008-04-30 2010-06-08 Avago Technologies Wireless Ip (Singapore) Transceiver circuit for film bulk acoustic resonator (FBAR) transducers
US8618670B2 (en) * 2008-08-15 2013-12-31 Qualcomm Incorporated Corrosion control of stacked integrated circuits
US8248185B2 (en) 2009-06-24 2012-08-21 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Acoustic resonator structure comprising a bridge
US8902023B2 (en) 2009-06-24 2014-12-02 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator structure having an electrode with a cantilevered portion
US8193877B2 (en) 2009-11-30 2012-06-05 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Duplexer with negative phase shifting circuit
US8796904B2 (en) 2011-10-31 2014-08-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Bulk acoustic resonator comprising piezoelectric layer and inverse piezoelectric layer
US9243316B2 (en) 2010-01-22 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Method of fabricating piezoelectric material with selected c-axis orientation
JP6342033B2 (ja) * 2010-06-30 2018-06-13 キヤノン株式会社 固体撮像装置
JP5505171B2 (ja) * 2010-07-30 2014-05-28 富士通株式会社 回路基板ユニット、回路基板ユニットの製造方法、及び電子装置
US8962443B2 (en) 2011-01-31 2015-02-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor device having an airbridge and method of fabricating the same
US9136818B2 (en) 2011-02-28 2015-09-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Stacked acoustic resonator comprising a bridge
US9048812B2 (en) 2011-02-28 2015-06-02 Avago Technologies General Ip (Singapore) Pte. Ltd. Bulk acoustic wave resonator comprising bridge formed within piezoelectric layer
US9425764B2 (en) 2012-10-25 2016-08-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Accoustic resonator having composite electrodes with integrated lateral features
US9148117B2 (en) 2011-02-28 2015-09-29 Avago Technologies General Ip (Singapore) Pte. Ltd. Coupled resonator filter comprising a bridge and frame elements
US9203374B2 (en) 2011-02-28 2015-12-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Film bulk acoustic resonator comprising a bridge
US9083302B2 (en) 2011-02-28 2015-07-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Stacked bulk acoustic resonator comprising a bridge and an acoustic reflector along a perimeter of the resonator
US9154112B2 (en) 2011-02-28 2015-10-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Coupled resonator filter comprising a bridge
US8575820B2 (en) 2011-03-29 2013-11-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Stacked bulk acoustic resonator
US9444426B2 (en) 2012-10-25 2016-09-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Accoustic resonator having integrated lateral feature and temperature compensation feature
CN103460376B (zh) * 2011-04-11 2016-02-17 株式会社村田制作所 电子部件以及电子部件的制造方法
US8350445B1 (en) 2011-06-16 2013-01-08 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Bulk acoustic resonator comprising non-piezoelectric layer and bridge
US8922302B2 (en) 2011-08-24 2014-12-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator formed on a pedestal
WO2013141091A1 (ja) * 2012-03-23 2013-09-26 オリンパス株式会社 積層型半導体装置およびその製造方法
EP2854170B1 (en) 2013-09-27 2022-01-26 Alcatel Lucent A structure for a heat transfer interface and method of manufacturing the same
US9373585B2 (en) * 2014-09-17 2016-06-21 Invensas Corporation Polymer member based interconnect
US9666514B2 (en) 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
US11600573B2 (en) * 2019-06-26 2023-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with conductive support elements to reduce warpage
CN116093031A (zh) * 2020-12-31 2023-05-09 华为技术有限公司 板级结构及通信设备

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967162A (en) * 1974-07-24 1976-06-29 Amp Incorporated Interconnection of oppositely disposed circuit devices
US4116517A (en) * 1976-04-15 1978-09-26 International Telephone And Telegraph Corporation Flexible printed circuit and electrical connection therefor
US4769272A (en) 1987-03-17 1988-09-06 National Semiconductor Corporation Ceramic lid hermetic seal package structure
US4813129A (en) * 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
US4857668A (en) * 1988-04-15 1989-08-15 Schlegel Corporation Multi-function gasket
JPH0349246A (ja) * 1989-07-17 1991-03-04 Hitachi Ltd 半導体集積回路装置
JP2510404Y2 (ja) * 1990-11-29 1996-09-11 北川工業株式会社 電磁波シ―ルド用ガスケット
US5262347A (en) 1991-08-14 1993-11-16 Bell Communications Research, Inc. Palladium welding of a semiconductor body
DE69321745T2 (de) 1992-02-04 1999-10-07 Matsushita Electric Industrial Co., Ltd. Direktkontakt-Bildsensor und Herstellungsverfahren dafür
JP2833326B2 (ja) 1992-03-03 1998-12-09 松下電器産業株式会社 電子部品実装接続体およびその製造方法
US5474458A (en) * 1993-07-13 1995-12-12 Fujitsu Limited Interconnect carriers having high-density vertical connectors and methods for making the same
US5397857A (en) * 1993-07-15 1995-03-14 Dual Systems PCMCIA standard memory card frame
CA2129073C (en) * 1993-09-10 2007-06-05 John P. Kalinoski Form-in-place emi gaskets
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5431328A (en) 1994-05-06 1995-07-11 Industrial Technology Research Institute Composite bump flip chip bonding
US6365500B1 (en) 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
US5854514A (en) * 1996-08-05 1998-12-29 International Buisness Machines Corporation Lead-free interconnection for electronic devices
US6266872B1 (en) * 1996-12-12 2001-07-31 Tessera, Inc. Method for making a connection component for a semiconductor chip package
US5938452A (en) * 1996-12-23 1999-08-17 General Electric Company Flexible interface structures for electronic devices
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
JPH1167829A (ja) * 1997-08-22 1999-03-09 Oki Electric Ind Co Ltd 電子部品の実装方法及び該方法に用いる電子部品と配線基板
US6090687A (en) 1998-07-29 2000-07-18 Agilent Technolgies, Inc. System and method for bonding and sealing microfabricated wafers to form a single structure having a vacuum chamber therein
US6118181A (en) 1998-07-29 2000-09-12 Agilent Technologies, Inc. System and method for bonding wafers
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
ATE338446T1 (de) * 2000-02-18 2006-09-15 Parker Hannifin Corp In-situ-herstellung einer elektromagnetisch abgeschirmten dichtung mit geringer schliesskraft
US6358063B1 (en) * 2000-06-28 2002-03-19 Intercon Systems, Inc. Sealed interposer assembly
US6713314B2 (en) * 2002-08-14 2004-03-30 Intel Corporation Hermetically packaging a microelectromechanical switch and a film bulk acoustic resonator
US7005573B2 (en) * 2003-02-13 2006-02-28 Parker-Hannifin Corporation Composite EMI shield

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102066109A (zh) * 2008-06-20 2011-05-18 阿尔卡特朗讯美国公司 热传递结构

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