CN1841743A - 双向晶体管及其方法 - Google Patents
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Abstract
在一个实施方案中,形成晶体管,以便沿二个方向将电流传导通过晶体管。
Description
本申请涉及到与此同时提交的至少具有一个共同发明人、一个共同受让人、且案号为ONS00673的题为“METHOD OF ANINTEGRATED POWER DEVICE AND STRUCTURE”的申请。
技术领域
本发明一般涉及到电子设备,更确切地说是涉及到制作半导体器件和结构的方法。
背景技术
过去,便携式电子系统常常由诸如二个电池或由一个电池和交流插座经由交流/直流转换器或电池充电器之类的多个电源来提供功率。开关网络通常被用来根据工作模式而控制功率流。例如,若便携式装置从初级电池提供功率而次级电池被充电,则有些开关被开通而另一些开关被关断。在另一模式中,各个开关可能已经被反转。为了在所有模式中都有作用,这些开关应该沿二个方向传导和阻断。但功率金属氧化物半导体场效应晶体管(功率MOSFET)仅仅能够沿一个方向阻断电压。MOSFET的体二极管沿反方向传导电流,于是,二个功率MOSFET典型地被串联连接作为一个开关。二个功率MOSFET典型地以其漏连接在一起而被使用,致使当栅电压为0时,不管极性如何,一个器件可能总是阻断跨越二个晶体管而施加的电压。这种开关的一个例子是亚利桑拉州凤凰城ON Semiconductor公司所提供的NTLTD7900。由于这种开关采用了二个晶体管,故这些开关使用的硅是一个晶体管的二倍,提高了成本。此外,由于二个晶体管被串联,故开态电阻大。
因此,希望拥有一种降低成本并减小双向开关电阻的制作双向开关的方法。
发明内容
根据本发明的一方面,提供一种双向晶体管,包括:第一MOS晶体管,它具有本体区、第一电流承载电极、以及第二电流承载电极;以及开关,它被构造成响应于施加到第一MOS晶体管的源和漏的信号而选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第一电流承载电极或第二电流承载电极。
根据本发明的另一方面,提供一种制作双向晶体管的方法,包括:在第一导电类型的半导体衬底上形成第一MOS晶体管;在半导体衬底的表面上形成第一MOS晶体管的本体区,并由第一P-N结隔离于第一MOS晶体管的第一电流承载电极区,且由第二P-N结隔离于第一MOS晶体管的第二电流承载电极区;以及形成耦合的第二MOS晶体管来选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第一电流承载电极。
根据本发明的另一方面,提供一种制作双向晶体管的方法,包括:提供第一导电类型的半导体衬底;在半导体衬底的表面上形成第二导电类型的第一掺杂区,作为第一晶体管的本体区;在第一掺杂区内形成第一导电类型的第二掺杂区并延伸进入第一掺杂区第一距离,作为第一晶体管的第一电流承载电极区;以及形成从第二掺杂区延伸进入第一掺杂区第二距离的第一导电类型的第三掺杂区。
附图说明
图1示意地示出了根据本发明的双向晶体管实施方案一部分的电路表示;
图2示意地示出了根据本发明的图1的双向晶体管实施方案一部分的放大平面图;
图3示出了根据本发明的图2的双向晶体管实施方案的剖面部分;
图4示意地示出了根据本发明的图1-3的双向晶体管变通实施方案一部分的放大平面图;
图5示出了根据本发明的图4的双向晶体管实施方案的剖面部分;而
图6示出了根据本发明的图1和图2的双向晶体管变通实施方案的剖面部分;
为了说明的简明,各图中的各个元件没有必要按比例,且不同图中相同的参考号表示相同的元件。此外,为了简明而略去了众所周知步骤和元件的描述和细节。如此处所用的那样,电流承载电极意味着诸如MOS晶体管的源或漏、双极晶体管的发射极或收集极、或二极管的阴极或阳极之类的承载通过器件的电流的器件元件,且控制电极意味着诸如MOS晶体管的栅或双极晶体管的基极之类的控制通过器件的电流的器件元件。虽然此处器件被解释为某些N沟道或P沟道器件,但本技术领域熟练人员可以理解的是,根据本发明,互补器件也是可能的。为附图清晰起见,器件结构的掺杂区被示为具有一般直线边沿和精确的有角角落。但本技术领域熟练人员可以理解的是,由于掺杂剂的扩散和激活,掺杂区的边沿通常不是直线,且各个角落不是精确的角。
具体实施方式
图1示意地示出了双向晶体管10的电路表示,此双极晶体管10能够沿二个方向通过晶体管10传导电流,并沿跨越晶体管10的二个方向阻挡反向电压。晶体管10包括第一MOS晶体管11、第一开关或第一开关晶体管14、以及第二开关或第二开关晶体管17。如以下将要看到的那样,晶体管10还包括控制电极或栅21以及能够用作晶体管的源和漏的电流承载电极22和23。虽然此处晶体管10、11、14、17被示为N沟道晶体管,但晶体管10和晶体管11、14、17也可以是P沟道晶体管。如以下将要看到的那样,晶体管11包括被隔离于晶体管11的二个电流承载电极的本体区或本体12。为了便于双向电流传导通过晶体管10,本体12不被直接连接到晶体管11的任何一个电流承载电极,而是响应于施加在晶体管10的第一电流承载电极和第二电流承载电极上的信号,被选择性地耦合到晶体管14和17的电流承载电极22和23中的任何一个。晶体管的源典型地是连接到晶体管本体的电极。由于本体12不被直接连接到晶体管11的源或漏中的任何一个,故不清楚在晶体管10的电路示意表示中晶体管10的哪一个电流承载电极等同于晶体管10的源或漏。晶体管14的寄生源-漏二极管由二极管15示出,而晶体管17的寄生源-漏二极管由二极管18示出。
在工作中,若施加到电流承载电极22的信号电压大于施加到电流承载电极23的信号电压,则电极22用作晶体管10和11的漏,而电极23用作源。若施加到栅21的电压相对于施加到电极23的电压小于晶体管11的阈值电压,则晶体管11处于关断状态。晶体管14的栅处于低电压,于是,晶体管14也被关断。晶体管17的栅处于施加到电极22的电压。假设施加到电极22的电压大于晶体管17的阈值电压,则晶体管17被开通并将本体12耦合到电流承载电极23,从而确保本体12被连接到施加于晶体管10的最低电压。这便于晶体管10承受施加在电极22与23之间的电压。若施加到栅21的电压被改变为大于晶体管11的阈值电压,则晶体管11开通,于是,电极22上的电压基本上相同于施加到电极23的电压(减去晶体管11的Vds-on)。因此,施加到晶体管14和17的栅的电压也低,晶体管14和17因而都关断。本体12被浮置,但由于二极管18而决不会比电极23上的电压大大约0.6V以上。由于晶体管11开通,故电流能够从电极22通过晶体管11流到电极23。由于晶体管10开通,故晶体管11不会阻挡施加在电极22和23之间的电压,本体12的连接于是不重要。
若施加到电极22和23的这些信号被反向,致使最高的电压被施加到电极23而较低的电压被施加到电极22,则电极22用作晶体管10和11的源,而电极23用作漏。若施加到栅21的电压相对于施加到电极22的电压再小于晶体管11的阈值电压,则晶体管11关断。晶体管17的栅接收来自电极22的低电压,晶体管17于是关断。晶体管14的栅接收来自电极23的高电压,使晶体管14能够将本体12连接到电极22,从而连接到施加于晶体管10的最低电压。这种连接便于晶体管10承受施加在电极22和23之间的电压。若施加到栅的电压被改变成大于晶体管11的阈值电压,则晶体管11开通,从而使电流能够从电极23通过晶体管11流到电极22。由于晶体管11开通,故电极23上的电压基本上相同于施加到电极22的电压(减去晶体管11的Vds-on)。因此,施加到晶体管14和17的栅的电压也低,晶体管14和17因而关断。本体12被浮置,但由于二极管15而决不会比电极22上的电压大大约0.6V以上。由于晶体管11开通,故晶体管11不会阻挡电压,本体12的连接于是不重要。
为了协助提供晶体管10的这一功能,晶体管14的漏被共接到晶体管17的栅以及晶体管10和11的电流承载电极22。晶体管14的源被共接到本体12和晶体管17的源。晶体管17的漏被共接到晶体管14的栅以及晶体管10和11的电流承载电极23。
图2示出了图1所述晶体管10的实施方案的部分放大平面图。
图3示出了图2所示晶体管10的实施方案沿剖面线3-3的剖面部分。为图的清晰起见,剖面3-3被绘制成以一定的角度通过晶体管10,以便尽可能显示下方的特征。本技术领域的熟练人员可以理解的是,利用带角度的剖面可将下方特征显示成从直角剖面线发生了畸变,但为了图和解释的清晰起见,在图3中未示出这种畸变。此描述参照了图2和图3。在一个实施方案中,晶体管11是具有沟槽栅的N沟道垂直功率MOSFET,而晶体管14和17是横向N沟道晶体管。在此实施方案中,晶体管11具有典型地彼此横向平行延伸跨越半导体衬底35的多个沟槽栅。衬底35典型地包括本体N型衬底30和形成在本体衬底30表面上的N型外延层32。晶体管11、14、17被形成在衬底35的第一表面上。导体31被形成在衬底30的第二表面上,并用作晶体管10的部分电极23。
晶体管11包括形成在衬底35第一表面上的第一掺杂区47。掺杂区47用作晶体管11的本体12,且其导电类型与层32的导电类型相反。区域47的掺杂浓度通常大于层32的掺杂浓度,以便提供沟道区和阻挡施加到晶体管10的电压。例如当施加到电极23的电压大于施加到电极22的电压时,区域47和层32协助阻挡施加到晶体管10的反向电压。可以用峰值浓度约为每立方厘米1×1016-1×1018原子的硼来对区域47进行掺杂。区域47常常被称为pHV区。掺杂区48和掺杂区49被形成在区域47内,以方便形成对区域47的电接触。区域48和49的导电性典型地相同于区域47,且具有更高的掺杂浓度。沟槽被形成为从衬底35的表面延伸通过区域47而进入到层32中,以便形成晶体管11的沟槽型栅26、27、28。栅26、27、28通常用箭头表示。剖面线3-3仅仅切割栅26、27、28,故即使图2中晶体管11的描述示出了比栅26、27、28更多的栅,在图3中也仅仅示出了这些栅。诸如二氧化硅之类的绝缘体51沿各个沟槽的侧壁和底部被形成。沟槽的其余部分被填充以诸如多晶硅之类的栅导体52,以便形成栅26、27、28。典型地用另一部分绝缘体51来覆盖导体52。掺杂区56被形成在衬底35的表面上,并被排列在各个沟槽栅之间,以便用作晶体管11的第一电流承载电极(CCE1)。区域56的导电类型与区域47相反。可以用峰值掺杂浓度约为每立方厘米5×1019-1×1021原子的砷来对区域56进行掺杂。区域56典型地从衬底35的表面延伸通常约为0.15微米的第一距离而进入到区域47中。例如当施加到电极22的电压大于施加到电极23的电压时,高电压区被形成来协助阻挡正向电压。高电压区也称为nHV区,被形成作为掺杂区55,从衬底35的表面延伸第二距离进入区域47,典型地约为0.5微米,这大于区域56的第一距离,以便置于区域56下方。可以在区域56之前形成区域55,且区域55部分可以被过掺杂以形成区域56。区域55的掺杂浓度通常小于区域56的掺杂浓度,以便在区域47与区域55之间提供高的正向击穿电压。没有区域55的晶体管可能仅仅能够承受非常小的反向电压,典型地小于大约8V。但由于有区域55,晶体管10就能够承受大的正向电压。区域55的峰值掺杂浓度约为每立方厘米1×1016-1×1018原子,以便于晶体管10可承受至少约为15-50V的正向击穿电压。借助于改变晶体管10的其它参数,例如晶体管11的栅绝缘体厚度或栅深度,能够提高正向击穿电压。形成在区域47与层32之间界面处的P-N结,构成了图1中被示为二极管19的寄生二极管,且形成在区域55与47之间界面处的P-N结,构成了图1中被示为二极管20的另一寄生二极管。
晶体管17被形成在衬底35的表面上,且邻接晶体管11一侧。在优选实施方案中,晶体管17包括平行于区域47延伸跨越衬底35第一表面的掺杂区34(见图2)。区域34用作晶体管17的本体,其导电性典型地与层32相反。掺杂区36被形成在区域34内,且导电类型相反,以便用作晶体管17的漏。掺杂区37被形成在区域36内,且导电性相同,掺杂浓度比区域36高,以方便形成对区域36的电接触。导电类型和掺杂浓度相似于区域37的掺杂区38,被形成在区域34内并被分隔于区域36,以便用作晶体管17的源。导电类型相同于区域34的掺杂区39,被形成为邻接区域38,以便协助形成对区域34的电接触。晶体管17的栅包括形成在衬底35表面上且位于至少部分区域37和38上方的栅绝缘体42、形成在绝缘体42上方的栅导体43、以及覆盖导体43以便将导体43隔离于其它导体的介质44。
掺杂区33被形成在邻接于区域34的衬底35表面上,且典型地平行于区域34而延伸。区域33的导电类型相同于层32且掺杂浓度更高,并延伸进入到层32中,以便形成对层32的电接触。区域33便于在晶体管17的漏与晶体管11的电流承载电极23之间形成电接触。
晶体管14包括掺杂区60,掺杂区60除了平行于晶体管11的不同侧延伸之外相似于区域34。掺杂区63相似于区域36被形成为从衬底35的第一表面延伸进入到区域60中,并构成晶体管14的漏。掺杂区64相似于区域37,被形成在区域63内,以方便形成对区域63的电接触。相似于掺杂区38的掺杂区62,被形成在区域60内,并被分隔于区域63,以便用作晶体管14的源。相似于区域39的掺杂区61,被形成为邻接区域62,从而方便形成对区域60的低阻电接触。区域61、62、63、64的掺杂类型和浓度各相似于区域39、38、36、37。
导体76被形成,以便形成对区域33的电接触,并通过对区域37的电接触而形成对晶体管17的漏的电接触。诸如层间介质之类的部分介质75,将导体76隔离于衬底35的部分表面。导体76将晶体管17的漏连接到晶体管11的电极23。导体78被形成,以通过区域48形成对区域47的电接触和对区域38的电接触,以便将本体12连接到晶体管17的源。另一部分介质75将导体78隔离于衬底35的表面部分。在图2中,导体76和78用虚线框表示,以便示出晶体管10的某些下方部分。导体79延伸其上以形成对整个区域56的电接触,以便形成晶体管11的电极22。其它的部分介质75将导体79隔离于栅26、27、28。导体81被形成来构成对区域49以及区域61和62的电接触,以便在本体12与晶体管14的源之间形成电接触。另一部分介质75将导体81隔离于晶体管11和14的其它部分。导体82被形成来构成对区域64的电接触,以便形成对晶体管14的源的电连接。导体79、81、82在图2中由虚线框示出,以便示出晶体管10的某些下方部分。如图2所示,部分导体82可以延伸跨越衬底35作为导体72,以便将导体82电连接到导体79,从而电连接到晶体管11的电极22和第一电流承载电极(CCE1)以及晶体管17的栅(见图2)。此外,部分导体76可以延伸跨越衬底35以形成导体71,以便将晶体管17的漏连接到晶体管14的栅。在图2中,导体71和72由虚线示出,以便示出晶体管10的下方各部分。
如本技术领域熟练人员可以理解的那样,为了支持高的dv/dt,晶体管14和17的开态电阻应该小。晶体管14和17的开态电阻典型地小于大约25欧姆,优选小于大约5欧姆。
图4示出了双向晶体管85的实施方案的部分放大平面图,这是图1-3所述晶体管10的一个变通实施方案。
图5示出了图4所示晶体管85的实施方案沿剖面线5-5的剖面部分。此描述参照了图4和图5。晶体管85相似于晶体管10,以垂直MOS晶体管86代替了横向MOS晶体管17。垂直晶体管通常可以被形成为具有比横向晶体管更低的开态电阻。晶体管86被形成在衬底35的表面上。掺杂区94用作晶体管86的本体。区域94被形成在衬底35的表面上,基本上相同于区域47,但分隔于区域47。以相似于晶体管11的栅26、27、28的方式,形成了晶体管86的沟槽栅88、89、90。沟槽被形成通过区域94,并用相似于绝缘体51的绝缘体进行衬里。相似于导体52的栅导体,被形成在沟槽内,并被绝缘体51环绕。掺杂区93被形成在栅88与89之间以及89与90之间,从衬底35的第一表面延伸进入区域94中,以方便形成对晶体管86的本体的电接触。区域93的导电性典型地相同于区域94,但掺杂浓度更高。掺杂区92被形成在栅88与89之间以及栅89与90之间,以便用作晶体管86的源。区域92通常被形成为邻接相邻的栅,并延伸以邻接相邻的区域93。区域92通常被掺杂成导电性与区域94相反,并可以具有大约每立方厘米5×1019-5×1020原子的掺杂浓度。导体78被延伸以电接触区域92和区域93,以便将晶体管86的本体和源连接到晶体管11和85的本体12。以一般的方式如图4中虚线所示,导体82典型地延伸跨越衬底35,以便形成对晶体管85的栅的电接触。此外,掺杂区96被形成在衬底35的表面上,并延伸进入到衬底35中,以方便形成对晶体管85和11的第二电流承载电极(CCE2)的低阻电接触。区域96被形成为邻接并平行于区域60延伸,且分隔于区域60。以一般的方式如图4中虚线所示,导体97被形成来电接触区域96并延伸跨越衬底35,以便形成对晶体管14的栅的电接触。本技术领域熟练人员可以理解的是,仅仅示出了晶体管86的安置,但可以相对于晶体管11的安置而不同地安置晶体管86。
图6示出了双向晶体管100的实施方案的剖面部分,这是图1和2所述晶体管10的另一个变通实施方案。晶体管100包括协助降低晶体管100的开态电阻的埋置层101。在某些实施方案中,层32的掺杂浓度可以低,以便除了在衬底35上形成其它类型的有源和无源元件之外,还形成晶体管14和17。此轻掺杂能够提高晶体管11的开态电阻。但埋置层101被形成为具有高的掺杂浓度和位于晶体管11的沟道区下方,以便减小开态电阻。层32的峰值掺杂浓度可以不大于大约每立方厘米1×1016原子,优选为不大于大约每立方厘米1×1015原子,而层101的峰值掺杂浓度可以大于大约每立方厘米4×1016原子,优选为大于大约每立方厘米1×1016原子。埋置层101通常沿衬底30与层32的界面被形成,且延伸进入衬底30和层32二者中。可以用各种方法来形成层101,包括在形成层32之前,对衬底30的表面进行掺杂,在衬底30上形成层32,以及对衬底35进行退火,以便将掺杂剂扩散到衬底30和层32二者中。层101典型地具有至少足以位于区域47下方的长度。如虚线所示,层101也可以延伸到晶体管11最外面的栅部分即栅26和28下方,甚至还可以延伸通过栅26和28的最内边沿而达及远端边沿。
考虑到上述所有情况,显然公开了一种新颖的器件和方法。包括在所有特点中的是选择性地将本体12耦合到晶体管10的不同电极,以便容易双向阻挡施加到晶体管10的电压。在区域56下方形成nHV区域,便于承受跨越晶体管10的电压。用一个晶体管代替二个串联的晶体管,降低了双向晶体管以及采用此双向晶体管的系统的成本。使用一个晶体管还减小了开态电阻。
虽然用具体的优选实施方案描述了本发明,但显然,对于半导体技术领域的熟练人员来说,各种变通和变化是显而易见的。更具体地说,对于特定的N沟道MOS晶体管结构,已经描述了本发明,但此方法可直接应用于P沟道晶体管以及BiCMOS、金属半导体FET(MESFET)、HFET、以及其它晶体管结构。而且,晶体管11和86可以被形成为具有传统表面栅而不是沟槽栅的垂直晶体管。区域55可以仍然被用来协助阻挡反向电压。本技术领域的熟练人员可以理解的是,其它金属层也可以被用来协助形成更多的对本体区的电接触,以便减小电阻。本技术领域的熟练人员可以理解的是,各晶体管彼此的相对安置仅仅是说明性的,各个晶体管可以相对于双向晶体管其它晶体管的安置而被不同地安置。此外,为描述清晰起见而通篇采用了词语“连接的”,但其意义与词语“耦合的”相同。因此,“连接的”应该被解释为包括直接连接或间接连接。
Claims (10)
1.一种双向晶体管,包括:
第一MOS晶体管,它具有本体区、第一电流承载电极、以及第二电流承载电极;以及
开关,它被构造成响应于施加到第一MOS晶体管的源和漏的信号而选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第一电流承载电极或第二电流承载电极。
2.权利要求1的双向晶体管,其中,被构造成响应于施加到第一MOS晶体管的第一电流承载电极和第二电流承载电极的信号而选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第一电流承载电极或第二电流承载电极的开关包括第一开关晶体管,此第一开关晶体管具有耦合到本体区的第一电流承载电极、耦合到第一MOS晶体管的漏的第二电流承载电极、以及耦合到第一MOS晶体管的源的控制电极。
3.权利要求1的双向晶体管,其中,第一MOS晶体管的本体区没有到第一MOS晶体管的第一电流承载电极的直接电连接。
4.权利要求1的双向晶体管,其中,被构造成选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第一电流承载电极或第二电流承载电极的开关,包括被构造成选择性地将此本体区耦合到第一MOS晶体管的第一电流承载电极或第二电流承载电极的第二MOS晶体管以及第三MOS晶体管。
5.一种制作双向晶体管的方法,包括:
在第一导电类型的半导体衬底上形成第一MOS晶体管;
在半导体衬底的表面上形成第一MOS晶体管的本体区,并由第一P-N结隔离于第一MOS晶体管的第一电流承载电极区,且由第二P-N结隔离于第一MOS晶体管的第二电流承载电极区;以及
形成耦合的第二MOS晶体管来选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第一电流承载电极。
6.权利要求5的方法,还包括形成电耦合在第一MOS晶体管的本体区与第一MOS晶体管的第二电流承载电极区之间的第二MOS晶体管。
7.权利要求5的方法,还包括耦合的第三MOS晶体管来选择性地将第一MOS晶体管的本体区耦合到第一MOS晶体管的第二电流承载电极。
8.一种制作双向晶体管的方法,包括:
提供第一导电类型的半导体衬底;
在半导体衬底的表面上形成第二导电类型的第一掺杂区,作为第一晶体管的本体区;
在第一掺杂区内形成第一导电类型的第二掺杂区并延伸进入第一掺杂区第一距离,作为第一晶体管的第一电流承载电极区;以及
形成从第二掺杂区延伸进入第一掺杂区第二距离的第一导电类型的第三掺杂区。
9.权利要求8的方法,还包括在半导体衬底的表面上形成第二导电类型的第四掺杂区,且分隔于第一掺杂区;在第四掺杂区中形成第二晶体管的源和漏;以及将第二晶体管电耦合在第一掺杂区与半导体衬底之间。
10.权利要求9的方法,其中,在第四掺杂区中形成第二晶体管的源和漏包括:在第四掺杂区内形成第五掺杂区;在第四掺杂区内形成第六掺杂区并分隔于第五掺杂区;将第五掺杂区电耦合到第一掺杂区;以及将第六掺杂区耦合到半导体衬底。
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