CN111261698B - 一种消除电压折回现象的rc-ligbt器件 - Google Patents
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Abstract
本发明属于功率半导体技术领域,提供一种基于绝缘体上硅技术的消除电压折回现象的RC‑LIGBT器件,在传统SSA‑LIGBT器件的基础上,在集电极一侧引入一个栅源短接的N沟道MOEFET;当器件工作在正向状态时,将一直工作在IGBT模式下,完全消除了由MOS模式过渡到IGBT模式而产生的电压折回现象;当器件工作在反向状态时,随着发射极电压升高,栅漏短接的NMOS开启,器件工作于反向并联的IGBT模式,实现器件的反向导通特性;综上,本发明RC‑LIGBT器件既能完全消除电压折回现象,又兼具高可集成度、低导通压降、小器件尺寸、能够快速关断等优点;同时,器件具有更高的电流密度,降低了器件的导通压降,改善了导通压降和关断损耗之间的折中关系。
Description
技术领域
本发明属于功率半导体技术领域,具体提供一种具有低导通压降、小器件尺寸、良好开关速度,同时完全消除电压折回现象的RC-LIGBT器件。
背景技术
电力电子系统的小型化、集成化是功率半导体器件的一个重要研究方向。智能功率集成电路(Smart Power Integrated Circuit,SPIC)或高压集成电路(High VoltageIntegrated Circuit,HVIC)将保护、控制、检测、驱动等低压电路和高压功率器件集成在同一个芯片上,这样不仅缩小了系统体积,提高了系统可靠性;同时,在较高频率的工作场合,由于系统引线电感的减少,对于缓冲和保护电路而言,能够显著降低其要求。
逆导型横向绝缘双极晶体管(Reverse Conducting Lateral Insulated-GateBipolar Transisto r,RC-LIGBT)是SPIC或HVIC的核心功率器件之一,由于其具有的高可集成度,低导通压降等优点而被广泛应用。基于绝缘体上硅技术(Silicon on Insulator,SOI)的RC-LIGBT器件由于其良好的隔离特性而更是被广泛使用。然而,传统的RC-LIGBT器件在正向导通时,当阳极正向电压较小时,阳极的PN结未导通,器件工作在MOS模式;当阳极电压持续增加时,阳极PN结导通,空穴注入使得器件工作模式转换为IGBT模式,便会发生电压折回现象,严重影响器件的可靠性;所以,如何消除电压折回现象,是设计RC-LIGBT器件的关键之一。除此之外,作为双极功率器件,漂移区中大量的非平衡载流子的存在增强了漂移区电导调制效应的同时也增加了器件的关断损耗;所以,优化器件的关断损耗(Turn-offloss:Eoff)和导通压降(On-state voltage drop:Von)之间的折中关系,也是RC-LIGBT需要解决的重要问题之一。
为了消除电压折回现象,J.-H.Chul等人在文章“A fastswitching SOI SA-LIGBTwitho ut NDR region”中提出了分离式阳极短路LIGBT器件(Separated Shorted AnodeLIGBT,S SA-LIGBT)。SSA-LIGBT器件结构如图1所示,通过增大阳极N+区与阳极P+区之间的间距,增大了电子电流路径上的电阻,使其在更低的集电极电压下转换为IGBT模式,从而减小了电压折回现象带来的影响。
然而,上述传统SSA-LIGBT器件为了消除电压折回现象,阳极N+区与阳极P+区之间的间距需要足够长,这会大大增加器件尺寸,对于节省芯片面积和降低系统功耗均是不利。综上所述,如何完全消除RC-LIGBT器件中电压折回现象的问题,又不会引入诸如增大器件尺寸等问题,是设计RC-LIGBT器件的关键之一。
发明内容
本发明的目的在于针对上述传统SSA-LIGBT器件存在的问题,提供一种消除电压折回现象的SOI RC-LIGBT器件;该器件既能完全消除电压折回现象,又兼具高可集成度、低导通压降、小器件尺寸、能够快速关断等优点。
为实现上述目的,本发明采用的技术方案如下:
一种消除电压折回现象的RC-LIGBT器件,其元胞结构包括:
P型衬底1,位于P型衬底1上的埋氧层区2,位于埋氧层上的N型半导体表面耐压区6,位于N型半导体表面耐压区6中的P型半导体基区3、第一栅极区、N型半导体缓冲区9与第二栅极区;其中,所述P型半导体基区3与第一栅极区相邻接,所述N型半导体缓冲区9被第二栅极区分割为两个子区;所述第一栅极区和第二栅极区均为立体槽栅区,第一栅极区由第一栅介质层8、填充于栅介质层中的第一多晶硅栅区7及覆盖于多晶硅栅区上的栅极金属17组成,第二栅极区由第二栅介质层15、填充于栅介质层中的第二多晶硅栅区14及覆盖于多晶硅栅区上的浮空短接金属19组成;
所述P型半导体基区3中设置有相邻接的作为沟道源区的重掺杂N型半导体源区5与重掺杂的P型半导体欧姆接触区4,所述重掺杂N型半导体源区5与重掺杂的P型半导体欧姆接触区4上覆盖发射极金属16;
所述N型半导体缓冲区9的第一子区中设置有P型半导体区10,P型半导体区10中设置有重掺杂N型半导体区13,所述P型半导体区10与重掺杂N型半导体欧姆接触区13均与第二栅介质层15相接触、且两者上覆盖集电极金属18;所述N型半导体缓冲区9的第二子区中设置有重掺杂P型半导体集电区11、重掺杂N型半导体欧姆接触区12,所述重掺杂P型半导体集电区上覆盖集电极金属18,所述重掺杂N型半导体欧姆接触区12通过浮空短接金属19与第二栅极区相短接。
本发明的有益效果在于:
本发明提供一种基于绝缘体上硅技术的消除电压折回现象的RC-LIGBT器件,通过在集电极一侧引入一个栅漏短接的N沟道MOEFET;当器件工作在正向状态时,将一直工作在I GBT模式下,完全消除了由MOS模式过渡到IGBT模式而产生的电压折回现象;当器件工作在反向状态时,随着发射极电压升高,栅漏短接的NMOS开启,发射极的P区开始向耐压区注入空穴,器件工作于反向并联的IGBT模式,实现器件的反向导通特性;综上,本发明R C-LIGBT器件既能完全消除电压折回现象,又兼具高可集成度、低导通压降、小器件尺寸、能够快速关断等优点;同时,由于完全消除了电压折回现象以及小于传统结构的器件尺寸,使得器件具有更高的电流密度,降低了器件的导通压降,改善了导通压降和关断损耗之间的折中关系。
附图说明
图1为现有技术中传统SOI SSA-LIGBT结构示意图;
图2为本发明实施例提供的一种制作在SOI衬底上的消除电压折回现象的RC-LIGBT结构示意图;
图3为仿真的本发明实施例对比传统SSA-RC-LIGBT的正反向电流-电压输出特性图;
图4为仿真的本发明实施例对比传统SSA-RC-LIGBT的Von-Eoff折中关系图;
图中,1为P型衬底,2为埋氧层区,3为P型半导体基区,4为重掺杂P型半导体欧姆接触区,5为重掺杂N型半导体源区,6为N型半导体表面耐压区,7为第一多晶硅栅区,8为第一栅介质层,9为N型半导体缓冲区,10为P型半导体区,11为重掺杂P型半导体集电区,12为重掺杂N型半导体欧姆接触区,13为重掺杂N型半导体欧姆接触区,14为第二多晶硅栅区,15为第二栅介质层区,16为发射极金属,17为栅极金属,18为集电极金属,19为浮空短接金属。
具体实施方式
下面参照附图对本发明进行更全面的描述,在说明书附图中,相同的标号表示相同或者相似的组件或者元素,本发明要旨是提供一种消除电压折回现象的基于SOI的新型高压RC-LIGBT器件。
实施例1
本实施例提供的一种制作于SOI衬底上的消除电压折回现象的RC-LIGBT器件,其元胞结构如图2所示(二维示意图),包括:
P型衬底1,位于衬底1上的埋氧层区2,位于所述埋氧层上的N型半导体表面耐压区6,位于所述N型半导体表面耐压区6顶层左侧的P型半导体基区3、及与之邻接的第一栅极区,位于所述N型半导体表面耐压区6顶层右侧的N型半导体缓冲区9、及深入表面耐压区6的第二栅极区;所述表面耐压区6由恒定掺杂的或者变掺杂的N型半导体层形成,表面耐压区的N型半导体层在一侧与所述第一栅极区的栅介质层以及所述P型基区3相接触,另一侧与所述N型半导体缓冲区9、第二栅极区的栅介质层相接触;
所述第一栅极区和第二栅极区均为立体槽栅区,第一栅极区由第一栅介质层8、填充于栅介质层中的第一多晶硅栅区7及覆盖于多晶硅栅区上的栅极金属17组成,第二栅极区由第二栅介质层15、填充于栅介质层中的第二多晶硅栅区14及覆盖于多晶硅栅区上的浮空短接金属19组成;
所述P型半导体基区3中具有相邻接的重掺杂的N型半导体区5和重掺杂的P型半导体区4分别作为RC-LIGB器件沟道的源极区和基区欧姆接触区;所述源极区和基区欧姆接触区上的器件表面覆盖有发射极金属;所述P型半导体基区3、第一栅极区以及发射极金属16共同形成了RC-LIGBT器件的第一有源区;
所述N型半导体缓冲区9中被第二栅极分隔成两个子区;其中,所述被分隔的第一子区位于第二栅极右侧,与第二栅极栅介质层15相接触,内部包括P型半导体区10以及重掺杂N型半导体欧姆接触区13,并且在器件表面均被集电极金属18所覆盖;第二子区位于第二栅极左侧,与第二栅介质层15相接触,内部包括重掺杂P型半导体集电区11以及一个用于形成欧姆接触的重掺杂N型半导体区12,所述重掺杂P型半导体集电区在器件表面被集电极金属18覆盖,所述重掺杂N型半导体区在器件表面通过浮空金属19与第二栅极相短接;所述N型半导体缓冲区9、第二栅极区、重掺杂P型集电区11、重掺杂N型欧姆接触区12、重掺杂N型欧姆接触区13、P型半导体区10以及集电极金属18和浮空短接金属19共同形成第二有源区。
本发明中第二栅极与N型半导体缓冲区中的重掺杂N型欧姆接触区通过浮空金属19短接在一起,因此,本发明提出的SOI RC-LIGBT器件仍然是一个三端器件。
基于上述实施例,下面结合说明书附图对本发明工作原理进行详细说明:
与传统的RC-LIGBT相比(SSA-LIGBT),本发明主要在集电极一侧引入了额外的第二栅极以及一个P型半导体区,如图2中虚线框内所示,第二栅极区作为栅极、P型半导体区10作为衬底以及沟道区、N型半导体缓冲区9作为漏极、重掺杂N型半导体欧姆接触区13作为源极,在集电极一侧形成了一个N沟道MOEFET(命名为M),所述MOSFET的漏极与栅极通过浮空金属19短接在一起,集电极金属18作为所述MOSFET的源极金属;因此,所述MOSFET与P型半导体基区3在器件内形成了一个与原器件反并联的IGBT,原器件的发射极与集电极分别作为反并联IGBT的集电极与发射极。
当器件工作在正向导通状态时,集电极施加正向电压,由于所述MOSFET的栅源极通过金属短接并浮空,栅源电压小于所述MOSFET的阈值电压,MOSFET的沟道将不会开启,集电极重掺杂N型半导体区13将被高电阻的P型沟道区屏蔽而无法收集电子,器件将一直工作在IGBT模式下,因此便完全消除了由MOS模式过渡到IGBT模式而产生的电压折回现象。
当器件工作在反向状态时,原器件发射极施加正向电压,即所述反并联IGBT的集电极施加正向电压,随着正向电压的增加将引起N型半导体缓冲区9的电位抬升,同时由于所述N型半导体缓冲区与第二栅极区通过浮空金属短接,电位的抬升将导致第二栅极区的栅电容开始快速充电,其电位也将迅速抬升,当所述反并联IGBT的栅极与发射极之间的电位差超过其阈值电压Vth时,所述反并联IGBT将导通,从而实现器件的反向导通特性。
相比于传统的RC-LIGBT,本发明完全消除了电压折回现象,同时本发明采用引入MOS FET的沟道区而不是增大重掺杂P型集电区与重掺杂N型集电区之间的间距来增大电子电流路径上的电阻,大大减小了器件尺寸,并且提高了正向电流密度,从而有效的降低了器件的导通压降,改善了导通压降和关断损耗之间的折中关系。除此之外,通过合理控制第二栅极区的栅介质层厚度以及P型半导体区10的掺杂浓度,在反向状态下可以降低所述MOSFET的阈值电压Vth,进一步改善器件的反向导通特性。
本实施例采用的仿真器件结构参数主要设定为:SOI层厚度25μm、埋氧层厚度3μm、器件长度69μm、表面耐压区6采用恒定掺杂浓度为2.5×1014cm-3,得到的器件正反向电流-电压输出特性曲线如图3所示,得到的Von-Eoff折中曲线仿真结果如图4所示。由图3可见,本发明器件相比于传统器件完全消除了电压折回现象,并获得了更大的正向电流密度,由图4可见相比于传统器件,本发明器件在正向导通电压为3V的条件下,关断损耗降低了81.8%;在关断损耗为3mJ/cm2条件下,导通压降降低了23.4%,获得了更好的折中关系。
以上所述,仅为本发明的具体实施方式,本说明书中所公开的任一特征,除非特别叙述,均可被其他等效或具有类似目的的替代特征加以替换;所公开的所有特征、或所有方法或过程中的步骤,除了互相排斥的特征和/或步骤以外,均可以任何方式组合。
Claims (1)
1.一种消除电压折回现象的RC-LIGBT器件,其元胞结构包括:
P型衬底(1),位于P型衬底(1)上的埋氧层区(2),位于埋氧层上的N型半导体表面耐压区(6),位于N型半导体表面耐压区( 6) 中的P型半导体基区(3)、第一栅极区、N型半导体缓冲区(9)与第二栅极区;其中,所述P型半导体基区(3)与第一栅极区相邻接,所述N型半导体缓冲区(9)被第二栅极区分割为两个子区;所述第一栅极区和第二栅极区均为立体槽栅区,第一栅极区由第一栅介质层(8)、填充于第一栅介质层中的第一多晶硅栅区(7)及覆盖于第一多晶硅栅区上的栅极金属(17)组成,第二栅极区由第二栅介质层(15)、填充于第二栅介质层中的第二多晶硅栅区(14)及覆盖于第二多晶硅栅区上的浮空短接金属(19)组成;
所述P型半导体基区(3)中设置有相邻接的重掺杂N型半导体源区(5)与重掺杂P型半导体欧姆接触区(4),所述重掺杂N型半导体源区(5)与重掺杂P型半导体欧姆接触区(4)上覆盖发射极金属(16);
所述N型半导体缓冲区(9)的第一子区中设置有P型半导体区(10),P型半导体区(10)中设置有第一重掺杂N型半导体欧姆接触区(13),所述P型半导体区(10)与第一重掺杂N型半导体欧姆接触区(13)均与第二栅介质层(15)相接触、且两者上覆盖集电极金属(18);所述N型半导体缓冲区(9)的第二子区中设置有重掺杂P型半导体集电区(11)、第二重掺杂N型半导体欧姆接触区(12),所述重掺杂P型半导体集电区(11)上覆盖集电极金属(18),所述第二重掺杂N型半导体欧姆接触区(12)通过浮空短接金属(19)与第二栅极区相短接。
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006023171A1 (de) * | 2006-05-17 | 2008-01-17 | Infineon Technologies Austria Ag | Halbleiterbauelement mit lokaler Plasmaextraktion |
CN103383958A (zh) * | 2013-07-17 | 2013-11-06 | 电子科技大学 | 一种rc-igbt器件及其制作方法 |
CN103413824A (zh) * | 2013-07-17 | 2013-11-27 | 电子科技大学 | 一种rc-ligbt器件及其制作方法 |
CN106067480A (zh) * | 2016-07-26 | 2016-11-02 | 电子科技大学 | 一种双通道rc‑ligbt器件及其制备方法 |
CN106098762A (zh) * | 2016-07-26 | 2016-11-09 | 电子科技大学 | 一种rc‑igbt器件及其制备方法 |
CN106129110A (zh) * | 2016-07-26 | 2016-11-16 | 电子科技大学 | 一种双通道rc‑igbt器件及其制备方法 |
CN108389900A (zh) * | 2018-03-19 | 2018-08-10 | 电子科技大学 | 一种槽栅短路阳极soi ligbt |
CN109216435A (zh) * | 2018-08-30 | 2019-01-15 | 西安理工大学 | 一种集电极隔离逆导型绝缘栅双极型晶体管及其制备方法 |
CN110190113A (zh) * | 2019-05-16 | 2019-08-30 | 东南大学 | 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管 |
CN110400840A (zh) * | 2019-08-06 | 2019-11-01 | 电子科技大学 | 一种抑制电压回折现象的rc-ligbt器件 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4440040B2 (ja) * | 2004-08-27 | 2010-03-24 | 三菱電機株式会社 | 半導体装置 |
-
2020
- 2020-02-14 CN CN202010092691.8A patent/CN111261698B/zh active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006023171A1 (de) * | 2006-05-17 | 2008-01-17 | Infineon Technologies Austria Ag | Halbleiterbauelement mit lokaler Plasmaextraktion |
CN103383958A (zh) * | 2013-07-17 | 2013-11-06 | 电子科技大学 | 一种rc-igbt器件及其制作方法 |
CN103413824A (zh) * | 2013-07-17 | 2013-11-27 | 电子科技大学 | 一种rc-ligbt器件及其制作方法 |
CN106067480A (zh) * | 2016-07-26 | 2016-11-02 | 电子科技大学 | 一种双通道rc‑ligbt器件及其制备方法 |
CN106098762A (zh) * | 2016-07-26 | 2016-11-09 | 电子科技大学 | 一种rc‑igbt器件及其制备方法 |
CN106129110A (zh) * | 2016-07-26 | 2016-11-16 | 电子科技大学 | 一种双通道rc‑igbt器件及其制备方法 |
CN108389900A (zh) * | 2018-03-19 | 2018-08-10 | 电子科技大学 | 一种槽栅短路阳极soi ligbt |
CN109216435A (zh) * | 2018-08-30 | 2019-01-15 | 西安理工大学 | 一种集电极隔离逆导型绝缘栅双极型晶体管及其制备方法 |
CN110190113A (zh) * | 2019-05-16 | 2019-08-30 | 东南大学 | 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管 |
CN110400840A (zh) * | 2019-08-06 | 2019-11-01 | 电子科技大学 | 一种抑制电压回折现象的rc-ligbt器件 |
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