CN1825552A - 实现补偿杂质区的方法和半导体器件结构 - Google Patents
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Abstract
本发明公开了实现当栅极长度增加时产生更多补偿掺杂的补偿注入的方法和所得结构。具体地说，本发明在镶嵌工艺期间通过栅极开口实施倾斜补偿注入，以使补偿杂质的浓度随栅极长度的增加而增加。以这种方式，较长器件的阈值电压的减小远大于较短器件的阈值电压的减小，由此在不影响较短器件的阈值电压的情况下将较长器件的阈值电压减小到可接受的水平。本发明尤其适用于超陡峭倒退阱。
Description
技术领域
本发明通常涉及半导体器件制造，更具体地说，涉及实现在栅极长度增加时产生更多补偿掺杂的沟道补偿杂质区的方法和所得半导体器件结构。
背景技术
在半导体器件结构中持续关注着阈值电压的减小。一种其中阈值电压被认为对于长栅极器件来说太高的特殊结构是超陡峭倒退阱(SSRW)晶体管器件。术语“倒退阱”指使用其中阱里的最高(注入)杂质浓度位于离表面一定距离处的方法形成的阱，该方法使器件更少地受击穿的影响。术语“超陡峭”指从较低的杂质浓度向较高的浓度的过渡是相当突然的，即，杂质分布在过渡处具有超陡峭的特征。
图1和2示出了对于具有0.8V的Vdd的nFETs，阈值电压(Vtsat)对栅极长度(Lpoly)的滚降特性图。图1示出了对于480的硅厚度，并对于器件具有：无SSRW(圆圈)、具有7.96e18/cm3的杂质浓度的SSRW(正方形)和具有2.72e19/cm3的杂质浓度的SSRW(菱形)的曲线图。图2示出了对于120的硅厚度，并对于器件具有：无SSRW(圆圈)、具有1.5e19/cm3的杂质浓度的SSRW(正方形)和具有5e18/cm3的杂质浓度的SSRW(菱形)的曲线图。如图所示，当栅极长度增加时，阈值电压增加到了对一些采用SSRW的器件来说不可接受的水平。当硅变得更薄时，如图2所示，这个问题更加严重。对于基于栅极长度的SSRW器件，阈值电压的范围存在对制造具有不同尺寸器件的挑战。
如上所述，在本领域内具有对减小采用依赖于栅极长度的SSRW的器件的阈值电压的需求。
发明内容
本发明包括实现当栅极长度增加时产生更多补偿掺杂的补偿注入的方法和所得结构。具体地说，本发明在镶嵌工艺期间通过栅极开口实施倾斜补偿注入，以使补偿杂质的浓度随栅极长度的增加而增加。以这种方式，较长器件的阈值电压的减小远大于较短器件的阈值电压的减小，由此在不影响较短器件的阈值电压的情况下将较长器件的阈值电压减小到可接受的水平。本发明尤其适用于超陡峭倒退阱。
本发明的第一方面旨在实现补偿杂质区的方法，所述方法包括以下步骤：提供包括围绕栅极材料区和栅极介质的隔离物的栅极电极，所述栅极电极位于衬底中的阱之上；在所述栅极电极周围形成平面介质层；从所述栅极电极除去所述栅极材料区和所述栅极介质以形成栅极开口；实施倾斜注入进入所述栅极开口以在所述阱中形成所述补偿杂质区；以及退火以激活所述补偿杂质区。
本发明的第二方面包括半导体器件结构，所述结构包括：栅极电极，包括围绕栅极材料区和栅极介质的隔离物；超陡峭倒退阱，位于衬底中的所述栅极电极之下；以及补偿杂质区，位于超陡峭倒退阱中，其中补偿杂质区中的杂质量基于所述栅极材料区的长度。
本发明的第三方面包括形成包括补偿杂质区的栅极电极的方法，所述方法包括以下步骤：提供包括围绕栅极材料区和栅极介质的隔离物的栅极电极，所述栅极电极位于衬底中的超陡峭倒退阱之上；在所述栅极电极周围形成平面介质层；从所述栅极电极除去所述栅极材料区和所述栅极介质以形成栅极开口；实施倾斜注入进入所述栅极开口以在所述超陡峭倒退阱中形成所述补偿杂质区，以使注入的杂质量随所述栅极开口的长度增加；退火以激活补偿杂质区；以及在所述栅极开口中再形成所述栅极介质和所述栅极材料区。
本发明的上述和其它特征将从下面对本发明的实施例的更加具体的描述中变得显而易见。
附图说明
将参考下列附图详细描述本发明的实施例，其中类似标记代表类似元素，并且其中：
图1示出了一组具有第一硅厚度的器件的阈值电压对栅极长度的滚降特性图。
图2示出了一组具有第二硅厚度的器件的阈值电压对栅极长度的滚降特性图。
图3-7示出了根据本发明实现补偿杂质区的方法。
图8示出了图3-7的方法的最后一步和形成的半导体器件结构。
具体实施方式
参考附图，图3示出了根据本发明用于实现补偿杂质区的方法的最初结构。如图所示，提供的栅极电极10包括围绕栅极材料区14和栅极介质16的隔离物12。栅极电极10置于衬底22中的阱20之上。同时示出了源极-漏极区24，和基极延伸26。在一个实施例中，阱20包括如上面定义的超陡峭倒退阱。阱20中的杂质的类型和量将根据所需器件的类型而变。例如，对于nFET，阱20中的杂质是p型。在一个实施例中，超陡峭倒退阱20具有大于5.0e18/cm3的杂质浓度，虽然这没有必要。
如图4中所示，下一步包括在栅极电极10周围形成平面介质层30。平面介质层30可以通过例如二氧化硅(SiO2)(优选)或氮化硅(Si3N4)的淀积以任何常规形式形成，并通过化学机械抛光平面化。
图5示出了下一步，其中从栅极电极10除去栅极材料区14和栅极介质16(图3和4)以形成栅极开口32。在一个实施例中，栅极材料区14和栅极介质16通过实施常规的各向同性蚀刻34除去。
图6示出了下一步，其中实施倾斜注入36进入栅极开口32以在阱20中形成补偿杂质区40。可以用任何常规方式实施倾斜注入36，例如，倾斜加速度型离子注入机的盘上的衬底22。注入的材料可以根据所需类型的器件而变，例如，对于nFET，杂质应该是对阱20的p型杂质补偿的n型。观察图6，可以确定，注入的杂质量随栅极开口32的长度(L)增加。更具体地说，通过平面介质层30部分掩蔽倾斜注入36来确定栅极开口32内的注入量。对于较小的栅极开口32的长度，倾斜注入36在阱20(即，沟道区)中形成的掺杂小于对于较长的栅极开口32的长度形成的掺杂。从而，通过补偿杂质区40产生的阈值电压(Vtsat)的减小量随栅极开口32的长度增加。在一个实施例中，补偿杂质区40具有1.0e18/cm3和1.0e19/cm3之间的杂质浓度。
图7示出了下一步，其中退火44以激活补偿杂质区40。在一个实施例中，退火包括将栅极开口32暴露于激光或实施闪烁(flash)退火以最小化扩散。
最后，如图8中所示，使用常规技术再形成栅极介质16和栅极材料区14，以形成包括栅极电极110的半导体器件结构100，所述栅极电极包括补偿杂质区40。后续工艺可以包括任何公知的或后来开发的线中或线后端工艺。栅极材料区14可以包括任何公知的或后来开发的例如掺杂多晶硅、金属或金属硅化物的栅极材料。栅极介质16可以包括二氧化硅(SiO2)、氧氮化物(ON)、氮化硅(Si3N4)和/或高介电常数材料。半导体器件结构100的补偿杂质区40中的杂质量基于栅极材料区14，即，栅极开口32的长度。从而，通过补偿杂质区40产生的阈值电压(Vt)的减小量随栅极材料区14的长度增加。
尽管结合上述具体实施例描述了本发明，但显然，许多改变、修改和变化对于本领域内的技术人员来说是明显的。因此，上述本发明的实施例旨在说明，而不在限制。在不脱离如下面的权利要求所定义的本发明精神和范围的情况下，可以进行各种变化。
Claims (20)
1.一种实现补偿杂质区的方法，所述方法包括以下步骤：
提供包括围绕栅极材料区和栅极介质的隔离物的栅极电极，所述栅极电极位于衬底中的阱之上；
在所述栅极电极周围形成平面介质层；
从所述栅极电极除去所述栅极材料区和所述栅极介质以形成栅极开口；
实施倾斜注入进入所述栅极开口以在所述阱中形成所述补偿杂质区；以及
退火以激活所述补偿杂质区。
2.根据权利要求1的方法，其中在所述实施步骤期间注入的杂质量随所述栅极开口的长度增加。
3.根据权利要求1的方法，其中通过所述补偿杂质区产生的阈值电压的减小量随所述栅极开口的长度增加。
4.根据权利要求1的方法，其中所述平面介质层包括二氧化硅(SiO2)和氮化硅(Si3N4)中的一种。
5.根据权利要求1的方法，其中所述除去步骤包括实施各向同性蚀刻。
6.根据权利要求1的方法，其中所述退火步骤包括将所述栅极开口暴露于激光和实施闪烁退火中的一种。
7.根据权利要求1的方法，还包括再形成所述栅极介质和所述栅极材料区的步骤。
8.根据权利要求6的方法，其中所述栅极介质包括二氧化硅(SiO2)、氧氮化物(ON)、氮化硅(Si3N4)和高介电常数材料中的至少一种。
9.根据权利要求1的方法，其中所述阱包括超陡峭倒退阱。
10.一种半导体器件结构，包括：
栅极电极，包括围绕栅极材料区和栅极介质的隔离物；
超陡峭倒退阱，位于衬底中的所述栅极电极之下；以及
补偿杂质区，位于超陡峭倒退阱中，其中所述补偿杂质区中的杂质量基于所述栅极材料区的长度。
11.根据权利要求10的半导体器件结构，其中通过所述补偿杂质区产生的阈值电压的减小量随所述栅极材料区的长度增加。
12.根据权利要求10的半导体器件结构，其中所述超陡峭倒退阱具有大于5.0e18/cm3的杂质浓度。
13.根据权利要求10的半导体器件结构，其中所述补偿杂质区具有不小于1.0e18/cm3而不大于1.0e19/cm3的杂质浓度。
14.根据权利要求10的半导体器件结构，其中所述栅极材料区包括掺杂多晶硅、金属和金属硅化物中的一种。
15.根据权利要求10的半导体器件结构，其中所述栅极介质包括二氧化硅(SiO2)、氧氮化物(ON)、氮化硅(Si3N4)和高介电常数材料中的至少一种。
16.一种形成包括补偿杂质区的栅极电极的方法，所述方法包括以下步骤：
提供包括围绕栅极材料区和栅极介质的隔离物的栅极电极，所述栅极电极位于衬底中的超陡峭倒退阱之上；
在所述栅极电极周围形成平面介质层；
从所述栅极电极除去所述栅极材料区和所述栅极介质以形成栅极开口；
实施倾斜注入进入所述栅极开口以在所述超陡峭倒退阱中形成所述补偿杂质区，以使注入的杂质量随所述栅极开口的长度增加；
退火以激活所述补偿杂质区；以及
在所述栅极开口中再形成所述栅极介质和所述栅极材料区。
17.根据权利要求16的方法，其中通过所述补偿杂质区产生的阈值电压的减小量随所述栅极开口的长度增加。
18.根据权利要求16的方法，其中所述平面介质层包括二氧化硅(SiO2)和氮化硅(Si3N4)中的一种。
19.根据权利要求16的方法，其中所述除去步骤包括实施各向同性蚀刻。
20.根据权利要求16的方法，其中所述退火步骤包括将所述栅极开口暴露于激光和实施闪烁退火中的一种。
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| US10/905,591 US20060154428A1 (en) | 2005-01-12 | 2005-01-12 | Increasing doping of well compensating dopant region according to increasing gate length |
| US10/905,591 | 2005-01-12 |
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| CN102593172A (zh) * | 2011-01-14 | 2012-07-18 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
| WO2012094858A1 (zh) * | 2011-01-14 | 2012-07-19 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
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