CN1822393A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1822393A
CN1822393A CNA2005101359900A CN200510135990A CN1822393A CN 1822393 A CN1822393 A CN 1822393A CN A2005101359900 A CNA2005101359900 A CN A2005101359900A CN 200510135990 A CN200510135990 A CN 200510135990A CN 1822393 A CN1822393 A CN 1822393A
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丁明镇
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Abstract

本发明公开了一种半导体器件及其制造方法，其中，可在源极/漏极区之下的应变硅层之中形成绝缘层，以基本上解决半导体器件中通道减小所产生的问题。一种用于制造半导体器件的方法，可包括：在第一硅层上生长锗层；在锗层中形成至少两条沟道；在包括沟道的锗层中形成绝缘层；通过抛光锗层和绝缘层直至在沟道的底部处共面来形成至少两个栅极绝缘层图样；重新生长和平坦化锗层；在锗层上形成第二硅层；在至少两个绝缘层之间的第二硅层上形成栅极绝缘层和栅电极；以及通过向在栅电极的侧面处的第二硅层中注入杂质离子来形成源极/漏极区。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2004年12月31日提交的第P2004-117613号韩国专利申请的优先权，其全部内容结合于此供参考。
技术领域
本发明涉及一种半导体器件，更具体地，涉及一种半导体器件及其制造方法，其中，应变硅层充当有源层，以及在源极/漏极区之下的应变硅层之中或之下形成绝缘层，由此改善半导体器件的工作特性。
背景技术
通常，当将锗(Ge)设置到或沉积到硅(Si)衬底上时，可在预定温度下在硅衬底上形成锗层。然后，可在锗层上形成硅层，从而形成在Si晶格中的某些位置之间具有一定距离的应变硅层，使得沉积的Si晶格与锗层的晶格基本上相同。因此，在该应变硅层中，其晶格结构可在晶格中的硅原子之间具有更大的距离。
随着半导体器件的微型化趋势，常规的Si结构会产生有关电子和空穴的迁移率下降的问题。为了解决该迁移率问题，半导体器件的衬底可采用应变硅。
在采用了应变硅衬底的情况下，能够增大电子和空穴的迁移率，从而改善其上的半导体器件的工作特性。然而，这种半导体器件还已经最小化到了纳米级，因此可能产生诸如漏电流、漏极感应势垒下降(DIBL)、以及结击穿电压的问题。
发明内容
因此，本发明的实施例旨在提供一种半导体器件及其制造方法，其能够充分地解决由于如上所述的相关技术的局限性和缺陷所导致的一个或多个问题。
本发明的一个目的在于，提供了一种半导体器件及其制造方法，其中，在源极/漏极区之下的应变硅层之中形成绝缘层，从而能够降低漏电流和结击穿电压，与此同时，得到用于使热量相对较容易地从器件中释放的通道。因此，和常规方法相比，根据本发明的实施例的半导体器件能够工作在相对较高的电压下。
本发明的其它优点、目的、和特征将至少部分地在随后的说明中阐述，并且，对于本领域的技术人员而言，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
为了获得根据本发明的意图的这些目的和其他优点，如已概括和充分说明的，一种半导体器件可包括：(i)应变硅衬底，其包括依次形成的第一硅层、锗层、和第二硅层，其中所述应变硅衬底包括有源区和场效应区；(ii)栅电极，其形成于所述应变硅衬底的所述有源区上；(iii)源极/漏极区，其形成于所述应变硅衬底中的所述栅电极的侧面处；以及(iv)绝缘层，其形成于所述应变硅衬底之中所述源极/漏极区之下。
所述绝缘层可基本上延伸至所述源极/漏极区的耗尽点。同样，所述绝缘层可形成于或设置于所述应变硅衬底的所述锗层中。此外，所述第二硅衬底可具有约50到约250的厚度。
在另一方面中，一种半导体器件可包括：(i)应变硅衬底，其包括有序的第一硅层、锗层、和第二硅层；(ii)第一和第二栅电极，在所述应变硅衬底上；(iii)第一导电类型源极/漏极区，其在所述应变硅衬底之中的所述第一栅电极的侧面处；(iv)第二导电类型源极/漏极区，其在所述应变硅衬底之中的所述第二栅电极的侧面处；以及(v)绝缘层，其在所述第一和第二源极/漏极区之下的所述应变硅衬底中。
在又一方面中，一种用于制造半导体器件的方法，可包括以下步骤：(i)在第一硅层上生长第一锗层；(ii)在所述锗层中形成至少两条沟道；(iii)在包括所述沟道的所述第一锗层中形成绝缘层；(iv)通过抛光所述第一锗层和所述绝缘层直至在所述沟道的底部处平坦化，来形成至少两个SOI绝缘层图样；(v)重新生长和平坦化所述锗层(例如，在所抛光的第一锗层上生长第二锗层，然后平坦化所述第二锗层)；(vi)在所述第二锗层上形成第二硅层；(vii)在所述至少两个绝缘层之间的所述第二硅层上形成栅极绝缘层和栅电极；以及(viii)通过向所述栅电极的侧面处的所述第二硅层中注入杂质离子来形成源极/漏极区。
硅(Six-1)和锗(Gex)的成分比中的值X可以是从例如0.1到0.5。
应该理解，以上对本发明的一般性描述和以下的详细描述都是示例性和说明性质的，目的在于对要求保护的本发明提供进一步的说明。
附图说明
附图构成本说明书的一部分，有助于进一步理解本发明，这些附图示出了本发明的一些实施例，并可与说明书一起用来说明本发明的原理。附图中：
图1是示出根据本发明的实施例的半导体器件的剖视图；
图2A到图2G是示出用于制造根据本发明的实施例的半导体器件的工序的剖视图；以及
图3是示出根据本发明的实施例的CMOS半导体器件的剖视图。
具体实施方式
以下将详细参照本发明的优选实施例，其实例在附图中示出。尽可能地，在所有附图中使用相同的参考标号表示相同或相似的部件。
以下，将参照附图描述根据本发明的半导体器件及其制造方法。
图1是示出根据本发明的实施例的半导体器件的剖视图。如图1所示，在根据本发明的半导体器件中，应变硅衬底10可包括第一硅(Si)层3、锗(Ge)层5、以及第二硅(Si)层6。可在第一硅层3上生长锗层5，然后可在锗层5上生长第二硅层6。可在应变硅衬底10内限定有源区和场效应区。在此实例中，可在场效应区的应变硅衬底10中形成器件隔离层31。此外，可在应变硅衬底10的有源区中形成栅极绝缘层41、栅电极42、源极/漏极区44a/44b、以及绝缘层17a/17b。在有源区的应变硅衬底10的预定部分上可顺序地沉积栅极绝缘层41和栅电极42。然后，可在应变硅衬底10中的栅电极42的相对的两侧处形成源极/漏极区44a/44b。此外，可在源极/漏极区44a/44b之下的应变硅衬底10中形成绝缘层17a/17b。
在该具体实例中，绝缘层17a/17b可与器件隔离层31直接接触，并且可在应变硅衬底10的锗层5中形成绝缘层17a/17b。另外，可在栅电极42和栅极绝缘层41的侧壁上形成侧壁绝缘层43。如本领域所公知的，侧壁绝缘层43可包括氧化物(例如，二氧化硅)，氮化物(例如，氮化硅)，或二者都包括(例如，在氧化物缓冲层上的氮化硅)。
参见图2A-2F，下面将描述用于制造根据本发明的实施例的半导体器件的方法。图2A到图2F是示出用于制造根据本发明的实施例的半导体器件的工序的剖视图。
如图2A所示，可在第一硅层3上以外延生长方式形成或生长锗层5，然后可在锗层5上沉积第一绝缘层11。此时，锗层5的晶格中原子间距可能大于第一硅层3的晶格中原子间距。
作为一种通过外延生长方式在第一硅层3上形成锗层5的选择，有可能提供具有一定成分比的硅(Si1-x)和锗(Gex)的衬底，其中x是从0.1到0.5。
接下来，可在第一绝缘层11上涂覆光刻胶层，然后可通过曝光和显影去除与源极/漏极区相对应的光刻胶层，从而形成第一光刻胶图样12。
如图2B所示，可利用第一光刻胶图样12作为掩模，将第一绝缘层11和锗层5去除至预定的深度，从而形成沟道15。接下来，将第一光刻胶图样12和第一绝缘层11完全地去除。然后，可在锗层5的基本整个表面上包括沟道15的内壁上形成第二绝缘层17。可通过CVD(化学气相沉积，如本领域所公知的，诸如等离子增强[PE]-CVD或高密度等离子体[HDP]-CVD，从硅源诸如TEOS或硅烷[SiH4]，以及氧源诸如臭氧[O3]或氧[O2])或通过常规湿法或干法热氧化(其也可修复以前的蚀刻过程对锗层造成的任何损害)来形成第二绝缘层17。
如图2C所示，可通过CMP(化学机械抛光)部分地去除第二绝缘层17和锗层5，由此使锗层5和第二绝缘层17平坦化至基本上共面(例如，在沟道15的底部)。结果，可形成绝缘层图样17a/17b。
绝缘层图样17a/17b可基本上延伸至源极/漏极区的耗尽点，以增大源极/漏极区的泄漏通道，并减少结电容。可选地，可使源极/漏极区(例如图1中的44a/44b)形成为使得其耗尽点或区在绝缘层图样17a/17b上表面之上。另外，绝缘层图样17a/17b之间的空隙(例如，绝缘层不连续)可有助于源极区与漏极区之间产生的热量相对较容易地释放。
如图2D所示，当例如通过外延生长在包括绝缘层图样17a/17b的衬底上重新生长锗层5(例如，形成第二锗层)之后，由于锗层5在绝缘层图样17a/17b上面或上方的部分可能在重新生长锗层5的过程中或由于重新生长该锗层而相对较薄，所以可通过CMP来平坦化锗层5。
如图2E所示，可在平坦化的锗层5上形成第二硅层6。第二硅层6可具有约50到约250的通过外延生长的厚度，从而形成包括依次沉积的第一硅层3、锗层5、和第二硅层6的应变硅衬底10。第二硅层6的晶格原子间距基本上等于锗层5的晶格原子间距。
如图2F所示，应变硅衬底10可包括限定的有源区和场效应区。在此实例中，可将场效应区的应变硅衬底10蚀刻至预定深度，从而形成沟道。此外，可在沟道中形成或沉积绝缘层，由此可在适当的平坦化(如通过CMP)之后形成器件隔离层31。然后，可在包括器件隔离层31的应变硅衬底10上顺序地沉积或生长用于栅极绝缘的绝缘层41a和导电层42a。
如图2G所示，可选择性地去除用于栅极绝缘的绝缘层41a和导电层42a，从而形成栅极绝缘层41和栅电极42。栅极绝缘层41和栅电极42每个的宽度均可对应于晶体管的通道宽度。即，栅极绝缘层41和栅电极42每个的宽度均可大于绝缘层图样17a/17b之间的距离，从而源极/漏极区的耗尽点基本上被绝缘层图样17a/17b覆盖。因此，可增大漏电流的相关泄漏通道。因而，根据一些实施例，栅电极42可与绝缘层图样17a/17b重叠。
接下来，在利用栅极绝缘层41和栅电极42作为掩模的情况下可注入轻掺杂质离子，从而在应变硅衬底10中的栅电极42的两侧处形成轻掺漏极(LDD)区23a/23b。
然后，可在衬底10的基本整个表面上沉积绝缘层，然后可各向异性地蚀刻所沉积的绝缘层，从而在栅电极42和栅极绝缘层41的侧面形成隔离物43。此后，通过利用栅电极42和隔离物43作为掩模，可将重掺杂质离子注入应变硅衬底10的有源区，从而形成源极/漏极区44a/44b。
参照图3，根据本发明的实施例的半导体器件可应用到典型的CMOS类型结构。在根据本发明的实施例的典型的CMOS型半导体器件中，应变硅衬底100可包括第一硅(Si)层13、锗(Ge)层15、以及第二硅(Si)层16。例如，可在第一硅层13上形成或者生长锗层15，然后可在锗层15上形成或者生长第二硅层16。另外，如图所示，可在应变硅衬底100的预定部分上形成NMOS栅极绝缘层142a、NMOS栅电极141a、PMOS栅极绝缘层141b、以及PMOS栅电极142b。
然后，可在应变硅衬底100中的NMOS栅电极141a两侧处形成重掺n型源极/漏极区144a。此外，可在应变硅衬底100中的PMOS栅电极142b两侧处形成重掺p型源极/漏极区145b。然后，可在n型源极/漏极区144a和p型源极/漏极区145b之下的应变硅衬底100中形成绝缘层117a/117b。
可在应变硅衬底100的锗层15中形成绝缘层117a/117b，其中，绝缘层117a/117b可向着通道延伸，以覆盖源极/漏极区144a和145b的耗尽点。
根据本发明的各种实施例，即使是典型的CMOS晶体管，也能够获得相对较高的电子迁移率，有效地取消了形成另外的n型阱和p型阱的必要。这样，根据本发明的实施例，不必在NMOS和PMOS晶体管之间设置器件隔离层。
如上所述，本半导体器件及其制造方法具有以下优点。首先，绝缘层可在源极/漏极区之下的应变硅衬底之中形成。结果，有关微型半导体器件的电子和空穴迁移率下降的问题能被减少或最小化。此外，由此形成的半导体器件的尺寸相对于常规的方法可最小化，并能够使由于通道变小所产生的漏电流减小或最小化。根据本发明的实施例的实施，发现饱和激励电流提高了大约20％至40％。
此外，根据实施例，通过减少泄漏电流，可发现漏极感应势垒(DIBL)和结击穿电压下降。这样，可实现纳米级的半导体器件，以及同常规技术制造的半导体器件相比能工作在相对较高电压下的半导体器件。而且，根据某些实施例，电子迁移率能比常规方法提高超过50％，从而提高了半导体器件的效率。
对于CMOS半导体器件，可省去常规的用于形成n型阱(N阱)和p型阱(P阱)的程序，从而提高了生产率并降低了单位制造成本。另外，根据实施例，源极区与漏极区之间产生的热量可被绝缘层之间的空隙(比如，绝缘层不连续)相对较容易地释放掉，以使得半导体器件的效率不会由于热而降低。而且当形成这种CMOS半导体器件时，不必在NMOS与PMOS晶体管之间设置器件隔离层。从而能够使半导体器件的总体尺寸相比传统方法制造的半导体器件减小或最小化。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

1.一种半导体器件，包括：
应变硅衬底，其包括有序的第一硅层、锗层、和第二硅层，其中所述应变硅衬底包括有源区和场效应区；
栅电极，位于所述应变硅衬底的所述有源区上；
源极/漏极区，位于所述应变硅衬底之中的所述栅电极的侧面处；以及
绝缘层，位于所述源极/漏极区之下的所述应变硅衬底中。
2.根据权利要求1所述的半导体器件，还包括隔离物，其位于所述栅电极的侧壁处。
3.根据权利要求1所述的半导体器件，其中所述绝缘层至少延伸到所述源极/漏极区的耗尽点。
4.根据权利要求1所述的半导体器件，其中所述绝缘层在所述应变硅衬底的所述锗层中。
5.根据权利要求1所述的半导体器件，其中所述第二硅衬底具有约50到约250的厚度。
6.根据权利要求1所述的半导体器件，还包括器件隔离层，其在所述应变硅衬底中的所述场效应区中。
7.根据权利要求6所述的半导体器件，其中所述器件隔离层与所述绝缘层相接触。
8.根据权利要求1所述半导体器件，其中所述绝缘层包括在第一源极/漏极区之下的第一部分和在第二源极/漏极区之下的第二部分，以及所述应变硅衬底的一部分在所述绝缘层的所述第一部分和第二部分之间。
9.一种半导体器件，包括：
应变硅衬底，其包括有序的第一硅层、锗层、和第二硅层；
第一和第二栅电极，位于所述应变硅衬底上；
第一导电类型源极/漏极区，位于所述应变硅衬底之中的所述第一栅电极的侧面处；
第二导电类型源极/漏极区，位于所述应变硅衬底之中的所述第二栅电极的侧面处；以及
绝缘层，位于所述第一和第二源极/漏极区之下的所述应变硅衬底中。
10.根据权利要求9所述的半导体器件，其中所述绝缘层至少延伸至所述第一和第二源极/漏极区的耗尽点。
11.根据权利要求9所述的半导体器件，其中所述绝缘层在所述应变硅衬底的所述锗层中。
12.根据权利要求9所述的半导体器件，其中所述第二硅层具有约50到约250的厚度。
13.根据权利要求9所述的半导体器件，其中所述绝缘层包括在所述第一源极/漏极区之下的第一部分和在所述第二源极/漏极区之下的第二部分，以及所述应变硅衬底的多个部分夹在所述绝缘层的各所述第一部分之间和所述绝缘层的各第二部分之间。
14.一种用于制造半导体器件的方法，包括以下步骤：
在第一硅层上生长锗层；
在所述锗层中形成至少两条沟道；
在包括所述沟道的所述锗层中形成绝缘层；
通过抛光所述锗层和所述绝缘层直至在所述沟道的底部处共面，来形成至少两个绝缘层部分；
重新生长和平坦化所述锗层；
在所述锗层上形成第二硅层；
在所述至少两个绝缘层部分之间的所述第二硅层上形成栅极绝缘层和栅电极；以及
通过向所述栅电极的侧面处的所述第二硅层中注入杂质离子来形成源极/漏极区。
15.根据权利要求14所述的方法，其中硅Si1-x和锗Gex以一定的成分比存在，其中X是约0.1到约0.5。
16.根据权利要求14所述的方法，其中所述至少两个绝缘层图样至少延伸至所述源极/漏极区的耗尽点。
17.根据权利要求14所述的方法，其中所述第二硅层具有约50到约250的厚度。
18.根据权利要求14所述的方法，所述栅电极与所述至少两个栅极绝缘层部分相重叠。
19.一种用于制造半导体器件的方法，包括以下步骤：
在第一硅层上的第一锗层之上或之中形成至少两个绝缘层部分。
在所抛光的锗层上生长第二锗层，并平坦化所述第二锗层；
在所述锗层上形成第二硅层；
在所述至少两个绝缘层部分之间的所述第二硅层上形成栅绝缘层和栅电极；以及
通过向在所述栅电极的多个相对的侧面处的所述第二硅层中注入杂质离子来形成源极/漏极区。
20.根据权利要求19所述的方法，其中所述栅电极与所述至少两个栅极绝缘层部分重叠，以及所述至少两个栅极绝缘层部分被形成为使所述第一锗层的一部分在所述至少两个栅极绝缘层部分之间。
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