CN1783469A - 集成电路晶片结构 - Google Patents
集成电路晶片结构 Download PDFInfo
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- CN1783469A CN1783469A CNA2005101173494A CN200510117349A CN1783469A CN 1783469 A CN1783469 A CN 1783469A CN A2005101173494 A CNA2005101173494 A CN A2005101173494A CN 200510117349 A CN200510117349 A CN 200510117349A CN 1783469 A CN1783469 A CN 1783469A
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- integrated circuit
- conductive plate
- weld pad
- solid conductive
- circuit die
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- Engineering & Computer Science (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
本发明提供一种集成电路晶片结构,包括一焊垫结构、一低介电常数层及主动电路。焊垫结构包含了一焊垫,一第一实心导电板,及一第二实心导电板。第一实心导电板位于焊垫的下方且与焊垫导通。第二实心导电板位于第一实心导电板下方。一低介电常数层或低介电常数层与二氧化硅层的组合位于焊垫结构下方。至少部分的主动电路位于焊垫结构的下方。本发明所述集成电路晶片,具有良好的结合能力,且其制程步骤相对于已知技术有较低的成本,以及其较易转换至设计规则。
Description
技术领域
本发明有关于一种集成电路晶片的焊垫结构及金属化层。
背景技术
在晶圆封装中常常通过金属线(如金或铝导线)来连接集成电路与导线架或基底,以完成信号交换的功能。一般利用热压(thermal compression)或超音波振荡(ultrasonic vibration)将金属导线与集成电路晶片上的焊垫连接。在金属导线连接制程(bonding process)中,会对焊垫及焊垫下的结构施加热压及机械压力,因此焊垫必须能承受所施加的压力,以确保金属导线的连接品质。
在现有技术中,焊垫是由底层向顶层依序制造,这样的制造方式会使得金属导线及半导体元件无法穿过至焊垫结构下或置于焊垫结构之下。为了更有效的利用晶片面积或缩小晶片尺寸,需设法将半导体元件及金属导线置于焊垫下,有时将其称为BOAC(bond over active circuits)。然而,在许多制程中利用低介电及超低介电材料当作金属间介电层(IMD),来降低阻容迟滞(RC delay)或寄生电容。在一般的金属间介电层的设计中,介电常数倾向由顶层往基底递减。然而随着介电常数的减少,介电材料的强度也跟着递减。许多低介电常数的材料容易产生破裂,尤其在一些机械式的制程中(例如:金属线连接或化学机械研磨)缺乏支撑强度,因此需要一种适用于以低介电常数材料作为金属间介电层的焊垫结构,能有效分散导线连接制程所产生的压力,以及可将导线及元件形成于焊垫之下。
发明内容
有鉴于此,本发明的目的就在于解决上述的需求及问题。
本发明提供一种集成电路晶片,包含一焊垫结构,一低介电常数层及一主动电路。焊垫结构包括一焊垫、一第一实心导电板及一第二实心导电板。第一实心导电板位于焊垫之下,且与焊垫导通。第二实心导电板位于第一实心导电板之下。低介电常数层位于焊垫之下。至少部分主动电路置于焊垫之下。
本发明所述的集成电路晶片结构,该第一实心导电层与该第二实心导电层皆具有一顶部形状、且该第二实心导电层面积不小于该第一实心导电层面积的60%。
本发明所述的集成电路晶片结构,该焊垫具有一顶部形状,且该第一实心导电层面积大于或小于该焊垫面积。
本发明所述的集成电路晶片结构,该第一实心导电层面积小于200μm×200μm。
本发明所述的集成电路晶片结构,第一焊垫结构更进一步包括:介于该第一实心导电层与该第二实心导电层间的多个导电插塞,以导通第一及第二实心导电层。
本发明所述的集成电路晶片结构,该导电插塞具有一小于约1μm的宽度。
本发明所述的集成电路晶片结构,更包括置于该焊垫与该主动电路间的多层介电层。
本发明所述的集成电路晶片结构,该焊垫中具有至少一边角大于或等于90度。
本发明所述的集成电路晶片结构,更包含一第二焊垫结构,其中无主动电路置于该第二焊垫结构之下。
本发明所述的集成电路晶片结构,该第二焊垫结构包括一第二焊垫以及一置于该第二焊垫之下的非实心导电部分。
本发明所述的集成电路晶片结构,该第二焊垫结构包含一置于该第二焊垫且相邻于该非实心导电部分的非导电部分,该非导电部分的尺寸小于约200μm×200μm。
本发明所述的集成电路晶片结构,该非实心导电部分包含一狭缝。
本发明所述的集成电路晶片结构,该非实心导电部分包含一空洞。
本发明另提供一种集成电路晶片,包含一焊垫结构,一低介电层及主动电路。焊垫结构包括一焊垫、一第一实心导电板及一第二实心导电板。第一实心导电板位于焊垫之下且与焊垫导通。第一导电板顶部表面具有一形状。第二实心导电板位于第一导电板之下。第二导电板顶部表面具有一形状,且其表面积不小于第一导电板表面积的60%。低介电常数层位于焊垫之下。至少部分主动电路置于焊垫之下。
本发明还提供一种集成电路晶片,其中包含一焊垫结构,一低介电层及主动电路。焊垫结构包含一焊垫、第一实心导电板及第二实心导电板。第一导电板位于焊垫之下,且与焊垫导通。第二实心导电板位于第一导电板之下。低介电常数层位于焊垫之下。至少部分主动电路置于焊垫之下。在第二焊垫结构下无主动电路。
本发明所述集成电路晶片,具有良好的结合能力,且其制程步骤相对于已知技术有较低的成本,以及其较易转换至设计规则。
附图说明
图1显示包含本发明实施例的集成电路晶片表面图;
图2显示图1中A部分的放大图;
图3显示第一实施例中焊垫结构的截面图;
图4显示焊垫结构中第一导电板的顶部平面图;
图5显示焊垫结构中第二导电板的顶部平面图;
图6显示第二实施例中焊垫结构的截面图;
图7显示在第一导电板及第二导电板间导电插塞的顶部平面图;
图8显示图1中B部分的放大图;
图9显示第三实施例中两种不同焊垫结构的截面图;
图10显示第三实施例中两焊垫结构的第一导电板的顶部平面图;
图11显示第三实施例中两焊垫结构第二导电板的顶部平面图;
图12显示第四实施例中两焊垫结构第二导电板的顶部平面图;
图13显示第五实施例中两焊垫结构的截面图。
具体实施方式
为了让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图示,作详细说明如下:
本发明实施例提供一种集成电路中焊垫结构的改善方式,以及更好的结构设计,将至少部分的集成电路或主动电路置于焊垫结构的下方,这样可使晶片的使用面积(real estate)最大化或有效的缩小晶片的尺寸。在此将详述本发明实施例应用于导线接合(wire bonding)或焊球封装BGA(bump grid array),也可将本发明实施例应用在其他领域中。
图1至图5为本发明的第一实施例,图6及图7为本发明的第二实施例,图8至图11为本发明的第三实施例,图12为第四实施例,最后图13显示本发明的第五实施例。
如图1至图5为本发明第一实施例中各种角度的示意图,其中较特别的是,图1为包含本发明实施例的集成电路晶片的平面图。图2为图1中A部分的放大图。图3为第一实施例中焊垫结构22的截面图。第四图显示第一实施例中焊垫结构22内第一实心导电板的顶部平面图。图5显示焊垫结构22中第二实心导电板的顶部平面图。
如图1所示,以虚线所界定的主动电路区域36来表示置于顶部表面34之下的主动电路。在图1中只显示部分焊垫,如31及32,其余的以椭圆点38来表示。其中只有部分焊垫结构超出主动电路区域的范围,在后面会作更详尽的描述。在本发明的其他实施例中(未描述)焊垫的数量及分布会不同于图1中的晶片20。虽然图1中所有焊垫31及32都具有相同的形状及尺寸,但是在其他实施例中焊垫可具有不同的形状及尺寸。图2显示第一图中A部分中的焊垫31,其具有本发明第一实施例中的焊垫结构22。图3显示图2中焊垫31焊垫结构的截面图。焊垫结构22包含焊垫31及保护层40,虽然图中保护层显示为单层结构,但在实际应用中,保护层可为数种材料组成的多层结构。同样地,焊垫31虽然显示为单层结构,但在实际应用中,也可为数种材料组成的多层结构。
一般而言,焊垫31的尺寸通常小于100μm×100μm,但在其他实施例中焊垫31可为各种形状或各种尺寸大小。在较佳的实施例中,如图2所示,焊垫31中至少一边角区域42的边角大于或等于90度,如图2所示。这种形状相对于长方形降低了在连接制程中,在边角区域42应力的提高。因此在较佳实施例中,焊垫中至少有一边角无焊垫材料。焊垫边角的增加或边角具有一曲率,可降低焊垫31应力集中的现象。焊垫31的材料包含了各种不同的导电材料,如:铝、金、银、镍、铜、钨、钛、钽、复合物、多层结构、合金或化合物。
图3显示第一实施例中的焊垫结构22,于焊垫31之下具有一第一导电板48,且与焊垫31导通,而在其他实施例中(未显示),于焊垫31及第一导电板间可具有多层结构。图4显示焊垫结构22中第一导电板48顶部平面图。在本发明第一实施例中,第一导电板具有一可大于或小于焊垫31表面积的顶部区域,可使得在连接制程中在焊垫上产生的应力均匀分布。而在其他实施例中第一导电板表面积可小于焊垫的表面积。在一较佳实施例中,焊垫结构22中的第一导电板的顶部面积小于200μm×200μm。
在第一实施例中的第一导电板48为一具有凹痕边角区域50的长方形,因此边角区域50内的边角52大于90度。这种形状可降低连接制程中在边角区域50应力集中的现象。在第一实施例中,具有一连接线54,延伸自第一导电板48且提供一导电连结。在其他实施例中,第一导电板48可具有多个延伸出的连接线,也可不具连接线。第一导电板48的顶部表面可依不同实施例的需求来改变其形状。第一导电板48材料一般为铜,也可为各种不同的导电材料,如:铝、金、银、镍、铜、钨、钛、钽、复合物、合金、化合物或多层结构。如图4所示,第一导电板介电材料56至少围绕部分第一导电板48。
如图3所示,第二实心导电板58置于第一导电板48之下,且两导电板间具有一介电层60。介电层60的较佳材料为未掺杂硅玻璃,可在焊垫结构22中提供一适当的强度。在其他实施例中,可利用其他的低介电常数材料来形成导电板间介电层60。虽然导电板间介电层如图示中为一单层结构,但在实际应用中可为数种材料组成的多层结构。图5显示焊垫结构22中第二实心导电板58的顶部平面图,在第一实施例中的第二实心导电板58为一具有凹痕的边角区域62的长方形,实质上与第一实心导电板48相同(但不具有连接线54),因此边角区域62内的边角64大于90度。这种形状可降低连接制程中在转角62应力集中的现象。在第一实施例中的第二实心导电板58的主要功能为增加结构强度,因此不与结构中其他部分导通。在其他实施例中,第二实心导电板可延伸出多条导线连接主动电路或接地电压,也可与第一导电板48或焊垫31导通。第二导电板58顶部表面的形状可依不同实施例的需求作改变。第二导电板58材料一般为铜,也可为各种不同的导电材料,如:铝、金、银、镍、铜、钨、钛、钽、复合物、合金、化合物或多层结构。如图5所示,第二实心导电板介电材料67至少围绕部分第二实心导电板58。
在较佳实施例中,第二导电板58的顶部面积不小于第一导电板48的顶部面积的60%。在其他实施例中,第二导电板的顶部面积可小于第一导电板的顶部面积的60%。在本发明的第一实施例中,第二导电板的顶部面积与第一导电板的顶部面积大约相等(不包括连接线54的部分)且两者形状也相同(不包括连接线54的部分)。将第二导电板的顶部面积控制在不小于第一导电板的顶部面积的60%,因此可均匀分散连接制程中焊垫上产生的压力。
如图3所示,一或多层金属间介电层(IMD)形成于第二导电板58之下,金属间介电层一般包括导线、插塞(vias)或连接主动电路72的导线(未显示)。主动电路72一般形成在半导体基底74之内或之上。主动电路以长方形显示以简化图示,主动电路包含多种不同的电子元件,例如:存储单元(memory cell)、逻辑元件、放大器(amplifier)、电源转换器(power converters)、磁穿隧接面元件(magnetic tunnel junction devices)、二极管、晶体管、电阻、电容、电感、电源总线以及上述元件的组合。金属间介电层70包括一或多层介电常数小于4的低介电常数材料,且其介电常数一般小于二氧化硅。低介电常数材料相对于二氧化硅为多孔性、质地较软且强度较弱,通常具有较高的热膨胀系数及相较于邻近结构其热传导性较低。介电材料的结构强度随介电常数的减少而降低,然而在实际应用中,又需要低介电常数来降低阻容迟滞(RC delay)及寄生电容,因此较佳的金属间介电层材料包括:介电常数小于3的介电材料或介电常数小于2.5的介电材料,其中低介电常数材料包括:硅、碳、氮、氧、多孔性材料以及上述材料的结合。在焊垫结构中第一导电板48与第二导电板58的结合,有助于降低及有效控制在连接制程中应力集中的问题延伸至金属间介电层70中的下层低介电常数层及主动电路中。因此在本发明的实施例中可将至少部分的主动电路72置于焊垫31之下,同时在金属间介电层70中使用低介电常数材料。
图1、图2及图4至图7显示本发明中第二实施例的图示。图6显示第二实施例中焊垫结构22的截面图。除了第一及第二实心导电板间的导电插塞78外,第二实施例的焊垫结构实质上与第一实施例(图1至图5)相同,换句话说第二实施例为第一实施例的应用变化,因此第二实施例可取代或结合第一实施例。第二实施例中的第一导电板48及第二导电板58可与第一实施例相同或作改变。
图7显示第一导电板48及第二导电板58间导电插塞78的截面图,导电插塞78可为各种适合的导电材料,包括:铝、金、银、镍、铜、钨、钛、钽、复合物、合金、化合物或多层结构。在较佳的实施例中,第一导电板48可通过导电插塞78与第二导电板58导通。在其他实施例中,第一导电板48可通过导电插塞78隔绝第二导电板58(例如以非导电材料隔开)。在较佳实施例中,至少部分导电插塞78宽度小于1μm。在第二实施例中,第二导电板58可透过导电插塞78仅仅与第一导电板48导通,也就是说第二导电板58与导电插塞主要是用来增加结构强度。因此导电插塞并无实质的导通功能。在另一实施例中(未显示),第一导电板48不具延伸出的连接线54,但第二导电板则具有延伸出的连接线,因此导电插塞78可在焊垫31及第二导电板58间形成一电性连接。值得注意的是,在其他实施例中导电插塞的数量、形态及配可不同于图6及图7。
图1及图8至图11显示本发明第三实施例不同角度的示意图,其中图8为图1中B部分的放大图,图9显示第三实施例中两种不同焊垫结构22及82的截面图,图10显示焊垫结构22及82中第一导电板的顶部平面图,而图11则为焊垫结构22及82中第二导电板的顶部平面图。
第三实施例的特征在于一集成电路晶片20中至少一主动电路72的一部分置于焊垫结构之下,以及第二焊垫结构82之下无主动电路。在本发明的一些实施例中(未显示),可将整个焊垫结构置于主动电路之上。如图9所示,在第三实施例中第一焊垫结构22置于主动电路72之上,而第二焊垫结构82置于主动电路区域36之外。在其他实施例中(未显示),将部分或全部的焊垫结构置于主动电路区域36之外,如同将部分或全部焊垫结构置于主动电路区域36之上(至少部分结构在主动电路之中)。
图9中的焊垫结构22本质上与上述第一实施例中的焊垫结构相同。在第二焊垫结构82中包含了一第一导电板84及一第二导电板86。在第三实施例中,第二焊垫结构82中的第一导电板84为一实心导电板,而焊垫结构82中的第二导电板为一非实心导电板。在其他实施例中,第一导电板84与第二导电板86将有别于第三实施例中的导电板(如图10及图11所示之)。图10显示第一焊垫结构22及第二焊垫结构82中的第一导电板48及84的顶部平面图。图11显示第一焊垫结构22及第二焊垫结构82中的第二导电板58及86的顶部平面图。如图9及图11所示,一非导电部分88置于焊垫32之下且相邻于第二焊垫结构82中的非实心导电部分86,其中非导电部分88的材料可与环绕非实心导电部分86的介电材料相同,且非导电部分88的表面积小于200μm×200μm。
图1、图8至图10及图12显示本发明第四实施例中各种角度的示意图。除了在第四实施例焊垫结构82中形成在第二导电板86内的狭缝90之外,第四实施例中焊垫结构22及82本质上与上述第三实施例中的焊垫结构相同。图12显示第四实施例中焊垫结构22及82第二导电板的顶部平面图。因此,第四实施例中第二焊垫结构82可取代或结合第三实施例中的第二焊垫结构82来使用。在第四实施例中,第一焊垫结构22的第一导电板48及第二导电板58可与第三实施例中的导电板相同。
图1、图8、图10、图11及图13显示本发明第五实施例不同角度的示意图。除了于第一导电板48及84与第二导电板58及86之间加入一导电界层窗78及92,第五实施例中的焊垫结构22及82本质上与第三实施例中的焊垫结构相同。图13显示第五实施例中两焊垫结构22及82的截面图。第五实施例中的焊垫结构22及82可取代或结合第三实施例中的焊垫结构22及82使用。第五实施例中第一导电板48及84与第二导电板58及86可通过结构上的组合来产生相同或不同于第三及第四实施例中的导电板。
本发明的实施例中,可加入一额外的缓冲层(未显示)于焊垫结构22及82中。可将上述任何实施例作适当的结合使用。本发明实施例的优点包括:(1)良好的结合能力。(2)制程步骤相对于已知技术有较低的成本,以及较易转换至设计规则。
虽然本发明已通过较佳实施例说明如上,但该较佳实施例并非用以限定本发明。本领域的技术人员,在不脱离本发明的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
集成电路晶片:20、22、32、82
焊垫结构:22、82
顶部表面:34
保护层:40
第一导电板:48、84
边角区域:50、62
边角:52、64
连接线:54
第一导电板介电材料:56
第二导电板介电材料:67
第二导电板:58、86
金属间介电层:60、70
主动电路:72
半导体基底:74
导电插塞:78
非导电部分:88
狭缝:90
Claims (13)
1.一种集成电路晶片结构,其特征在于,所述集成电路晶片结构包括:
一第一焊垫结构,包括一焊垫、一置于该焊垫下且与该焊垫导通的第一实心导电层以及一置于该第一实心导电层之下的第二实心导电层;
一低介电常数层置于该焊垫之下;以及
一主动电路,至少部分置于该焊垫之下。
2.根据权利要求1所述的集成电路晶片结构,其特征在于,该第一实心导电层与该第二实心导电层皆具有一顶部形状、且该第二实心导电层面积不小于该第一实心导电层面积的60%。
3.根据权利要求2所述的集成电路晶片结构,其特征在于,该焊垫具有一顶部形状,且该第一实心导电层面积大于或小于该焊垫面积。
4.根据权利要求3所述的集成电路晶片结构,其特征在于,该第一实心导电层面积小于200μm×200μm。
5.根据权利要求1所述的集成电路晶片结构,其特征在于,第一焊垫结构更进一步包括:介于该第一实心导电层与该第二实心导电层间的多个导电插塞,以导通第一及第二实心导电层。
6.根据权利要求5所述的集成电路晶片结构,其特征在于,该导电插塞具有一小于1μm的宽度。
7.根据权利要求1所述的集成电路晶片结构,其特征在于,更包括置于该焊垫与该主动电路间的多层介电层。
8.根据权利要求1所述的集成电路晶片结构,其特征在于,该焊垫中具有至少一边角大于或等于90度。
9.根据权利要求1所述的集成电路晶片结构,其特征在于,更包含一第二焊垫结构,其中无主动电路置于该第二焊垫结构之下。
10.根据权利要求9所述的集成电路晶片结构,其特征在于,该第二焊垫结构包括一第二焊垫以及一置于该第二焊垫之下的非实心导电部分。
11.根据权利要求10所述的集成电路晶片结构,其特征在于,该第二焊垫结构包含一置于该第二焊垫且相邻于该非实心导电部分的非导电部分,该非导电部分的尺寸小于200μm×200μm。
12.根据权利要求10所述的集成电路晶片结构,其特征在于,该非实心导电部分包含一狭缝。
13.根据权利要求10所述的集成电路晶片结构,其特征在于,该非实心导电部分包含一空洞。
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US10/989,481 US20060091566A1 (en) | 2004-11-02 | 2004-11-16 | Bond pad structure for integrated circuit chip |
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US7592710B2 (en) * | 2006-03-03 | 2009-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure for wire bonding |
US20080003804A1 (en) * | 2006-06-29 | 2008-01-03 | Ravi Nalla | Method of providing solder bumps of mixed sizes on a substrate using solder transfer in two stages |
EP2568498A3 (en) * | 2007-10-31 | 2013-04-24 | Agere Systems Inc. | Bond pad support structure for semiconductor device |
US8178980B2 (en) * | 2008-02-05 | 2012-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure |
US8581423B2 (en) * | 2008-11-17 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double solid metal pad with reduced area |
US8680681B2 (en) * | 2011-08-26 | 2014-03-25 | Globalfoundries Inc. | Bond pad configurations for controlling semiconductor chip package interactions |
US9553040B2 (en) * | 2012-03-27 | 2017-01-24 | Mediatek Inc. | Semiconductor package |
EP4035586A1 (en) | 2015-04-16 | 2022-08-03 | Gentuity LLC | Micro-optic probes for neurology |
EP3344126A4 (en) | 2015-08-31 | 2019-05-08 | Gentuity LLC | IMAGING SYSTEM COMPRISING IMAGING PROBE AND DELIVERY DEVICES |
DE102017210654B4 (de) * | 2017-06-23 | 2022-06-09 | Infineon Technologies Ag | Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst |
US10896885B2 (en) * | 2017-09-13 | 2021-01-19 | Polar Semiconductor, Llc | High-voltage MOSFET structures |
WO2019108598A1 (en) | 2017-11-28 | 2019-06-06 | Gentuity, Llc | Imaging system |
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US5700735A (en) * | 1996-08-22 | 1997-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bond pad structure for the via plug process |
US6144100A (en) * | 1997-06-05 | 2000-11-07 | Texas Instruments Incorporated | Integrated circuit with bonding layer over active circuitry |
KR100267105B1 (ko) * | 1997-12-09 | 2000-11-01 | 윤종용 | 다층패드를구비한반도체소자및그제조방법 |
US6043144A (en) * | 1998-05-25 | 2000-03-28 | United Microelectronics Corp. | Bonding-pad structure for integrated circuit and method of fabricating the same |
US6232662B1 (en) * | 1998-07-14 | 2001-05-15 | Texas Instruments Incorporated | System and method for bonding over active integrated circuits |
US6734093B1 (en) * | 1999-03-17 | 2004-05-11 | Intel Corporation | Method for placing active circuits beneath active bonding pads |
US6306749B1 (en) * | 1999-06-08 | 2001-10-23 | Winbond Electronics Corp | Bond pad with pad edge strengthening structure |
JP3387083B2 (ja) * | 1999-08-27 | 2003-03-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US20030127716A1 (en) * | 2002-01-09 | 2003-07-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Single layer wiring bond pad with optimum AL film thickness in Cu/FSG process for devices under pads |
CN1265452C (zh) * | 2002-04-02 | 2006-07-19 | 台湾积体电路制造股份有限公司 | 一种集成电路的金属焊垫及其制作方法 |
US6900541B1 (en) * | 2004-02-10 | 2005-05-31 | United Microelectronics Corp. | Semiconductor chip capable of implementing wire bonding over active circuits |
US7115985B2 (en) * | 2004-09-30 | 2006-10-03 | Agere Systems, Inc. | Reinforced bond pad for a semiconductor device |
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