CN110379720A - 一种dcb衬板的制作方法及igbt模块 - Google Patents

一种dcb衬板的制作方法及igbt模块 Download PDF

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CN110379720A
CN110379720A CN201910625696.XA CN201910625696A CN110379720A CN 110379720 A CN110379720 A CN 110379720A CN 201910625696 A CN201910625696 A CN 201910625696A CN 110379720 A CN110379720 A CN 110379720A
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metal
wiring layer
dcb
groove
igbt module
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CN110379720B (zh
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张宏强
史波
敖利波
曹俊
马浩华
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Gree Electric Appliances Inc of Zhuhai
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Abstract

本发明涉及一种DCB衬板的制作方法，包括以下步骤：S10：在DCB基底表面的第一金属布线层上开设凹槽；S20：将第二金属布置在所述凹槽内部；S30：将与所述第二金属相同材质的丝线与所述第二金属进行连接。通过该方法制作的IGBT模块，克服了不同材质之间键合所导致的CTE值不匹配等问题，不但使键合更加牢固，还减少了模块在工作过程中产生的微裂纹等问题。

Description

一种DCB衬板的制作方法及IGBT模块
技术领域
本发明涉及半导体技术领域，特别地涉及一种DCB衬板的制作方法及IGBT模块。
背景技术
IGBT模块是由绝缘栅双极型晶体管芯片(IGBT)和续流二极管芯片(FWD)通过特定的电路桥接封装而成的模块化半导体产品，主要由芯片、塑料框架、电极端子、DCB衬底、基板、金属底板、键合丝和焊料等材料构成。
IGBT模块的焊接方式一般是采用电极端子底部平面和DCB衬底表面金属作为键合区域，用铜丝、金丝或铝丝键合的工艺实现端子与模块内部的电气连接，由此可实现模块结构薄型化、部件轻量化、封装工艺和组装模具简易化，同时由于模块高度较低，缩短端子通流距离，使得封装电感减小。
在键合工艺中，所使用的金属丝一般为铝丝。因为与铜丝、金丝相比，铝丝具有较软，应力较小，成本低，导电性能良好等特点，因而在模块的键合工艺中得到广泛应用。而DCB衬底表面的金属布线层一般为铜布线层，所以DCB衬底表面的键合方式一般为铝-铜键合。但是，由于铜的CTE(热膨胀系数)值为17×10-6/℃,铝的CTE值为25×10-6/℃，两种金属的CTE值存在差异，所以铝-铜键合方式将会由于CTE值的不匹配性在热疲劳实验中显示出来，并导致模块在工作过程中应力增加并最终出现微裂纹。
发明内容
为了解决上述问题，本发明提供了一种DCB衬板的制作方法及IGBT模块，用于解决上述问题。
第一方面，本申请提供了一种DCB衬板的制作方法，包括以下步骤：
S10：在DCB基底表面的第一金属布线层上开设凹槽；
S20：将第二金属布置在所述凹槽内部；
S30：将与所述第二金属相同材质的丝线与所述第二金属进行连接。
在一种实施方式中，所述凹槽的纵截面构造成正立的锥形。
在一种实施方式中，所述凹槽设置在所述第一金属布线层的中间位置。
在一种实施方式中，所述锥形的高度小于等于第一金属布线层厚度的1/2。
在一种实施方式中，所述凹槽上表面的圆形的直径小于等于第一金属布线层宽度的1/4，所述凹槽下表面的圆形的直径小于等于第一金属布线层宽度的1/2。
在一种实施方式中，在步骤S20和步骤S30之间还包括：将第二金属的上表面进行抛光打磨处理。
在一种实施方式中，所述第一金属为铜，相应地，第一金属布线层为铜布线层，
所述第二金属为铝材，相应地，与第二金属相同材质的丝线为铝丝线。
在一种实施方式中，铜布线层与铝材之间采用挤压成型的方式结合在一起。
在一种实施方式中，在步骤S30之后还包括：将凹槽内的铝材上表面以及铝材与铝丝线连接处进行镀镍处理。
在一种实施方式中，镀镍层的厚度为3-10微米。
第二方面，本申请提供了一种IGBT模块，包括从下至上依次设置的基板、DCB衬板和芯片，
所述DCB衬板包括DCB基底和设置在所述DCB基底上方的第一金属布线层，所述第一金属布线层的中间位置设有凹槽，所述凹槽内压接第二金属，所述第二金属连接与所述第二金属相同材质的丝线。
在一种实施方式中，所述IGBT模块还包括设置在基板下方的散热组件，所述散热组件包括散热层和设置在所述散热层和所述基板之间的导热材料。
在一种实施方式中，所述基板和所述DCB衬板之间通过第一焊接层进行连接。
在一种实施方式中，所述芯片和所述DCB衬板的外围封装有绝缘材料，且所述芯片的表面设置有延伸至所述绝缘材料外部的引脚或者母线端子。
在一种实施方式中，所述第一金属布线层和所述芯片之间通过第二焊接层进行连接。
在一种实施方式中，所述第一焊接层和所述第二焊接层的材质为锡或者银。
与现有技术相比，本发明的优点在于：
本申请将DCB衬板基底表面的金属布线层开设凹槽，并在该凹槽内压接与金属连接丝相同材质的金属，其中，较常见的一般是在铜布线层上开设凹槽，并在凹槽内压接铝材，并采用铝丝与铝材进行键合连接。从而克服了因铝-铜键合方式所导致的CTE值不匹配等问题，该种同质材料间的键合不仅更加牢固，还减少了模块在工作过程中产生的微裂纹等问题。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。
图1是根据本发明的一种DCB衬板的制作方法的流程图。
图2是采用图1的方法所制作的包含DCB衬板的IGBT模块的结构示意图。
图3是图2中的凹槽部分的结构放大图。
图4是图3的俯视图。
图5是现有技术的一种IGBT模块的结构示意图。
具体实施方式
下面将结合附图对本发明作进一步说明。
如图1所示，显示了根据本申请的一种DCB衬板的制作方法，包括以下步骤：
第一步：在DCB基底表面的第一金属布线层上开设凹槽。
图2显示了根据图1的方法所制作的IGBT模块的结构示意图。图3是图2的凹槽13的放大图。图4是图3所示凹槽的俯视图。参考图2-图4可知，该凹槽13设置在第一金属布线层52的中间位置，优选地，该凹槽13从第一金属布线层的52中心位置向下延伸。该凹槽13的纵截面构造成正立的锥形，锥形的高度小于等于第一金属布线层厚度的1/2，凹槽上表面的圆形的直径小于等于第一金属布线层宽度的1/4，凹槽下表面的圆形的直径小于等于第一金属布线层宽度的1/2。
第二步：将第二金属布置在凹槽内部。
优选地，将第二金属的表面进行抛光打磨处理。
第三步：采用与第二金属相同材质的丝线与第二金属进行连接。
在一个具体的实施例中，第一金属为铜，相应地，第一金属布线层为铜布线层，第二金属为铝材，相应地，与第二金属相同材质的丝线为铝丝线。
在一个具体的实施例中，铜布线层与铝材之间采用挤压成型的方式结合在一起。
在该实施例中，将凹槽内的铝材上表面以及铝材与铝丝线连接处进行镀镍处理。优选地，镀镍层的厚度为3-10微米。
再次参考图2，该IGBT模块包括从下至上依次设置的基板3、DCB衬板5和芯片7。
DCB衬板5包括DCB基底51和设置在DCB基底51上方的第一金属布线层52，第一金属布线层52的中间位置设有凹槽13，凹槽13内布置有第二金属，第二金属与第一金属布线层之间通过挤压成型结合在一起。将与第二金属相同材质的丝线8与第二金属进行连接。
通过将DCB衬板基底表面的金属布线层开设凹槽，并在该凹槽内压接与金属连接丝相同材质的金属，其中，较常见的一般是在铜布线层上开设凹槽，并在凹槽内压接铝材，并采用铝丝与铝材进行键合连接。从而克服了因铝-铜键合方式所导致的CTE值不匹配等问题，该种同质材料间的键合不仅更加牢固，还减少了模块在工作过程中产生的微裂纹等问题。
为了进一步说明本申请的进一步，图5显示了现有技术的一种IGBT模块，该模块中，DCB衬底5表面的金属布线层为铜布线层，而丝线8为铝线，在铜布线层的表面铝线与铜进行键合连接，但是由于铝和铜之间的热膨胀系数之间的差异，该种键合方式因热膨胀系数的不匹配而导致微裂纹，从而影响键合的牢固性。
在图2所示的实施例中，IGBT模块还包括设置在基板3下方的散热组件，散热组件包括散热层1和设置在散热层1和基板3之间的导热材料2。优选地，该导热材料2为导热脂。
在一个具体的实施例中，基板3和DCB衬板5之间通过第一焊接层4进行连接。第一金属布线层52和芯片7之间通过第二焊接层6进行连接。第一焊接层和第二焊接层的材质通常为锡或者银。
在图2所示的实施例中，芯片7和DCB衬板5的外围封装有绝缘材料9，绝缘材料9优选为硅胶或塑封料等。
芯片7的表面设置有延伸至绝缘材料9外部的引脚10或者母线端子，使芯片电极与外部实现电性连接。
优选地，第一金属布线层52为铜布线层，第二金属为铝材，第二金属丝线为铝丝线。从而铝丝线实现了芯片与通布线层以及引脚之间的电性连接。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (16)

1.一种DCB衬板的制作方法，其特征在于，包括以下步骤：
S10：在DCB基底表面的第一金属布线层上开设凹槽；
S20：将第二金属布置在所述凹槽内部；
S30：将与所述第二金属相同材质的丝线与所述第二金属进行连接。
2.根据权利要求1所述的制作方法，其特征在于：所述凹槽的纵截面构造成正立的锥形。
3.根据权利要求1所述的制作方法，其特征在于：所述凹槽设置在所述第一金属布线层的中间位置。
4.根据权利要求2所述的制作方法，其特征在于：所述锥形的高度小于等于第一金属布线层厚度的1/2。
5.根据权利要求1-3任一项所述的制作方法，其特征在于：所述凹槽上表面的圆形的直径小于等于第一金属布线层宽度的1/4，所述凹槽下表面的圆形的直径小于等于第一金属布线层宽度的1/2。
6.根据权利要求1所述的制作方法，其特征在于：在步骤S20和步骤S30之间还包括：将第二金属的上表面进行抛光打磨处理。
7.根据权利要求1所述的制作方法，其特征在于：所述第一金属为铜，相应地，第一金属布线层为铜布线层，
所述第二金属为铝材，相应地，与第二金属相同材质的丝线为铝丝线。
8.根据权利要求7所述的制作方法，其特征在于：铜布线层与铝之间采用挤压成型的方式结合在一起。
9.根据权利要求7所述的制作方法，其特征在于：在步骤S30之后还包括：将凹槽内的铝材上表面以及铝材与铝丝线连接处进行镀镍处理。
10.根据权利要求9所述的制作方法，其特征在于：镀镍层的厚度为3-10微米。
11.一种IGBT模块，其特征在于，包括从下至上依次设置的基板、DCB衬板和芯片，
所述DCB衬板包括DCB基底和设置在所述DCB基底上方的第一金属布线层，所述第一金属布线层的中间位置设有凹槽，所述凹槽内压接第二金属，所述第二金属连接与所述第二金属相同材质的丝线。
12.根据权利要求11所述的IGBT模块，其特征在于，所述IGBT模块还包括设置在基板下方的散热组件，所述散热组件包括散热层和设置在所述散热层和所述基板之间的导热材料。
13.根据权利要求11所述的IGBT模块，其特征在于，所述基板和所述DCB衬板之间通过第一焊接层进行连接。
14.根据权利要求11所述的IGBT模块，其特征在于，所述芯片和所述DCB衬板的外围封装有绝缘材料，且所述芯片的表面设置有延伸至所述绝缘材料外部的引脚或者母线端子。
15.根据权利要求13所述的IGBT模块，其特征在于，所述第一金属布线层和所述芯片之间通过第二焊接层进行连接。
16.根据权利要求15所述的IGBT模块，其特征在于，所述第一焊接层和所述第二焊接层的材质为锡或者银。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117161323A (zh) * 2023-09-07 2023-12-05 江苏富乐华半导体科技股份有限公司 一种衬板生产用成型模具及其成型方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201821629U (zh) * 2010-10-21 2011-05-04 芯通科技（成都）有限公司 一种新型嵌铜铝基板
CN102254877A (zh) * 2011-07-08 2011-11-23 南京银茂微电子制造有限公司 无金属底板功率模块
CN103107107A (zh) * 2012-12-12 2013-05-15 贵州振华风光半导体有限公司 提高厚膜混合集成电路同质键合系统批量生产性的方法
CN106863925A (zh) * 2015-12-11 2017-06-20 林暄智 复合金属制作方法及复合金属结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201821629U (zh) * 2010-10-21 2011-05-04 芯通科技（成都）有限公司 一种新型嵌铜铝基板
CN102254877A (zh) * 2011-07-08 2011-11-23 南京银茂微电子制造有限公司 无金属底板功率模块
CN103107107A (zh) * 2012-12-12 2013-05-15 贵州振华风光半导体有限公司 提高厚膜混合集成电路同质键合系统批量生产性的方法
CN106863925A (zh) * 2015-12-11 2017-06-20 林暄智 复合金属制作方法及复合金属结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117161323A (zh) * 2023-09-07 2023-12-05 江苏富乐华半导体科技股份有限公司 一种衬板生产用成型模具及其成型方法
CN117161323B (zh) * 2023-09-07 2024-01-30 江苏富乐华半导体科技股份有限公司 一种衬板生产用成型模具及其成型方法

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