CN1758437A - 半导体集成电路及其制造方法 - Google Patents

半导体集成电路及其制造方法 Download PDF

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CN1758437A
CN1758437A CNA2005101096727A CN200510109672A CN1758437A CN 1758437 A CN1758437 A CN 1758437A CN A2005101096727 A CNA2005101096727 A CN A2005101096727A CN 200510109672 A CN200510109672 A CN 200510109672A CN 1758437 A CN1758437 A CN 1758437A
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布伦特·A·安德森
爱德华·J·诺瓦克
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GlobalFoundries Inc
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Abstract

本发明提供一种集成电路及其制造方法。该集成电路具有制作在SOI区和体区中的器件，其中区由填充有外延淀积材料的沟槽连接。填充沟槽提供连接SOI和体区的连续半导体表面。SOI和体区可以具有相同或不同的晶体取向。通过形成具有由嵌入式侧壁间隙壁(由电介质构成)分隔开的SOI和体区的衬底，来制作本集成电路。蚀刻侧壁间隙壁，形成随后用外延材料填充的沟槽。在平面化之后，衬底具有带连续半导体表面的SOI和体区。对接的P－N结和硅化物层可以提供SOI和体区之间的电连接。

Description

半导体集成电路及其制造方法
技术领域
本发明一般涉及集成电路以及CMOS或FET器件。更具体地，本发明涉及一种具有在体(bulk)材料中所制作的器件和在SOI材料中所制作的器件的CMOS芯片。这些器件连接对接的硅化物结。
背景技术
一般利用两种不同类型的半导体衬底之一来制造半导体器件：体衬底和绝缘体上硅或绝缘体上半导体(SOI)衬底。体区制作的器件利用没有掩埋层的一整体半导体衬底。SOI衬底具有在电子器件下面的绝缘材料、一般为二氧化硅(SiO2)的掩埋层。
本领域中众所周知，SOI和体制作的器件具有不同的优点和不同的应用。例如，与体制作的器件相比，SOI器件可以具有减少寄生电容和更低功耗的优点。比较起来，体制造的器件可以提供其它的优点，例如体电压的控制，其可用于调整FET器件的阈值电压。并且，体制造的器件一般可以具有更低的制造成本和更高的功率操作能力。因此，在SOI和体制造之间的选择一般取决于电路应用和性能需要。
在单个晶片上同时利用SOI和体器件的集成电路对于电路设计者将提供最有用的解决方案，这是因为可以开发两种类型器件的优势。然而常规晶片加工技术使得这种工作很难实现。在单个衬底上集成SOI和体器件的一个显著问题是使器件之间电连接。过去，SOI和体器件区之间的电连接制作在布线层上。令人遗憾的是，用于连接SOI和体器件的布线层增加了电路的尺寸。这对于高密度存储器电路和微处理器来说尤其是一个问题。
将发展现有技术，以提供一种简单、廉价的方法，用于在单个衬底上同时制造体和SOI器件。这将特别用于提供在单个衬底上的SOI和体器件之间的小尺寸电连接。
还众所周知，晶体取向可以非常大地影响场效应晶体管以及其它半导体器件的开关速度和载流能力。例如，与在{100}取向的硅中相比，P型互补金属氧化物半导体(CMOS)晶体管在{110}取向的硅中可以具有2-3倍高的电荷载流子迁移率。相似的，与在{110}取向的硅中相比，N型CMOS器件在{100}取向的硅中可以具有大约2倍高的电荷载流子迁移率。因此，仅具有{110}晶体取向或仅具有{100}晶体取向的晶片不能同时提供具有最大载流子迁移率的P型和N型器件。对于同时在P型和N型器件中的最大载流子迁移率来说，同时具有{110}和{100}区的晶片是必需的。
已知几种方法用于制作同时具有{110}和{100}区的混合衬底。然而，在现有的混合晶片制作技术中，其可能很难提供跨接{110}和{100}区的电连接。过去，利用布线层来制作电连接，这是不理想的。
因此，将发展现有技术，以提供一种简单并廉价的方法，用于在单个混合衬底上制作具有不同晶体取向的器件。特别用于提供在不同晶体取向的区之间的小尺寸连接。
发明内容
本发明提供一种半导体集成电路，具有带掩埋电介质层的绝缘体上半导体(SOI)区和邻近SOI区的体半导体区。填充有外延半导体材料的沟槽设置在SOI区和体区之间的边界处。SOI区和体区可以具有相同或不同的晶体取向。
掩埋侧壁间隙壁可以设置在填充沟槽下面。
SOI区和体区可以具有不同的掺杂类型。在这种情况下，对接的P-N结可以设置在SOI区中或在填充沟槽中。金属硅化物层可以设置在对接的P-N结上。金属硅化物层可以延伸在SOI区和体区上方并提供区之间的电连接。
本发明还包括一种用于形成具有SOI区和体区的半导体集成电路的方法。在本方法中，形成了分离的SOI和体区。通过嵌入式侧壁间隙壁分隔开SOI和体区。蚀刻侧壁间隙壁以形成空的沟槽(可以完全去除或局部去除侧壁间隙壁)。然后，使半导体材料外延淀积在沟槽中。
在用外延淀积的材料填充沟槽之后，优选平面化晶片。SOI区和体区可以掺杂有不同的掺杂剂，使得P-N结形成在沟槽中或在SOI区中。可以在沟槽上方淀积金属硅化物层以形成桥接SOI区和体区的电接触。
附图说明
图1示出了根据本发明的混合SOI/体CMOS集成电路器件；
图2a示出了本发明的一个实施例，其中P-N对接结与SOI和体器件区之间的边界重叠；
图2b示出了本发明的一个实施例，其中外延填充沟槽向下延伸到SOI区的掩埋氧化物层；
图3a-3k示例了用于制作本发明的集成电路的一个优选方法；
图4示出了本发明的一个可替换实施例；
图5示出了本发明的一个可替换实施例，其中p+和n+掺杂区没有深深地延伸。
具体实施方式
本发明提供一种同时具有制作在SOI区和体区中的器件的集成电路。用填充有外延材料的沟槽来隔离SOI和体区。填充沟槽产生于本制作方法。填充沟槽提供了连接SOI和体区的连续半导体表面。SOI和体区可以具有相同或不同的晶体取向。通过首先形成具有由嵌入式侧壁间隙壁(例如，由SiO2构成)分隔开的SOI和体区的衬底，来制作本集成电路。蚀刻侧壁间隙壁，形成随后用外延材料填充的沟槽。在平面化之后，衬底具有带连续半导体表面的SOI和体区。可以在SOI和体区内同时制作FET和CMOS器件。通过掺杂的区和硅化物层，可以设置电连接跨接SOI和体区。不需要布线层来提供SOI和体区之间的电连接。
图1示出了根据本发明的CMOS集成电路。电路具有带SOI区22和体区24的衬底20。SOI区设置在掩埋氧化物层25(例如，由SiO2构成)上。SOI区具有可以具有{110}晶体取向的器件层26。体区24具有可以具有{100}晶体取向的器件层28。体器件层28优选外延生长在衬底20上。SOI和体区具有带栅电极30和32的场效应晶体管。如本领域所公知的，栅电极30和32具有间隙壁和栅极电介质层。浅沟槽隔离结构STI优选形成在一部分SOI区22周围。
外延填充沟槽34设置在SOI区22和体区24之间。外延填充沟槽34包括外延生长的半导体材料(例如，外延淀积的硅)。在此处所介绍的实施例中，大约在外延填充沟槽34的中心处，晶体取向经历SOI区的{110}取向和体区的{100}取向之间的过渡。然而，应明白，SOI区22可以具有{100}或{111}晶体取向，而体区24可以具有{110}或{111}晶体取向。还可以利用其它的晶体取向。SOI区22和体区24的晶体取向可以相同或不同。
掩埋侧壁间隙壁38位于外延填充沟槽下面。掩埋侧壁间隙壁38可以包括SiO2、氮化硅、氮氧化硅或本领域所公知的其它电介质材料。掩埋侧壁间隙壁38连接掩埋氧化物层25，但可以不与掩埋氧化物层25成为一整体(即，掩埋侧壁间隙壁可以按与掩埋氧化物层25分开的工艺来形成)。掩埋侧壁间隙壁直接位于外延填充沟槽34下面。掩埋侧壁间隙壁38将典型地具有与外延填充沟槽34相同的宽度。
众所周知，SOI区22优选具有邻近栅电极30的p+掺杂区和在电极下面的n-掺杂区。器件层26包括p+和n-掺杂区。众所周知，体区24优选具有邻近栅电极32的n+掺杂区和在电极下面的p-掺杂区。器件层28包括n+和p-掺杂区。值得注意的是，如本领域所公知的，p+和p-区不应该接触，以及n+和n-区不应该接触。通过使n+和p+掺杂区足够深来提供这种隔离。典型地，p+区应向下延伸到掩埋氧化物层25。n+区应向下至少延伸到掩埋侧壁间隙壁38的顶部。
P-N对接结36形成在p+和n+掺杂区的边界处。P-N对接结设置在图1中的SOI区22内。
金属硅化物层40形成在p+和n+掺杂区上。硅化物层40桥接P-N结并提供p+和n+掺杂区之间的欧姆接触。
本电路可以由硅或其它半导体材料、例如砷化镓、碳化硅来构成。STI结构、掩埋氧化物层25、栅极电介质和其它电介质结构可以由SiO2、氮化硅或本领域所公知的其它电介质材料构成。
在操作中，图1的电路提供SOI器件和体器件两者的优点。SOI器件和体器件都集成在单个衬底上。
并且，金属硅化物层40提供SOI区22和体区24之间的电连接。因此，不需要布线层来电连接SOI区22和体区24，如在现有技术中。
并且，由于SOI区和体区可以具有不同的晶体取向，所以可以针对具体的晶体取向使每个区中的器件最佳化。例如，SOI区中的CMOS器件(即，具有栅极30)可以是趋向于在{110}取向的晶体中具有较高的迁移率的p型FET。体区中的CMOS器件(即，具有栅极32)可以是趋向于在{100}取向的晶体中具有较高的迁移率的n型FET。
通过外延填充沟槽34使本发明的优势成为可能。外延填充沟槽34提供SOI区22和体区24之间的光滑半导体表面。由于SOI区22和体区24之间的边界不具有电介质填充沟槽，所以不需要金属布线层来用于两个区22和24之间的电连接。换句话说，外延填充沟槽使金属硅化物层40能够提供两个区22和24之间的电连接。
图2a示出了发明的一个可替换实施例，其中P-N对接结设置在外延填充沟槽34内。在本发明中，P-N对接结可以位于SOI区22中或在外延填充沟槽34内。由于P-N对接结36设置在SOI区22中，所以其在不对衬底20短路的情况下提供用于p+掺杂区对n+掺杂区的电连接。如果P-N对接结位于体区中，那么将产生对衬底的短路，并且器件将不会工作。因此，P-N对接结不能设置在体区24内。并且，在图2a的器件中，n+掺杂区必须向下延伸到掩埋侧壁间隙壁38。
图2b示出了本发明的一个可替换实施例，其中不具有掩埋侧壁间隙壁。图2b的器件将基本上按与图1的器件相同的方式来工作。在本实施例中，需要使n+掺杂区一直向下延伸到掩埋氧化物层25，使得p+和p-区隔离，并使得n+和n-区隔离。
图3a-3k示例了用于制作本发明的集成电路的一个优选方法。下面介绍这些附图。
图3a：本方法开始于具有掩埋氧化物层的SOI晶片。如果希望不同的晶体取向用于SOI和体区，那么器件层50必须由具有与操作衬底(handlesubstrate)不同的晶体取向的接合晶片制成。在本发明中，SOI区22的晶体取向与器件层的晶体取向相同。如果SOI和体区必须具有相同的晶体取向，那么可以通过氧注入来制得掩埋氧化物层。在器件层50上设置衬垫膜(例如具有40nm的Si3N4的10nm的SiO2)。器件层50可以具有大约15nm至100nm的厚度。
图3b：蚀刻晶片以露出操作衬底。侧壁间隙壁52形成在器件层和掩埋氧化物层的剩余部分的侧壁上。侧壁间隙壁可以包括SiO2或其它电介质材料。侧壁间隙壁52可以具有大约5nm至30nm的宽度53。
图3c：外延硅55选择性地生长在操作衬底上。生长外延硅直到其与器件层50齐平或者高于器件层50。
图3d：剥离衬垫膜并平面化衬底。衬底表面具有由侧壁间隙壁52分离的SOI和体区。
图3e：通过选择性蚀刻使侧壁间隙壁52凹进。例如，选择性蚀刻可以是湿法化学蚀刻或等离子体蚀刻。蚀刻侧壁间隙壁形成了沟槽57。可以局部去除(如所示例的)或完全去除侧壁间隙壁。通过蚀刻可以约50％除去侧壁间隙壁。侧壁间隙壁的完全去除将最终产生图2b中所示例的实施例。
图3f：进行外延生长。沟槽57外延填充半导体材料。在所示例的实施例中，SOI区具有生长的{110}外延层，而体区具有生长的{100}层。{110}和{100}区之间的边界近似位于沟槽57的中心处。优选地，无空隙填充沟槽。外延淀积掩埋侧壁间隙壁的未蚀刻的部分，由此形成掩埋侧壁间隙壁38。
图3g：平面化衬底。优选地，(但任选地)从SOI和体区中除去所有的外延淀积材料。现在衬底具有带不同晶体取向的区的连续硅表面。
图3h：在外延填充沟槽的一些区域内形成浅沟槽隔离(STI)。根据现有技术中所公知的许多技术，可以产生浅沟槽隔离STI。例如，参考美国专利5,804,490和6,479,368(此处引入供参考)来得到关于如何产生浅沟槽隔离的更多的信息。并且，可轻注入SOI和体区以形成p-和n-区(未示例的)。
图3i：如现有技术所公知的，形成栅电极30和32以及间隙壁。
图3j：进行注入以产生p+和n+掺杂区以及P-N对接结36。优选地，设置注入掩模，使得对接结36位于SOI区22内。对接结36或者可位于掩埋侧壁间隙壁38上方(并与外延填充沟槽重叠)。然而，因为掩模对准中的错误可能使对接结位于体区中，并且这将引起电路故障(由于p+掺杂区和衬底20之间的接触)，所以更难涉及这种结布置。
图3k：形成桥接对接结36的金属硅化物层40。金属硅化物可以是任一的钴、钛、钨、镍、铂或类似的硅化物。硅化物层40提供跨过对接结的欧姆连接。
当然，可以使掺杂极性与图1和图2a-2c中所示的极性相反。例如，图4示出了具有在SOI区22中的N型器件和在体区中的P型器件的本发明的一个实施例。
图5示出了本发明的可替换实施例，其中p+和n+掺杂区没有向下延伸到掩埋氧化物层25的水平面。因为p+和n+区延伸到掩埋侧壁间隙壁38下面的水平面，所以提供了隔离(例如，p+和p-区之间的隔离)。
本领域技术人员应清楚，在不脱离本发明范围的情况下，可以多种方式改变上述实施例。因此，将由所附权利要求及其合法的等效物来确定本
发明的范围。

Claims (18)

1、一种半导体集成电路，包括：
a)具有掩埋电介质层的绝缘体上半导体(SOI)区；
b)邻近所述SOI区的体半导体区；
c)设置在所述SOI区和所述体区之间填充有外延半导体材料的沟槽。
2、如权利要求1的半导体集成电路，进一步包括：在所述SOI区和所述体区之间、并设置在填充有外延半导体材料的所述沟槽下面的掩埋侧壁间隙壁。
3、如权利要求1的半导体集成电路，进一步包括：
a)在所述体区中的一第一类型掺杂；
b)在所述SOI区中的一第二类型掺杂；
c)在所述第一类型掺杂和所述第二类型掺杂之间的对接的P-N结，其中该对接的结设置在所述SOI区中或在所述填充的沟槽中。
4、如权利要求3的半导体集成电路，其中所述第一类型掺杂延伸进所述SOI区中。
5、如权利要求3的半导体集成电路，其中填充有外延半导体材料的所述沟槽具有所述第一类型掺杂。
6、如权利要求3的半导体集成电路，进一步包括设置在所述对接的P-N结上的金属硅化物层。
7、如权利要求6的半导体集成电路，其中所述金属硅化物层设置在具有所述第一类型掺杂的一部分体区上以及具有所述第二类型掺杂的一部分SOI区上。
8、如权利要求1的半导体集成电路，其中所述SOI区和所述体区具有不同的晶体取向。
9、如权利要求8的半导体集成电路，其中所述SOI区和所述体区由硅构成，以及其中所述SOI区具有{110}晶体取向，而所述体区具有{100}晶体取向。
10、一种半导体集成电路，包括：
a)具有掩埋电介质层的绝缘体上半导体(SOI)区；
b)邻近所述SOI区的体半导体区；
c)由所述体区中的一第一类型掺杂和所述SOI区中的一第二类型掺杂所形成的P-N结。
d)设置在所述P-N结上并电桥接所述P-N结的金属硅化物层。
11、如权利要求10的半导体集成电路，其中所述P-N结设置在所述SOI区中。
12、如权利要求10的半导体集成电路，其中所述P-N结设置在填充有外延半导体材料的沟槽处。
13、如权利要求10的半导体集成电路，进一步包括：
设置在所述SOI区和所述体区之间、填充有外延半导体材料的沟槽。
14、一种用于形成具有SOI区和体区的半导体集成电路的方法，包括如下步骤：
a)形成具有由嵌入式侧壁间隙壁分隔开的SOI区和体区的衬底；
b)蚀刻所述侧壁间隙壁以形成空的沟槽；以及
c)在所述沟槽中外延淀积半导体材料。
15、如权利要求14的方法，进一步包括如下步骤：
d)在步骤(c)之后平面化所述晶片；以及
e)在所述体区中形成一第一类型掺杂，以及在所述SOI区中形成一第二类型掺杂，其中在所述第一类型掺杂和所述第二类型掺杂之间的一P-N结设置在所述SOI区中或在所述沟槽中。
16、如权利要求15的方法，进一步包括如下步骤：
f)在步骤(e)之后形成跨接所述P-N结的金属硅化物层。
17、如权利要求13的方法，其中在步骤(b)中完全除去所述侧壁间隙壁。
18、如权利要求13的方法，其中在步骤(b)中局部除去所述侧壁间隙壁。
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