CN1755950A - 发光二极管的封装基板的形成方法 - Google Patents

发光二极管的封装基板的形成方法 Download PDF

Info

Publication number
CN1755950A
CN1755950A CNA2004100117986A CN200410011798A CN1755950A CN 1755950 A CN1755950 A CN 1755950A CN A2004100117986 A CNA2004100117986 A CN A2004100117986A CN 200410011798 A CN200410011798 A CN 200410011798A CN 1755950 A CN1755950 A CN 1755950A
Authority
CN
China
Prior art keywords
silicon substrate
neck ring
holes
insulation
insulation neck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100117986A
Other languages
English (en)
Other versions
CN100449799C (zh
Inventor
陈泽澎
邓绍猷
谢政璋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Epistar Corp
Original Assignee
GUOLIAN PHOTOELECTRIC SCIENCE AND TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GUOLIAN PHOTOELECTRIC SCIENCE AND TECHNOLOGY Co Ltd filed Critical GUOLIAN PHOTOELECTRIC SCIENCE AND TECHNOLOGY Co Ltd
Priority to CNB2004100117986A priority Critical patent/CN100449799C/zh
Publication of CN1755950A publication Critical patent/CN1755950A/zh
Application granted granted Critical
Publication of CN100449799C publication Critical patent/CN100449799C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Led Device Packages (AREA)

Abstract

一种发光二极管的封装基板的形成方法，包括提供一硅基板，该硅基板具有一第一面、一第二面及多个贯穿孔；藉由等离子体加强式化学气相沉积(PECVD)技术形成一绝缘层覆盖该第一面及该第二面，并同时形成一绝缘颈环(insulating collar)覆盖该多个贯穿孔的内壁；然后形成一导电层覆盖该绝缘层及该绝缘颈环。

Description

发光二极管的封装基板的形成方法
技术领域
本发明涉及发光二极管的封装，特别是涉及以硅芯片作为封装基板的工艺技术。
背景技术
目前以电路板材如FR4，或是陶瓷板材如Al2O3等来作封装基板已逐渐无法满足一些会产生高热的发光二极管元件的要求。所以，在高耐热性及高导热性的考虑下，改用硅芯片作为封装基板已成为发光二极管表面安装封装技术的最新发展趋势。
以硅芯片作为封装基板有一缺点，就是硅本身为一半导体，因此必须先在硅基板表面包覆一层绝缘层，使得在之后电极制作的阶段，电极与电极之间不会产生漏电的现象。硅基板上绝缘层的形成在现有技术(如台湾专利公告号495936)中已有叙述，乃将硅基板送入一含有氧气或氮气高温炉中使其表面形成一氧化层或氮化层即可。然而，此技术虽可在平坦的硅基板表面形成良好的绝缘，但是对于形成在硅基板贯穿孔内壁表面的绝缘，却往往会有包覆不完全或结构薄弱的缺陷。这是因为贯穿孔的孔径小深度大所产生的阶梯覆盖(Step Coverage)不良现象。此将导致贯穿孔内壁的半导体硅裸露出来，而与之后要形成的导电层接触，产生短路与漏电的现象。所以，要利用硅基板作发光二极管封装，必须先改善硅基板贯穿孔内壁的绝缘问题。
发明内容
本发明针对上述问题提出一种发光二极管的封装基板的形成方法，包括提供一硅基板，该硅基板具有一第一面、一第二面及多个贯穿孔；藉由等离子体加强式化学气相沉积(PECVD)技术形成一绝缘层覆盖该第一面及该第二面，并同时形成一绝缘颈环(insulating collar)覆盖该多个贯穿孔的内壁；然后形成一导电层覆盖该绝缘层及该绝缘颈环。
附图说明
图1：本发明的第一与第二实施例的制造流程图。
图2(a)到图2(e)：分别显示图1的制造流程图中每一步骤的硅基板的剖面图。
图2(F)：以本发明所制作的基板来封装发光二极管晶粒的一实例(传统引线焊接法)。
图2(g)：以本发明所制作的基板来封装发光二极管晶粒的另一实例(倒装芯片法)。
简单符号说明
11  提供一硅基板
13  于硅基板上形成多个贯穿孔
15  以PECVD技术形成一绝缘层及一绝缘颈环
17  将硅基板送入高温炉以形成一绝缘层及一绝缘颈环
19  以PECVD技术处理该绝缘颈环，使该绝缘颈环均匀分布在该多个贯穿孔的内壁上
12  形成一导电层覆盖绝缘层及绝缘颈环或进一步填满该多个贯穿孔
14  图案化导电层以形成符合需求的电极
210  硅基板  212  第一面  214  第二面
220  贯穿孔
230  绝缘层
240  绝缘颈环
250  导电层  252  电极  254  电极
260  发光二极管晶粒
270  金属线
280  封胶
具体实施方式
图1为本发明的第一及第二实施例的制造流程图。图2(a)到图2(e)则分别显示图1中每一步骤的硅基板的剖面图。
本发明的第一实施例，如图2(a)所示，提供一厚度约为100μm～500μm的硅基板210(如步骤11)。硅基板210具有一第一面212及一第二面214。接着，如图2(b)所示，以干式蚀刻(RIE)、湿式化学蚀刻或是激光贯孔的方式在硅基板210表面上形成多个贯穿孔220，其孔径大小约在20μm～80μm之间(如步骤13)。
然后参考图2(c)，利用等离子体加强式化学气相沉积(PECVD)技术，使硅基板210的第一面212及第二面214包覆一绝缘层230，并同时在贯穿孔220的内壁形成一绝缘颈环240(如步骤15)。必须注意的是此步骤中使用PECVD技术有别于现有技术，其主要的优点在于沉积绝缘层230及绝缘颈环240的同时，也利用等离子体来溅击绝缘层230及绝缘颈环240上的表面分子，使他们的分布更均匀、结构更加密实，因此得以完全覆盖在贯穿孔220的内壁以形成良好的绝缘。等离子体溅击的效果与贯穿孔220的外观比值(aspect Ration)有关。在此实施例中，绝缘颈环240的优选厚度约是在2000到5000之间，硅基板210的厚度在约100μm到500μm之间，及贯穿孔220的孔径大小在20μm到80μm之间时，可有优选效果。
现在说明本发明的第二实施例，其中前两个步骤(即步骤11及步骤13)与第一实施例相同。在多个贯穿孔220形成之后(即步骤13之后)，将硅基板210送入含有一反应气体的高温炉中，此反应气体可为氧气、氮气、氨气、水气或一定比例的上述气体的混合气体，使硅基板210的第一面212及第二面214包覆一含氧化物或氮化物的绝缘层230(如步骤17)。必须注意到的是，步骤17执行时也会同时在贯穿孔220的内壁形成一绝缘颈环240，但是，此绝缘颈环240并不能完全包覆贯穿孔220的内壁故将导致之后漏电的产生。所以，在硅基板210送入高温炉反应之后，必需以等离子体加强式化学气相沉积(PECVD)技术处理该绝缘颈环240，使该绝缘颈环240均匀分布在该多个贯穿孔220的内壁上，以避免该内壁露出(如步骤19)。第二实施例中，PECVD处理步骤可仅针对容易产生漏电缺陷的绝缘颈环240实施，与第一实施例比较能节省PECVD的操作时间，除此以外，所采用硅基板210的厚度、贯穿孔220的孔径大小、及绝缘颈环240的厚度等优选条件均与第一实施例相似。
接下来的步骤，第一实施例与第二实施例皆同。参考图2(d)及步骤12，形成一导电层250覆盖绝缘层230及绝缘颈环240，此导电层250可为任何金属材料，而且除了覆盖绝缘层230及绝缘颈环240外，也可进一步地将多个贯穿孔220填满。步骤12可藉蒸镀、溅射或电镀的方式来进行。接着，如图2(e)所示，利用一般光刻工艺或利用激光(Nd-YAG)切割来图案化导电层250以形成符合需要的电极252及254(如步骤14)，如此即完成一发光二极管封装用的基板。
图2(f)及图2(g)说明以本发明所制作的基板来封装发光二极管晶粒的实例。图2(f)显示传统引线焊接方式的封装，其中260代表发光二极管晶粒，270代表金属线，280代表封胶；图2(g)则显示另一种倒装芯片法的封装。
以上实施例的详述，希望能更加清楚描述本发明的特征与精神，而上述所揭露的实施例并非对本发明的范畴的限制。相反地，上述的说明以及各种改变及均等性的安排皆为本发明所欲受到保护的范畴。因此，本发明权利要求的范畴应此根据上述的说明作最宽广的解释，并涵盖所有可能均等的改变以及具均等性的安排。

Claims (11)

1.一种发光二极管的封装基板的形成方法，包括：
提供一硅基板，该硅基板具有一第一面、一第二面及多个贯穿孔，该多个贯穿孔贯穿该硅基板；
藉由等离子体加强式化学气相沉积技术形成一绝缘层覆盖该第一面及该第二面，及形成一绝缘颈环覆盖该多个贯穿孔的内壁；以及
形成一导电层覆盖该绝缘层及该绝缘颈环。
2.如权利要求1所述的方法，该硅基板的厚度约在100μm到500μm之间。
3.如权利要求1所述的方法，该贯穿孔的孔径大小约在20μm到80μm之间。
4.如权利要求1所述的方法，该绝缘颈环的厚度约在2000到5000之间。
5.如权利要求1所述的方法，其中该导电层还包括填满该多个贯穿孔。
6.一种发光二极管的封装基板的形成方法，包括：
提供一硅基板，该硅基板具有一第一面、一第二面及多个贯穿孔；
将该硅基板经过含有一反应气体的一高温炉，以形成一绝缘层覆盖该第一面及该第二面，及形成一绝缘颈环覆盖该多个贯穿孔的内壁；
以等离子体加强式化学气相沉积技术处理该绝缘颈环，使该绝缘颈环均匀分布在该多个贯穿孔的内壁上，以避免该内壁露出；以及
形成一导电层覆盖该绝缘层及该绝缘颈环。
7.如权利要求6所述的方法，该硅基板的厚度约在100μm到500μm之间。
8.如权利要求6所述的方法，该贯穿孔的孔径大小约在20μm到80μm之间。
9.如权利要求6所述的方法，该绝缘颈环的厚度约在2000到5000之间。
10.如权利要求6所述的方法，其中该反应气体选自含有氧气、氮气、氨气、水气、及上述的任何组合的群组。
11.如权利要求6所述的方法，其中该导电层还包括填满该多个贯穿孔。
CNB2004100117986A 2004-09-29 2004-09-29 发光二极管的封装基板的形成方法 Expired - Lifetime CN100449799C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100117986A CN100449799C (zh) 2004-09-29 2004-09-29 发光二极管的封装基板的形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100117986A CN100449799C (zh) 2004-09-29 2004-09-29 发光二极管的封装基板的形成方法

Publications (2)

Publication Number Publication Date
CN1755950A true CN1755950A (zh) 2006-04-05
CN100449799C CN100449799C (zh) 2009-01-07

Family

ID=36689027

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100117986A Expired - Lifetime CN100449799C (zh) 2004-09-29 2004-09-29 发光二极管的封装基板的形成方法

Country Status (1)

Country Link
CN (1) CN100449799C (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074639B (zh) * 2009-11-24 2013-06-05 展晶科技(深圳)有限公司 发光二极管及其制程
EP2387082A3 (en) * 2006-04-21 2014-08-06 Tridonic Jennersdorf GmbH LED platform having a LED chip on a membrane
CN113991004A (zh) * 2021-10-26 2022-01-28 东莞市中麒光电技术有限公司 Led基板制作方法、led基板、led器件制作方法及led器件

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5024966A (en) * 1988-12-21 1991-06-18 At&T Bell Laboratories Method of forming a silicon-based semiconductor optical device mount
US5098865A (en) * 1989-11-02 1992-03-24 Machado Jose R High step coverage silicon oxide thin films
US20010028922A1 (en) * 1995-06-07 2001-10-11 Sandhu Gurtej S. High throughput ILD fill process for high aspect ratio gap fill
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
EP0926723B1 (en) * 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
JP3262059B2 (ja) * 1998-02-12 2002-03-04 日本電気株式会社 半導体装置の製造方法
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US6531328B1 (en) * 2001-10-11 2003-03-11 Solidlite Corporation Packaging of light-emitting diode
JP3904484B2 (ja) * 2002-06-19 2007-04-11 新光電気工業株式会社 シリコン基板のスルーホールプラギング方法
US6936536B2 (en) * 2002-10-09 2005-08-30 Micron Technology, Inc. Methods of forming conductive through-wafer vias
TW580751B (en) * 2003-01-30 2004-03-21 Mosel Vitelic Inc Method of forming bottom oxide in the trench

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2387082A3 (en) * 2006-04-21 2014-08-06 Tridonic Jennersdorf GmbH LED platform having a LED chip on a membrane
CN102074639B (zh) * 2009-11-24 2013-06-05 展晶科技(深圳)有限公司 发光二极管及其制程
CN113991004A (zh) * 2021-10-26 2022-01-28 东莞市中麒光电技术有限公司 Led基板制作方法、led基板、led器件制作方法及led器件

Also Published As

Publication number Publication date
CN100449799C (zh) 2009-01-07

Similar Documents

Publication Publication Date Title
KR940010277A (ko) 다층배선구조의 반도체장치 및 그의 제조방법
US7749906B2 (en) Using unstable nitrides to form semiconductor structures
CN1115723C (zh) 氮化钨层制造方法及使用同样原理的金属连线制造方法
CN1755950A (zh) 发光二极管的封装基板的形成方法
CN101211892B (zh) 半导体器件的多层金属布线及其形成方法
CN106654052B (zh) 有机发光二极管器件及其封装方法
KR20010030091A (ko) 반도체 장치의 제조방법
US6596629B2 (en) Method for forming wire in semiconductor device
CN113964167A (zh) 显示面板制备方法、显示面板和显示装置
KR100445409B1 (ko) 반도체소자의금속배선형성방법
EP1247876A3 (en) Method for manufacturing a semiconductor device
KR100503965B1 (ko) 반도체 소자의 확산 방지막 형성 방법
KR100414745B1 (ko) 반도체소자의금속배선형성방법
US6309963B1 (en) Method for manufacturing semiconductor device
KR100439050B1 (ko) 티타늄나이트라이드막제조방법
KR100781456B1 (ko) 반도체 소자의 금속배선 제조 시 배리어막 형성방법
CN1405845A (zh) 氧化钛层的制造方法
JP2704120B2 (ja) 半導体装置の製造方法
CN117558679A (zh) 一种半导体结构的制作方法及半导体结构
KR20020011478A (ko) 반도체소자의 금속배선방법
KR100363976B1 (ko) 반도체장치의 제조방법
KR100447232B1 (ko) 듀얼 다머신 구조의 금속 배선 형성 방법
JPH05129446A (ja) 半導体装置およびその製造方法
JPH05206297A (ja) 半導体装置の製造方法
KR19990066631A (ko) 반도체소자의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20060310

Address after: Hsinchu city of Taiwan Province

Applicant after: EPISTAR Corp.

Address before: Hsinchu Science Industrial Park, Taiwan

Applicant before: UNITED EPITAXY CO.,LTD.

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20090107