CN101211892B - 半导体器件的多层金属布线及其形成方法 - Google Patents

半导体器件的多层金属布线及其形成方法 Download PDF

Info

Publication number
CN101211892B
CN101211892B CN2007101082704A CN200710108270A CN101211892B CN 101211892 B CN101211892 B CN 101211892B CN 2007101082704 A CN2007101082704 A CN 2007101082704A CN 200710108270 A CN200710108270 A CN 200710108270A CN 101211892 B CN101211892 B CN 101211892B
Authority
CN
China
Prior art keywords
layer
wiring
semiconductor device
metal wiring
wsix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101082704A
Other languages
English (en)
Other versions
CN101211892A (zh
Inventor
金秀贤
金栢满
李荣镇
郑东河
金鼎泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101211892A publication Critical patent/CN101211892A/zh
Application granted granted Critical
Publication of CN101211892B publication Critical patent/CN101211892B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种半导体器件的多层金属布线及其形成方法。该半导体器件的多层金属布线包括：下Cu布线；上Al布线，形成为与下Cu布线接触；和扩散阻挡层，夹置在下Cu布线和上Al布线之间。该扩散阻挡层由W基层形成。

Description

半导体器件的多层金属布线及其形成方法
技术领域
本发明涉及一种形成半导体器件的多层金属布线的方法，且更具体而言涉及一种半导体器件的多层金属布线及其形成方法，该半导体器件包括用于防止相互接触的上和下金属布线之间的相互金属扩散的扩散阻挡层。
背景技术
对于高度集成的半导体器件，要求高速器件元件，从而存储器单元形成为叠层结构。另外，将电信号运载到每个单元的金属布线也形成为多层结构。铺设在多层结构中的金属布线提供了有利的设计灵活性，且允许在设定金属布线电阻、电流容量等的余量上的更多的余地。
通常而言，铝(Al)由于其出色的导电性和易于用于制造工艺而成为金属布线的选择。然而，由于半导体器件的高度集成而在更快速工作和要求更低工作电压的产品中，铜(Cu)优于Al，因为Cu比Al具有相对低的电阻。
然而，由于增加的制造费用和在高度集成的器件元件中可能存在的特定不适当的特性，仅应用Cu作为形成为多层结构的所有金属布线的材料并不是优选的。按照上述，当高速是重要时，Cu被用作多层结构中的金属布线材料，而当速度相对不重要时则使用Al。
同时，当在多层金属布线结构中Cu被用作下金属布线且Al被用作上金属布线时，下和上金属布线之间的扩散阻挡层是需要的，从而防止金属布线之间的金属扩散。
通常而言，在具有Cu的下布线和Al的上布线的多层金属布线结构中，Ti层和/或TiN层(即或者单独或者作为叠层)被用作下和上金属布线之间的扩散阻挡层。然而，由堆叠的Ti和TiN层制成的扩散阻挡层不能保证充分抑制金属布线之间的金属扩散所需的厚度。
不是不可能增加Ti和/或TiN层的厚度来抑制下Cu布线和上Al布线之间的金属扩散；然而，这仅导致了形成为镶嵌图案的Al上布线的截面面积的减小，且由此导致了金属布线电阻的不期望的增加。
而且，当堆叠的Ti和TiN层的厚度增加时，在镶嵌图案中的通孔中填充Al来形成上金属布线将变得更加困难，从而在通孔中可能产生空腔，导致显著增加金属布线电阻。
因此，为了抑制下Cu布线和上Al布线之间的金属扩散的目的而增加堆叠的Ti和TiN层的厚度是不可行的。
发明内容
本发明的实施方式提供了一种防止相互接触的上和下金属布线之间的相互金属扩散的半导体器件的多层金属布线，及其形成方法。
在一个实施方式中，半导体器件的多层金属布线包括：下Cu布线；上Al布线，形成为与下Cu布线接触；和扩散阻挡层，夹置在下Cu布线和上Al布线之间且由W基(基于W的)层形成。
W基层由WN层形成。
WN层具有50到
Figure S071A8270420070622D000021
的厚度。
W基层由W层和WN层的叠层形成。
W层和WN层的叠层具有50到
Figure S071A8270420070622D000022
的厚度。
W基层由WSiNy层形成。
WSiNy层具有50到的厚度。
W基层由WSix层和WSixNy层的叠层形成。
WSix层和WSixNy层的叠层具有50到
Figure S071A8270420070622D000024
的厚度。
在半导体器件的多层金属布线中，上Al布线包括形成于扩散阻挡层上的Al成核生长层。
Al成核生长层具有50到
Figure S071A8270420070622D000025
的厚度。
在另一实施方式中，半导体器件的多层金属布线的形成方法包括：在其上形成有衬层(underlayer)的半导体基板的上部上方形成下Cu布线；和在下Cu金属布线上方通过夹置扩散阻挡层而形成上Al布线，其中扩散阻挡层由W基层形成。
W基层由WN层形成。
WN层具有50到
Figure S071A8270420070622D000026
的厚度。
WN层以ALD方法或CVD方法形成。
WN层在200到400℃的温度和1到40Torr的压力的条件下形成。
W基层由W层和WN层的叠层形成。
W层和WN层的叠层具有50到
Figure S071A8270420070622D000031
的厚度。
W层和WN层的叠层的形成包括沉积W层和氮化W层的表面的步骤。
W层基于ALD方法或CVD方法形成。
W层在200到400℃的温度和1到40Torr的压力的条件下沉积。
氮化W层的表面通过在NH3、N2H4、N2、和N2/H2的任一的气氛下的热处理或等离子体处理来进行。
W基层由WSiNy层形成。
WSiNy层具有50到
Figure S071A8270420070622D000032
的厚度。
WSiNy层基于ALD方法或CVD方法形成。
WSiNy层在300到500℃的温度和0.01到10Torr的压力的条件下形成。
W基层由WSix层和WSiNy层的叠层形成。
WSix层和WSiNy层的叠层具有50到
Figure S071A8270420070622D000033
的厚度。
WSix层和WSiNy的叠层的形成包括沉积WSix层和氮化WSix层的表面的步骤。
WSix层基于ALD方法或CVD方法形成。
WSix层在300到500℃的温度和0.01到10Torr的压力的条件下形成。
氮化WSix层的表面通过在NH3、N2H4、N2、和N2/H2的任一的气氛下的热处理或等离子体处理来进行。
半导体器件的多层金属布线的形成方法包括，在形成上Al布线之前在扩散阻挡层上形成Al成核生长层。
Al成核生长层基于CVD方法而具有50到
Figure S071A8270420070622D000034
的厚度。
形成上Al布线的方法包括基于PVD方法在200到400℃的温度在扩散阻挡层上方沉积Al层，且在400到500℃的温度对Al层进行热处理的步骤。
形成上Al布线的方法包括基于PVD方法在150到200℃的温度在扩散阻挡层上方沉积第一Al层，且在200到450℃的温度基于PVD方法在第一Al层上方沉积第二Al层的步骤。
附图说明
图1A到1E是用于解释根据本发明的实施方式的半导体器件的多层金属布线的形成方法的剖面图；
图2是用于解释根据本发明的第一实施方式的形成WN层作为扩散阻挡层的方法的剖面图；
图3是用于解释根据本发明的第二实施方式的形成W层和WN层的叠层作为扩散阻挡层的方法的剖面图；
图4是用于解释根据本发明的第三实施方式的形成WSixNy层作为扩散阻挡层的方法的剖面图；以及
图5是用于解释根据本发明的第四实施方式的形成WSix层和WSixNy层的叠层作为扩散阻挡层的方法的剖面图。
具体实施方式
本发明形成了W基层的扩散阻挡层。W基的扩散阻挡层插入下Cu布线和上Al布线之间的接触界面中。优选地，W基层由WN层、W层和WN层的叠层、WSiNy层、或WSix层和WSiNy层的叠层形成。
与常规的扩散阻挡层的Ti层和TiN层相比，W基层具有非常出色的扩散阻挡特性。W基扩散阻挡层具有出色能力以抑制下Cu布线和上Al布线之间的金属扩散。因此，当对于在超高集成器件中形成下Cu布线和上Al布线而形成多层金属布线时，本发明提供了能够抑制上和下金属布线之间的金属扩散以及抑制由于金属布线之间的金属相互扩散而产生具有高电阻的金属化合物的出色的扩散阻挡层。
因此，本发明可以抑制由于金属布线之间的金属扩散而产生具有高电阻的金属化合物，使得可以改善器件性能特性和可靠性。而且，本发明提供了比堆叠的Ti和TiN层的常规阻挡层更薄厚度的扩散阻挡层，由此减小接触电阻。
其后，将参考图1A到1E详细描述根据本发明实施方式的半导体器件的多层金属布线的形成方法。
参考图1A，第一层间绝缘层110形成于半导体基板100上方，在半导体基板100上形成了衬层(未显示)，且第一层间绝缘层被蚀刻以形成界定用于形成下金属布线140的区域的沟槽120。第一扩散阻挡层130形成在包括沟槽120的第一层间绝缘层110上方。第一扩散阻挡层130由Ta层130a和TaN层130b的叠层形成。
Cu籽晶层沉积在第一扩散阻挡层130上方。Cu层采用电镀方法沉积在Cu籽晶层上方，从而填充沟槽120。通过蚀刻Cu层和第一扩散阻挡层130使得沟槽120之外的第一层间绝缘层110露出，下Cu布线140形成于沟槽120中。
参考图1B，第二层间绝缘层150形成于包括下Cu布线140的第一层间绝缘层110上方，且然后蚀刻第二层间绝缘层150以形成暴露下Cu布线140的接触孔160。
参考图1C，用于防止下Cu布线140和上金属布线(将形成于接触孔160中)之间的相互金属扩散的第二扩散阻挡层170形成于包括接触孔160的第二层间绝缘层150上方。第二扩散阻挡层170由钨基(或W基)层形成。例如，W基层可以包括WN层或W和WN层的叠层或WSiNy层或WSix和WSiNy层的叠层，等等。
参考图1D，Al成核生长层181通过比如化学气相沉积(CVD)的沉积方法而形成于W基第二扩散阻挡层170上方。Al成核生长层181形成以具有50到的厚度。
Al层的布线182形成于Al成核生长层181上，从而填充了接触孔160。例如，通过在200到400℃的范围的温度通过比如物理气相沉积(PVD)的沉积方法来沉积Al并通过在400到500℃的范围的温度对Al层进行热处理，从而形成布线182的Al层。相似地，例如，通过在150到200℃的范围的温度通过PVD方法沉积第一Al层且在第一Al层上方在200到450℃的范围的温度也通过PVD方法沉积第二Al层，从而可以形成布线182的Al层为第一Al层和第二Al层的叠层。
参考图1E，蚀刻上布线182的Al层和W基第二扩散阻挡层170来形成接触下Cu布线140的上Al布线180，由此形成根据本发明实施方式的半导体器件的多层金属布线。
图2是用于解释根据本发明的第一实施方式的形成WN层作为第二扩散阻挡层的方法的剖面图。如所示，WN层270在具有接触孔260的第二层间绝缘层250上方通过原子层沉积(ALD)或CVD方法形成为50到200的厚度。
例如，通过在200到400℃的范围的温度和1到40Torr的范围的压力下提供B2H6、WF6和NH3的组合的一种或更多的气体，形成了WN层270。当形成WN层270时，除了B2H6以外，还可以使用在B10H14、SiH4和Si2H6的组合中的一种或更多的气体。
另外，还可以通过提供B2H6和WF6的气体而将W层沉积到10到
Figure S071A8270420070622D000061
的厚度，然后通过提供B2H6和NH3的气体而将W层改变为WN层，由此沉积WN层，从而形成WN层270。除了B2H6气体以外，还可以使用在B10H14、SiH4和Si2H6的任一气体来形成W层。
在图2中，参考标记200代表半导体基板；210代表第一层间绝缘层；230a代表Ta层；230b代表TaN层；230代表第一扩散阻挡层；且240代表下Cu布线。
图3是用于解释根据本发明的第二实施方式的形成W层和WN层的叠层作为第二扩散阻挡层的方法的剖面图。如所示，在具有接触孔360的第二层间绝缘层350上方通过ALD或CVD方法首先沉积W层371且然后氮化W层371的表面，由此形成W层371和WN层372的叠层370为50到
Figure S071A8270420070622D000062
的厚度。
例如，通过首先在200到400℃的范围的温度和1到40Torr的范围的压力下提供WF6和B2H6的气体来沉积W层371，且然后在NH3的气氛下氮化W层371的表面，从而在W层371的表面上形成WN层372，由此形成了W层371和WN层372的叠层370。
除了B2H6气体以外，还可以使用在B10H14、SiH4和Si2H6的任一气体来沉积W层371。W层371表面的氮化可以通过使用除了NH3气体之外的N2H4的气体来进行，且氮化还可以通过由形成N2和N2/H2等离子体而提供包括N的自由基来进行。
同时，可以通过提高半导体基板的温度或可以通过热处理工艺来进行W层371表面的氮化，以利于有效的氮化处理。
在图3中，参考标记300代表半导体基板；310代表第一层间绝缘层；330a代表Ta层；330b代表TaN层；330代表第一扩散阻挡层；且340代表下Cu布线。
图4是用于解释根据本发明的第三实施方式的形成WSixNy层作为第二扩散阻挡层的方法的剖面图。如所示，WSixNy层470在具有接触孔460的第二层间绝缘层450上方通过ALD或CVD方法形成为50到300的厚度。
例如，通过在300到500℃的范围的温度和0.01到10Torr的范围的压力下提供WF6、B2H6、SiH4和NH3的组合的一种或更多的气体，形成了WSixNy层470。WSixNy层470可以以B2H6供给-B2H6排气-WF6供给-WF6排气-SiH4供给-SiH4排气-NH3供给-NH3排气的循环或以WF6供给-WF6排气-B2H6供给-B2H6排气-SiH4供给-SiH4排气-NH3供给-NH3排气的循环形成。
除了B2H6气体之外，还可以通过使用BH3和B10H14的一种或更多气体来形成WSixNy层470，且除了SiH4气体之外，还可以通过使用Si2H6和SiH2Cl2的一种或更多气体来形成WSixNy层470。
在图4中，参考标记400代表半导体基板；410代表第一层间绝缘层；430a代表Ta层；430b代表TaN层；430代表第一扩散阻挡层；且440代表下Cu布线。
图5是用于解释根据本发明的第四实施方式的形成WSix层和WSixNy层的叠层作为第二扩散阻挡层的方法的剖面图。如所示，WSix层571和WSixNy层572的叠层570在具有接触孔560的第二层间绝缘层550上方通过ALD或CVD方法沉积WSix层571且然后氮化WSix层571的表面而形成为50到300
Figure S071A8270420070622D00007142937QIETU
的厚度。
例如，通过首先在300到500℃的范围的温度和0.01到10Torr的范围的压力下提供WF6、B2H6和SiH4的组合中的一种或更多的气体来沉积WSix层571，且然后在NH3的气氛下氮化WSix层571的表面，从而在WSix层571的表面上形成WSixNy层572，由此形成了WSix层571和WSixNy层572的叠层570。
还可以使用B2H6气体以外的BH3或B10H14气体并使用SiH4气体以外的Si2H6或SiH2Cl2气体来沉积WSix层571。对WSix层571表面的氮化可以通过使用NH3气体以外的N2H4的气体来进行，且还可以通过由形成N2和N2/H2等离子体而提供包括N的自由基来进行。
同时，可以通过提高半导体基板500的温度或可以通过热处理工艺来进行对WSix层571表面的氮化，以利于有效的氮化处理。
在图5中，510代表第一层间绝缘层；530a代表Ta层；530b代表TaN层；530代表第一扩散阻挡层；且540代表下Cu布线。
如上所述，本发明使用W基层作为下Cu布线和上Al布线之间的扩散阻挡层。与比如Ti层和TiN层的叠层的常规扩散阻挡层相比，W基层具有出色的扩散阻挡特性，有效地抑制了下Cu布线和上Al布线之间的金属扩散。
如上所述，当在超高集成器件中形成接触上Al布线的下Cu布线的多层金属布线结构时，本发明提供了用于有效抑制上和下金属布线之间的金属扩散的出色的扩散阻挡。本发明还抑制了通过金属布线之间的金属扩散产生高电阻金属化合物，由此改善了器件可靠性和性能特性。
而且，本发明提供了比堆叠的Ti和TiN层的常规扩散阻挡层更薄的扩散阻挡，由此降低了接触电阻。
虽然为了说明的目的描述了本发明的具体实施方式，然而本领域的技术人员可以理解在不脱离由所附权利要求所界定的本发明的精神和范围的情况下，可以进行各种修改、添加和替代。
本发明要求于2006年12月28日提交的韩国专利申请No.10-2006-0137204的优先权，其全文引入于此作为参考。

Claims (14)

1.一种半导体器件的多层金属布线，包括：
下Cu布线；
上Al布线，形成于下Cu布线上方且电接触下Cu布线；和
W基扩散阻挡层，形成于下Cu布线和上Al布线之间，
其中W基扩散阻挡层包括WSix层和WSixNy层的叠层。
2.根据权利要求1所述的半导体器件的多层金属布线，其中WSix层和WSixNy层的叠层具有50到
Figure FSB00000029856800011
的厚度。
3.根据权利要求1所述的半导体器件的多层金属布线，其中上Al布线层包括形成于扩散阻挡层上的Al成核生长层。
4.根据权利要求3所述的半导体器件的多层金属布线，其中Al成核生长层具有50到
Figure FSB00000029856800012
的厚度。
5.一种半导体器件的多层金属布线的形成方法，包括：
在半导体基板上方形成下Cu布线；
在下Cu布线上形成W基扩散阻挡层；和
在包括W基扩散阻挡层的下Cu布线上方来形成上Al布线，
其中W基扩散阻挡层包括WSix层和WSixNy层的叠层。
6.根据权利要求5的半导体器件的多层金属布线的形成方法，其中WSix层和WSiNy层的叠层具有50到
Figure FSB00000029856800013
的厚度。
7.根据权利要求5的半导体器件的多层金属布线的形成方法，其中WSix层和WSiNy层的叠层通过沉积WSix层和氮化WSix层的表面来形成。
8.根据权利要求5的半导体器件的多层金属布线的形成方法，其中WSix层以ALD方法或CVD方法沉积。
9.根据权利要求7的半导体器件的多层金属布线的形成方法，其中WSix层在300到500℃的范围的温度和0.01到10Torr的范围的压力的条件下沉积。
10.根据权利要求7的半导体器件的多层金属布线的形成方法，其中对WSix层表面的氮化通过在NH3、N2H4、N2、和N2/H2的任一的气氛下的热处理或等离子体处理来进行。
11.根据权利要求5的半导体器件的多层金属布线的形成方法，还包括在形成上Al布线之前在扩散阻挡层上形成Al成核生长层。
12.根据权利要求11的半导体器件的多层金属布线的形成方法，其中Al成核生长层基于CVD方法而具有50到
Figure FSB00000029856800021
的厚度。
13.根据权利要求5的半导体器件的多层金属布线的形成方法，包括：
形成上Al布线的方法包括基于PVD方法在200到400℃的范围的温度在扩散阻挡层上方沉积Al层；以及
在400到500℃的范围的温度对Al层进行热处理的步骤。
14.根据权利要求5的半导体器件的多层金属布线的形成方法，还包括：
在150到200℃的范围的温度以PVD方法在扩散阻挡层上方沉积第一Al层；且
在200到450℃的范围的温度以PVD方法在第一Al层上方沉积第二Al层。
CN2007101082704A 2006-12-28 2007-06-07 半导体器件的多层金属布线及其形成方法 Expired - Fee Related CN101211892B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060137204A KR100842914B1 (ko) 2006-12-28 2006-12-28 반도체 소자의 금속배선 형성방법
KR137204/06 2006-12-28

Publications (2)

Publication Number Publication Date
CN101211892A CN101211892A (zh) 2008-07-02
CN101211892B true CN101211892B (zh) 2011-11-09

Family

ID=39582746

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101082704A Expired - Fee Related CN101211892B (zh) 2006-12-28 2007-06-07 半导体器件的多层金属布线及其形成方法

Country Status (3)

Country Link
US (2) US20080157367A1 (zh)
KR (1) KR100842914B1 (zh)
CN (1) CN101211892B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492878B2 (en) 2010-07-21 2013-07-23 International Business Machines Corporation Metal-contamination-free through-substrate via structure
US20120273950A1 (en) * 2011-04-27 2012-11-01 Nanya Technology Corporation Integrated circuit structure including copper-aluminum interconnect and method for fabricating the same
CN110571189B (zh) * 2018-06-05 2022-04-29 中芯国际集成电路制造(上海)有限公司 导电插塞及其形成方法、集成电路
CN111696918A (zh) * 2020-07-15 2020-09-22 华虹半导体(无锡)有限公司 互连结构的制作方法及器件
US20220367260A1 (en) * 2021-05-12 2022-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal nitride diffusion barrier and methods of formation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1195188A (zh) * 1997-03-31 1998-10-07 摩托罗拉公司 扩散阻挡层的淀积方法
CN1788336A (zh) * 2004-04-12 2006-06-14 株式会社爱发科 隔离膜的形成方法及电极膜的形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970001883B1 (ko) * 1992-12-30 1997-02-18 삼성전자 주식회사 반도체장치 및 그 제조방법
US6187673B1 (en) * 1998-09-03 2001-02-13 Micron Technology, Inc. Small grain size, conformal aluminum interconnects and method for their formation
KR20030058261A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 듀얼다마신공정을 이용한 금속배선 형성 방법
US6797642B1 (en) * 2002-10-08 2004-09-28 Novellus Systems, Inc. Method to improve barrier layer adhesion
US6913994B2 (en) 2003-04-09 2005-07-05 Agency For Science, Technology And Research Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1195188A (zh) * 1997-03-31 1998-10-07 摩托罗拉公司 扩散阻挡层的淀积方法
CN1788336A (zh) * 2004-04-12 2006-06-14 株式会社爱发科 隔离膜的形成方法及电极膜的形成方法

Also Published As

Publication number Publication date
US20080157367A1 (en) 2008-07-03
US20100193956A1 (en) 2010-08-05
CN101211892A (zh) 2008-07-02
US8008774B2 (en) 2011-08-30
KR100842914B1 (ko) 2008-07-02

Similar Documents

Publication Publication Date Title
US7872351B2 (en) Multi-layered metal line of semiconductor device for preventing diffusion between metal lines and method for forming the same
KR20070028574A (ko) 반도체장치 및 그 제조방법
CN101188210A (zh) 半导体结构的形成方法
CN101211892B (zh) 半导体器件的多层金属布线及其形成方法
US7531902B2 (en) Multi-layered metal line of semiconductor device having excellent diffusion barrier and method for forming the same
JP2007150301A (ja) 半導体装置およびその製造方法
KR100924556B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
US7902065B2 (en) Multi-layered metal line having an improved diffusion barrier of a semiconductor device and method for forming the same
US7875978B2 (en) Metal line having a multi-layered diffusion layer in a semiconductor device and method for forming the same
KR100701673B1 (ko) 반도체 소자의 구리 배선 형성방법
KR20080114056A (ko) 반도체 소자의 배선 및 그의 형성방법
KR100967130B1 (ko) 반도체 소자의 금속배선 및 그의 형성방법
KR100307827B1 (ko) 반도체소자의 금속배선 콘택 형성방법
JP2003218201A (ja) 半導体装置およびその製造方法
KR100935193B1 (ko) 반도체 소자의 금속배선 및 그의 형성방법
US20090001583A1 (en) Method of manufacturing semiconductor device
KR20100036008A (ko) 반도체 소자의 금속배선 형성방법
JP2006073792A (ja) 半導体装置および半導体装置の製造方法
KR100721195B1 (ko) 반도체 소자의 듀얼 다마신 금속 배선 형성 방법
KR100728965B1 (ko) 반도체 소자의 제조방법
KR20050040552A (ko) 반도체 장치의 구리 배선 형성 방법.
TW395040B (en) Metallization process of integrating tungsten plug and copper interconnect
KR20080061965A (ko) 반도체 소자의 금속배선 형성방법
JPH0235753A (ja) 半導体装置の製造方法
KR20090034037A (ko) 반도체 소자의 금속배선 및 그의 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111109

Termination date: 20130607