CN1754257A - 层状硬膜和介电材料及其方法 - Google Patents

层状硬膜和介电材料及其方法 Download PDF

Info

Publication number
CN1754257A
CN1754257A CNA028142756A CN02814275A CN1754257A CN 1754257 A CN1754257 A CN 1754257A CN A028142756 A CNA028142756 A CN A028142756A CN 02814275 A CN02814275 A CN 02814275A CN 1754257 A CN1754257 A CN 1754257A
Authority
CN
China
Prior art keywords
layer
electronic device
poly
hard membrane
etch stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA028142756A
Other languages
English (en)
Inventor
L·福雷斯特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Publication of CN1754257A publication Critical patent/CN1754257A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3125—Layers comprising organo-silicon compounds layers comprising silazane compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31652—Of asbestos
    • Y10T428/31663—As siloxane, silicone or silane

Abstract

一种镶嵌结构包括以液相形式涂布在线路介电层上的硬膜层。预期的硬膜层包含Si－N键并被致密化使得该镶嵌结构中的硬膜层的耐蚀性大于线路介电层的耐蚀性和通孔介电层的耐蚀性。特别优选的硬膜层包含聚全氢硅氮烷。

Description

层状硬膜和介电材料及其方法
技术领域
发明的领域是微电子器件的制造，特别涉及耐蚀材料的镶嵌(damascene)加工和沉积方法。
背景技术
目前，铝或铝合金是在集成电路中电子互连最常用的导电材料。铝合金一般具有许多理想的特性，包括对硅具有较强的附着力、较低的电阻率。然而，由于小型化的发展，铝的电阻率变得不可忽视，成为电路中电容-电阻(RC)时间延迟的重要影响因素。随着小型化的进一步发展，因为电迁移、应力引发形成的空隙和电流密度的局限性，铝的使用已经变得问题越来越大。于是，鉴于集成电路中元件尺寸的持续减小，越来越多的兴趣集中在发现互连结构中的替代导电材料。
因为铜和铜合金具有较大的坚韧性和较高的电导率，它们成为一种特别有希望的替代材料。例如，铜的电阻率比铝的电阻率低大约40％，同时有较少的可靠性问题如电迁移，等等。然而，铜比铝合金更难蚀刻，一般不能用常规金属化方法加工，在常规金属化中，在基底上沉积金属层并进行蚀刻形成导电线路，并且导线和导线之间的空隙随后用线状电介质填充。为了避免在制备互连结构过程中至少一些使用铜带来的问题，已经发展了一种新的制备互连的方法，也称为镶嵌方法。
在一种典型的镶嵌方法中，在介电层的表面蚀刻一种线路图案，用这种方法形成的沟槽，通过电镀、化学镀、或者溅射法用铜充填。在铜沉积在整个表面后，使用化学-机械平面化(CMP)步骤来去除过多的铜，并为了后继的处理步骤对晶片进行平面化。这种方法通常重复数次，在多层互连结构中形成通孔和线路。
为了进一步改进镶嵌方法，通孔和线路形成过程可以集成为一种单一方法，即所谓双重镶嵌法。在双重镶嵌法中，通孔介电层敷设在基底上，该通孔介电层随后用图案化的腐蚀停止层涂敷，由此在腐蚀停止层中的空隙与将要被蚀刻到通孔介电层中的通孔位置相对应。在下一个步骤中，线路介电层沉积在腐蚀停止层上，其又用图案化的硬膜(hard mask)层涂敷，后者确定线路的迹线。在其次的步骤中，形成通孔和线路的迹线，借此线路沟槽被蚀刻在线路介电层中，直到蚀刻剂到达蚀刻停止层。在没有蚀刻停止层的位置，蚀刻过程连续通过通孔电介质形成通孔。与镶嵌法中一样，蚀刻通孔和线路迹线用铜填充(在涂布Ta(N)隔离层和Cu籽晶层后)以及CMP步骤完成双重镶嵌法。一种典型的双重镶嵌法描述在Yew，T.的US5801094中，其并入本文作为参考。
虽然双重镶嵌法比镶嵌法更为有效，但是它需要额外的具有不同蚀刻选择性的介电材料层的连续沉积。关于通孔和线路介电层的沉积，涂布通孔和线路介电材料的这种较快的有效方法是本领域已知的。然而，因为硬膜和腐蚀停止材料的特别化学构成，沉积一般局限于化学气相沉积(CVD)。CVD通常需要单独的生产环境，即具有降低的气体压力和较高的温度，因此至少部分地使线路和通孔电介质的选择限于能够经受住相对苛刻条件的材料。而且，由于取决于硬膜和腐蚀停止材料，CVD步骤经常是耗费时间的且经常给生产增加额外的费用。已知的硬膜和腐蚀停止材料的另一个缺点是它们介电常数(K值)较高。例如，典型的硬膜和腐蚀停止材料，包括SiN、SiON和SiO2具有不符合要求的高介电常数，范围分别为大约7-4。
当需要多重镶嵌结构层时会发生另一个问题。因为铜具有较快的扩散速度，一般需要扩散阻挡层把一个镶嵌层的铜迹线与另一个镶嵌层的通孔电介质分开。扩散阻挡层通常包括钨、钽或各种氮化物或碳化物，包括氮化钛、氮化钨、碳化钛或氮化钽，一般通过化学气相沉积法涂布。另外，TixAlyNz或铝润湿层可以通过CVD或物理气相沉积(PVD)技术沉积作为扩散阻挡层，如US5939788中所述，该专利并入本文作为参考。通过CVD或PVD涂布阻挡层确实可以进行相对受控的沉积，然而，会增加制备多层双重镶嵌结构的额外的生产时间并且通常显著增大成本。
虽然使用具有不同蚀刻选择性的层状介电材料能使铜在微电子器件的生产中得到集成，沉积层状介电材料的已知方法经常是较昂贵的，或者使用具有较高介电常数的材料。于是，需要提供改进的组合物和方法来生产具有相互不同蚀刻选择性的层状介电材料。
发明内容
本发明涉及电子器件和相关的方法，其中电子器件包含用液相涂布到线路介电层(优选地采用旋压(spin-on)法)的硬膜层，其中硬膜层包含Si-N键，和其中硬膜层致密化到使硬膜层的蚀刻速率小于线路介电层和介电层的蚀刻速率。进一步预期的是，硬膜层、线路介电层、通孔介电层和铜元素形成一种双重镶嵌结构。
本发明主题的一个方面，线路介电层包含一种无机低介电常数材料，或一种有机低介电常数材料，优选的是聚芳撑醚、聚芳撑、聚酰亚胺或氰酸盐酯类树脂。用于硬膜层的特别优选材料包含聚全氢硅氮烷例如(SiH2-NH)n，n＝2-2000。
本发明主题的另一个方面，硬膜层使用选自炉固化法、快速热退火法、电炉退火法、以及电子束法中的一种方法进行致密化。进一步优选的镶嵌结构包括以液相涂布到硬膜层上的扩散阻挡层，扩散阻挡层包含Si-N键。
由下面的本发明优选实施例以及附图的详细描述，本发明的各个目的、特性、方面和优点将会更清楚，在附图中，相同的数字代表相同的部件。
附图简述
图1是根据本发明主题的一种方法的流程图。
图2是根据本发明主题的另一种方法的流程图。
图3是根据本发明主题的双重镶嵌结构的垂直截面侧视图。
图4是根据本发明主题的含Si-N键硬膜材料的典型分子式。
发明详述
在本文中使用的术语‘低介电常数’指的是介电常数(k值)小于10。特别预期的是介电常数小于6，更优选小于3。
在本文中使用的术语“对蚀刻剂的耐蚀性”，用来表征蚀刻剂溶解、或物理或化学分解基底的速率和/或动力学。低耐蚀性对应于基底以较高速率溶解，反之，高耐蚀性对应于基底以较低速率溶解。术语“对蚀刻剂的耐蚀性”不一定描述基底或蚀刻剂的本征特性，而是描述一种特定基底与一种特定蚀刻剂之间的相互作用。例如，SiO2对H2O有很高的耐蚀性，然而，相同的材料对HF具有低的耐蚀性。类似地，丙酮对于聚苯乙烯是强蚀刻剂，但是对SiO2是弱蚀刻剂。
在这里进一步使用的术语‘蚀刻剂’指的是一种能够溶解、和/或化学或物理降解基底的试剂。蚀刻剂可存在为许多形式，包括液体、液体混合物、气体、等离子体或电子束。
现在转向图1，方法100包括一个提供表面的步骤110，其中低介电常数材料沉积在所述表面上形成第一层。在另一个步骤120中，腐蚀停止层以液相形式涂布在第一层上，其中腐蚀停止层包括一种包含Si-N键的材料。在更进一步的步骤130中，腐蚀停止层采用选自炉固化法、快速热退火法、电炉退火法、以及电子束法中的一种方法来致密化。该方法可进一步包括在腐蚀停止层上沉积一层扩散阻挡层，在图2中描述了这个方法。在步骤240中略述了扩散阻挡层沉积在腐蚀停止层表面上，扩散阻挡层以液相形式沉积在致密化的腐蚀停止层上，其中，扩散阻挡层包括一种包含Si-N键的材料。
因此，特别预期的电子器件可包括一种双重镶嵌结构，如图3所示。这里，典型的双重镶嵌结构300的垂直横截面，包括铜填充的通孔315，通孔315嵌入在通孔电介质310和腐蚀停止层320。铜线路335嵌入在线路电介质330和硬膜340中，扩散势垒350层是覆盖硬膜340和铜线路335的顶层。
在本发明主题的特定方面，使用本领域中已知的常规方法和组合物形成双重镶嵌结构的通孔介电层和腐蚀停止层。例如，形成通孔介电层和腐蚀停止层采用的合适材料和方法在Yew，T.等人的U.S.5801094、或Ireland等人的U.S.5466639中描述，其并入本文作为参考。在进一步的步骤中，(腐蚀停止层的典型后续处理)线路介电层沉积在腐蚀停止层的表面。线路介电层的优选材料是氧化硅，它通过低压CVD(LPCVD)方法，使用正硅酸乙酯(TEOS)作为气源，沉积在腐蚀停止层的表面作为一种低介材料，厚度为几千个埃。在另一个步骤中，在1000-4000转/分下，用0.5％(重量百分数)的聚全氢硅氮烷的邻二甲苯溶液通过旋涂法，将聚全氢硅氮烷沉积在氧化硅表面上作为第二种低介材料，在350℃固化大约120分钟形成硬膜层.
关于线路介电层，预期的是各种有机的、含硅的和无机的低介电常数材料适合于形成线路电介质，线路电介质的优选材料包含氧化硅。然而，只要线路电介质用的低介电常数材料对蚀刻剂具有比硬膜层更低的耐蚀性，许多替代低介电常数材料也可以考虑。当希望介电材料的耐温性更高时、当希望CVD沉积第一种低介材料时、或者在用途要求蚀刻剂得自包含碳氟化合物如C4F8/CO或CF4/CHF3的混合物时，无机低介电常数材料可能是特别有利的。例如，预期的无机材料包括改性二氧化硅和氧化铝。在避免用CVD沉积第一层低介电常数材料的用途中，特别合适的有机材料包括聚芳撑醚、聚芳撑、聚酰亚胺以及氰酸盐酯类树脂。于是，有机材料特别预期的是可以通过各种替代方法涂布在表面上，包括旋涂法、浸涂法、刮刀法等等。其它的应用可能更偏向于使用可以进行第一低介电常数材料固化或交联程度的有机材料。所以，特别考虑的是可从单体或嵌段单体聚合和/或交联的低介电常数材料。例如，所预期的材料包括衍生的和非衍生的聚芳撑、聚酯、聚酰亚胺、聚氮茚、聚亚苯基等等。含硅低介材料公开于共同转让的U.S6143855中并包括HOSPTM(旋压混合硅氧烷-有机聚合物，从Honeywell可以购买)。
可以认可的是，虽然线路介电层优选具有几千个埃的厚度，线路介电层的厚度在大约50埃或更小与几百个微米之间显著变化。例如，在需要薄的介电夹层而不需要专用结构(例如，通孔、线路、或其它功能或结构单元)的应用中，厚度大约100埃可能就足够了。然而，在其上沉积第一层的表面明显不均匀和需要平面化步骤的应用中，最小厚度远超过8000埃。
关于沉积线路介电层用低介电常数材料的方法，应当理解线路介电层选择的材料一般指明采用的特定方法，因此，线路介电层不一定通过TEOS作为气源的LPCVD方法敷设。另外，还可以考虑在本领域中众所周知的各种方法，包括CVD、PVD、旋涂法、浸涂法、刮刀法等等。当线路介电材料和硬膜层通过旋涂法沉积时，旋涂法可能是特别具有优势的。
在本发明主题的另外一个方面中，硬膜用材料不需要局限于聚全氢硅氮烷，替代材料包括各种包含有机和无机材料的低介电常数材料，只要(a)替代材料可以以液相涂布和(b)替代材料对蚀刻剂的耐蚀性高于线路介电材料对蚀刻剂的耐蚀性。特别考虑的替代材料包括简单和复合聚硅氮烷。本文所用的聚硅氮烷包含具有至少一个Si-N键的重复单元。简单聚硅氮烷可包括取代或未取代的具有单一Si-N键的重复性单体，而复合聚硅氮烷可以具有取代和未取代的重复性单体，其中Si-N-基团含多余的杂原子，包括C、O、B等等(下文)。进一步考虑的材料包括单体的、低聚的和多聚形式的有机和含硅低介材料。合适的有机材料可能有利地在各种溶剂中具有高溶解度、与其它有机材料的混溶性、低粘度、高间隙填充潜力以及大约低于6或更小的介电常数。有机材料可进一步允许进行希望的物理化学特性的微调，例如吸湿性、柔性、交联度等等。预期的有机材料包括聚苯、聚酰亚胺、聚酰胺、环氧聚合物、聚醚、聚酯等等，或它们各自的前驱体。当对蚀刻条件的耐蚀性增强(例如，氧等离子体蚀刻法)是特别地合乎需要时，特别考虑无机材料。例如，各种聚硅氮烷，包括聚全氢硅氮烷，对氧等离子体蚀刻具有良好的耐蚀性。
应当理解的是添加剂可加入到硬膜低介材料中。例如，在一些应用中，可使用添加剂来增加对一些特殊蚀刻条件的耐蚀性(例如，通过化学法抑制(quenching)蚀刻剂，或通过硬膜材料的额外交联)。在其它应用中，可加入添加剂来增强对线路介电层的附着力。在其它应用中，可加入添加剂来降低材料的介电常数。添加剂的浓度从一个实例到另一个实例可以变化，但是一般说来添加剂通常不超过35％(按重量计)。
在替代实施方案的另一个方面，硬膜材料的沉积方法在若干应用中可以变化并且不需要局限于旋涂法，只要低介电常数硬膜材料是液相涂布层(即用液相涂布)。预期的方法包括辊涂法、浸涂法、旋涂法等等。假如硬膜层的厚度并不重要时，还可以考虑应用的其它方法，包括刷涂法或冲洗法。对于涂敷厚膜材料，有许多合适的溶剂，实际的溶剂随需要的介电材料而变化。例如，预期的溶剂包括极性和非极性溶剂，以及质子溶剂和质子惰性的溶剂。无论用什么沉积方法，应当理解的是形成的中间体包括第一介电材料，第二介电材料和液相。例如，在双重镶嵌结构中，中间体可以在液相中包括线路介电层和硬膜层。在另一个实施例中，中间体可以在液相中包括线路介电层、硬膜层和扩散阻挡层。
关于硬膜层的致密化，预期的是除了在350℃下焙烧60分钟以外的各种固化条件也是适当的。例如，根据所用的材料类型，可以考虑60分钟到10分钟或更短的固化时间。更短的固化时间可有利地导致热应力减小、生产时间缩短或物料流增加。然而，当实施具有较慢固化速率的低介电材料时，固化可能进行更长的时间，即60-120分钟到几个小时。固化时间可以延长到完全驱出残留溶剂，特别是当使用非水溶剂时。另外，硬膜层可使用炉固化法、快速热退火法、电炉退火法和电子束法，所有这些方法都是本领域技术人员熟知的。关于替代的致密化方法的持续时间和条件，预期的是特定致密化方法通常依赖于所用的特定材料，并且本领域技术人员能容易地确定而不用做不适当的实验。
在本发明主题的另一个替代方面，一种额外的扩散阻挡层沉积在硬膜(和铜导体)的表面上来防止或减小铜扩散。在一种示例性方法中，在构造双重镶嵌结构时，使用正硅酸乙酯(TEOS)作为气源通过低压CVD(LPCVD)方法形成线路介电层，把氧化硅作为低介电材料沉积在腐蚀停止层的表面，厚度为几千个埃。聚全氢硅氮烷然后沉积在氧化硅表面上，用5％(按重量计算)聚全氢硅氮烷的邻二甲苯溶液，通过以1000-4000rpm旋涂，在350℃固化大约120分钟形成硬膜层。在硬膜层图案化、蚀刻、铜填充和CMP以后，用5％(按重量计算)聚全氢硅氮烷的邻二甲苯溶液通过在1000-4000rpm旋涂法，在350℃固化大约60分钟，把扩散阻挡层沉积在镶嵌结构表面上。关于线路介电层各个方面和硬膜层的各个方面，应用上面讨论的相同考虑事项。关于扩散阻挡层的材料，预期的是可以使用除了聚硅氮烷以外的许多材料来形成扩散阻挡层，只要扩散阻挡层作为线路介电层对蚀刻剂具有高的耐蚀性。例如，扩散阻挡层材料可以是有机的或无机的聚合物，或聚合物的前驱体(上文)。同样应当理解的是扩散阻挡层材料不必在几个加工步骤之后沉积(例如，图案化、蚀刻、铜填充和CMP)。例如，有些应用可能需要对反蚀刻(back etching)具有较高耐蚀性的附加第三层低介材料。
可以预期的是，在一些实施方案中，双重镶嵌结构可包括线路介电层、沉积在线路介电层表面的腐蚀停止层、沉积在腐蚀停止层顶部的通孔介电层、以及沉积在通孔介电层顶部的硬膜层，其中腐蚀停止层和硬膜层中的至少一种是液相涂布层，且其中腐蚀停止层和硬膜层中的至少一种包含硅。在其它的实施方案中，腐蚀停止层和硬膜层可以都是液相涂布层，腐蚀停止层和硬膜层可能包含硅。在更进一步的实施方案中，双重镶嵌结构可能包括额外的扩散阻挡层，其中扩散阻挡层是一种液相涂布层，并且其中扩散阻挡层包含硅。关于腐蚀停止层、硬膜层和扩散阻挡层的化学组成，预期的是所述的每一层可有利地包含聚硅氮烷和/或聚全氢硅氮烷。同时应当理解的是腐蚀停止层、硬膜层和扩散阻挡层的至少一种是液相涂布层。
图4表示聚硅氮烷的通式结构，n通常为2到20000。当R1＝R2＝R3＝H时，以及A是一个键时，则聚硅氮烷称为聚全氢硅氮烷。当A是一个键时，以及R1＝R2＝H，R3是一种有机取代基时，则聚硅氮烷称为简单聚硅氮烷。有机取代基可包含各种原子，优选的是C、N或S，并且分子量最高约120Da。预期的取代基包括苯基、乙炔基、三氟甲基和氨基。优选的取代基是增加对蚀刻剂耐蚀性的化学基团，特别包括氧等离子体。同样应当理解的是R1和R2不需要是相同的，并且可以不是H。例如，合适的取代基可以包括含有C、N、O和S以及Si和Al的取代基。特别预期的是R1和/或R2可能是聚硅氮烷的分支点，即另一种聚硅氮烷可起源于R1和/或R2。当A不是一个键时，聚硅氮烷称为复合聚硅氮烷。可以预期的是A不仅可能是单个原子，包含O或S，而且可以是包含杂原子的取代基，杂原子包括C、O、N、卤素等等。关于分子量，可以预期的是合适的取代基的分子量要小于150Da。同时可以预期的是在复合聚硅氮烷中，不超过6个原子把一个单体中的一个硅原子与另一单体中的一个硅原子分开。特别优选的取代基可能有利地影响物理化学特性，例如，附着力、低介电常数或阻燃性。简单或复合聚硅氮烷的其它预期变化形式描述于Kaya等人的U.S.5459114以及Nakahara等人公开的U.S.5905130中，它们并入本文作为参考。
因此，已经公开了层合电介质结构的具体实施方案和应用。但是，应当清楚，对于本领域技术人员，除了那些已经描述之外的更多改善是可能的，而不会脱离这里的本发明概念。所以，除了所附权利要求的实质以外，本发明主题不受限制。而且，在解释说明书和权利要求时，所有的术语应当以与上下文一致的最宽可能方式解释。特别是术语“包含”和“含有”应当以非排它的方式解释为元素、化合物、或步骤，表明所提及的元素、化合物或步骤可以存在、利用或与其它未明确提及的元素、化合物或步骤相结合。

Claims (20)

1.一种电子器件，包括：
以液相涂布在线路介电层上的硬膜层，其中该硬膜层包含Si-N键，且其中硬膜层被致密化使该硬膜的耐蚀性比线路介电层的耐蚀性和通孔介电层的耐蚀性都要高；
和其中硬膜层、线路介电层、通孔介电层和铜元素被构造形成双重镶嵌结构。
2.权利要求1的电子器件，其中线路介电层包含有机低介电常数材料。
3.权利要求2的电子器件，其中有机低介电常数材料选自聚芳撑醚、聚芳撑、聚酰亚胺和氰酸盐酯类树脂。
4.权利要求1的电子器件，其中用液相涂布硬膜层包括旋涂法。
5.权利要求1的电子器件，其中硬膜层由聚全氢硅氮烷制成。
6.权利要求5的电子器件，其中聚全氢硅氮烷具有表示为(SiH2-NH)n的结构，其中n是2到2000的整数。
7.权利要求1的电子器件，其中硬膜层使用选自炉固化法、快速热退火法，电炉退火法和电子束法中的一种方法进行致密化。
8.权利要求1的电子器件，其进一步包含扩散阻挡层，其中扩散阻挡层以液相涂布到硬膜层上，且其中的扩散阻挡层包含Si-N键。
9.权利要求8的电子器件，其中扩散阻挡层包含Si-N键。
10.权利要求9的电子器件，其中扩散阻挡层用聚全氢硅氮烷制成。
11.权利要求10的电子器件，其中聚全氢硅氮烷具有表示为(SiH2-NH)n的结构，其中n是2到2000的整数。
12.一种形成双重镶嵌结构的方法，包括：
提供表面和在该表面上沉积低介电常数材料形成第一层。
在第一层上以液相涂布腐蚀停止层，其中腐蚀停止层包含含有Si-N键的材料；和使用选自炉固化法、快速热退火法、电炉退火法和电子束法中的一种方法来致密化腐蚀停止层。
13.权利要求12的方法，还包括扩散阻挡层以液相形式涂布在致密化的腐蚀停止层上，其中扩散阻挡层包含含有Si-N键的材料。
14.权利要求13的方法，其中双重镶嵌结构进一步包含铜作为导电材料。
15.权利要求12的方法，其中低介电常数材料包含有机低介电常数材料。
16.权利要求15的方法，其中有机低介电常数材料选自聚芳撑醚、聚芳撑、聚酰亚胺和氰酸盐酯类树脂。
17.权利要求13的方法，其中扩散阻挡层材料是聚硅氮烷或聚全氢硅氮烷。
18.权利要求17的方法，其中聚全氢硅氮烷具有表示为(SiH2-NH)n的结构，其中n是2到2000的整数。
19.权利要求13的方法，其中使腐蚀停止层致密化的步骤使用电子束法。
20.权利要求13的方法，其中腐蚀停止层和扩散阻挡层用聚全氢硅氮烷制成。
CNA028142756A 2001-05-17 2002-05-17 层状硬膜和介电材料及其方法 Pending CN1754257A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/860,993 US6656532B2 (en) 2001-05-17 2001-05-17 Layered hard mask and dielectric materials and methods therefor
PCT/US2002/015829 WO2002093641A1 (en) 2001-05-17 2002-05-17 Layered hard mask and dielectric materials and methods therefor

Publications (1)

Publication Number Publication Date
CN1754257A true CN1754257A (zh) 2006-03-29

Family

ID=25334585

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA028142756A Pending CN1754257A (zh) 2001-05-17 2002-05-17 层状硬膜和介电材料及其方法

Country Status (6)

Country Link
US (1) US6656532B2 (zh)
EP (1) EP1390976A1 (zh)
JP (1) JP2004538624A (zh)
KR (1) KR20040012833A (zh)
CN (1) CN1754257A (zh)
WO (1) WO2002093641A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100362834B1 (ko) * 2000-05-02 2002-11-29 삼성전자 주식회사 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치
US7053005B2 (en) * 2000-05-02 2006-05-30 Samsung Electronics Co., Ltd. Method of forming a silicon oxide layer in a semiconductor manufacturing process
US6623654B2 (en) * 2001-11-09 2003-09-23 Taiwan Semiconductor Manufacturing Company Thin interface layer to improve copper etch stop
DE10219122B4 (de) * 2002-04-29 2005-01-05 Infineon Technologies Ag Verfahren zur Herstellung von Hartmasken
US7187081B2 (en) * 2003-01-29 2007-03-06 International Business Machines Corporation Polycarbosilane buried etch stops in interconnect structures
US6803660B1 (en) * 2003-01-29 2004-10-12 International Business Machines Corporation Patterning layers comprised of spin-on ceramic films
US7081673B2 (en) * 2003-04-17 2006-07-25 International Business Machines Corporation Multilayered cap barrier in microelectronic interconnect structures
JP4517791B2 (ja) * 2004-09-10 2010-08-04 凸版印刷株式会社 窒化シリコン膜を用いたパターン形成方法
KR100727439B1 (ko) * 2005-03-22 2007-06-13 주식회사 하이닉스반도체 금속 배선 형성 방법
DE102008013446A1 (de) * 2008-02-15 2009-08-27 Ersol Solar Energy Ag Verfahren zur Herstellung monokristalliner n-Silizium-Solarzellen sowie Solarzelle, hergestellt nach einem derartigen Verfahren
KR200458283Y1 (ko) * 2009-01-15 2012-01-31 임재희 수액 채취용 수액유출기
CN102446813B (zh) * 2010-10-13 2013-09-11 中芯国际集成电路制造(上海)有限公司 互连结构的制作方法
KR102271773B1 (ko) 2014-09-16 2021-07-01 삼성전자주식회사 반도체 소자 제조 방법
CN111876730A (zh) * 2020-06-24 2020-11-03 肇庆宏旺金属实业有限公司 一种钛金抗指纹不锈钢的制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891513A (en) 1996-01-16 1999-04-06 Cornell Research Foundation Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications
US6100195A (en) 1998-12-28 2000-08-08 Chartered Semiconductor Manu. Ltd. Passivation of copper interconnect surfaces with a passivating metal layer
US6218317B1 (en) 1999-04-19 2001-04-17 National Semiconductor Corp. Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US6329281B1 (en) 1999-12-03 2001-12-11 Agere Systems Guardian Corp. Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
US6294832B1 (en) 2000-04-10 2001-09-25 National Science Council Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method
US6358842B1 (en) * 2000-08-07 2002-03-19 Chartered Semiconductor Manufacturing Ltd. Method to form damascene interconnects with sidewall passivation to protect organic dielectrics

Also Published As

Publication number Publication date
US20020172898A1 (en) 2002-11-21
EP1390976A1 (en) 2004-02-25
JP2004538624A (ja) 2004-12-24
WO2002093641A1 (en) 2002-11-21
KR20040012833A (ko) 2004-02-11
US6656532B2 (en) 2003-12-02

Similar Documents

Publication Publication Date Title
KR101093915B1 (ko) 반도체 장치의 제조 방법
CN1754257A (zh) 层状硬膜和介电材料及其方法
KR100780986B1 (ko) 반도체장치 및 그 제조방법
US20080251284A1 (en) Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme
KR20040031695A (ko) 상호 접속 구조체, 및 로우-ｋ 유전체와 금속 도체 상호접속 구조체를 제조하는 방법
JPH10189716A (ja) 半導体装置およびその製造方法
KR100481905B1 (ko) 복수의 배선층을 갖는 반도체 장치 및 그 제조 방법
EP0933814A1 (en) A metallization structure on a fluorine-containing dielectric and a method for fabrication thereof
JP2006019480A (ja) 半導体装置の製造方法
JP3992654B2 (ja) 半導体装置の製造方法
KR100569797B1 (ko) 다층 배선 구조의 제조 방법
JP4938222B2 (ja) 半導体装置
CN1107968C (zh) 在互连图形上形成平面化介质层的方法及多层互连图形结构
JP3465411B2 (ja) 半導体装置の層間絶縁膜
JP2002134612A (ja) 半導体装置及びその製造方法
CN100423226C (zh) 双镶嵌结构的制造方法
JP2003273216A (ja) 半導体装置およびその製造方法
US7576001B2 (en) Manufacturing method for semiconductor device
JP4493278B2 (ja) 多孔性樹脂絶縁膜、電子装置及びそれらの製造方法
US20040134608A1 (en) Layered hard mask and dielectric materials and method therefor
US20070161156A1 (en) Semiconductor device and method of manufacturing the same
KR100475529B1 (ko) 확산방지막 형성방법 및 이를 이용한 반도체 소자의금속배선 형성방법
JP2000040740A (ja) 有機樹脂系絶縁膜を有する電子装置の製造方法
KR100440475B1 (ko) 반도체 소자의 제조 방법
KR20010030169A (ko) 감소된 정전 용량을 갖는 집적 회로의 유전체 구조물

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication