CN1741271A - 具有混合电介质层的半导体集成电路器件及其制造方法 - Google Patents

具有混合电介质层的半导体集成电路器件及其制造方法 Download PDF

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CN1741271A
CN1741271A CNA2005100922325A CN200510092232A CN1741271A CN 1741271 A CN1741271 A CN 1741271A CN A2005100922325 A CNA2005100922325 A CN A2005100922325A CN 200510092232 A CN200510092232 A CN 200510092232A CN 1741271 A CN1741271 A CN 1741271A
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郑镛国
元皙俊
权大振
宋珉宇
金元洪
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Samsung Electronics Co Ltd
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Abstract

在具有混合电介质层的半导体集成电路器件及其制造方法中，混合电介质层包含按顺序堆迭的下电介质层、中间电介质层和上电介质层。下电介质层包含铪(Hf)或锆(Zr)。上电介质层也包含Hf或Zr。中间电介质层由具有比下电介质层的低的依赖于电压的电容变化的材料层形成。

Description

具有混合电介质层的半导体集成电路器件及其制造方法
技术领域
本发明涉及半导体集成电路器件及其制造方法，更特别地涉及具有混合电介质层的半导体集成电路器件及其制造方法。
背景技术
半导体集成电路器件通常包含金属氧化物半导体(MOS)晶体管、电阻和电容器。电容器由相互重叠的上、下电极和插入在两电极之间的电介质层构成。电极可由掺杂的多晶硅层制成。然而，多晶硅层在随后的热处理期间又会被氧化，从而降低了电容器的电学特性。另外，依照施加在多晶硅电极上的电压大小，电容器会呈现出不同的电容量。例如，当上、下电极由N型杂质掺杂的多晶硅层构成并且在上电极上施加负电压时，会在下电极的表面感应产生空穴。因此，会在下电极的表面形成耗尽层。耗尽层的宽度随着施加在上电极上的负电压的大小而改变。结果，可依照施加在电极上的电压的大小来改变电容器的电容量。因此，使用多晶硅电极的电容器并不适合于要求精确电容器特性的半导体集成电路器件，例如，包含模拟电路的半导体集成电路器件。
另外，为了增加半导体集成电路器件的集成密度，希望使用具有高介电常数的材料来形成电容器的电介质层。然而，与例如氧化硅层的低k电介质层比较，高k电介质层会呈现出大的漏电流。
在Schuegraf的美国专利No.6,071,771中公开了使用高k电介质层制造电容器的方法，该专利名为“形成电容器和电容器结构的半导体处理方法(Semiconductor processing method of forming a capacitor and capacitorconstructions)”。依照Schuegraf，使用强化的(densified)Ta2O5层作为呈现少量漏电流的高k电介质层，并将氮化物层插入在Ta2O5层和电极之间以抑制在其间的界面处的氧化反应。
另外，在Haukka等人的标题为“制造集成电路中介电堆栈的方法(Methods for making a dielectric stack in an integrated circuit)”的美国专利No.6,660,660 B2中公开了改善高k电介质层的漏电流特性的方法。依照Haukka等人，氧化铝(AL2O3)层或氧化镧(LaO)层被用作在高k电介质层和电极之间的界面层。这些界面层起到氧化阻挡层和扩散阻挡层的作用。
发明内容
本发明的一实施例提供了半导体集成电路器件，该器件具有适合于改善响应于施加电压的电容均匀性(uniformity)以及改善漏电流特性的混合电介质层。
本发明的另一实施例提供了制造半导体集成电路器件的方法，该器件具有适合于改善响应施加电压的电容均匀性以及改善漏电流特性的混合电介质层。
在一个方面，本发明提出具有混合电介质层的半导体集成电路器件。半导体集成电路器件的混合电介质层包含按顺序堆迭的下电介质层、中间电介质层和上电介质层。下电介质层是包含铪(Hf)或锆(Zr)的材料层，并且中间电介质层是具有比下电介质层的低的依赖于电压的电容变化(voltagedependent capacitance variation)的材料层。此外，上电介质层包含铪(Hf)或锆(Zr)。
在一些实施例中，下电介质层可以是氧化铪(HfO)层、氧化锆(ZrO)层和氧化铪锆(HfZrO)层中的一种。另外，下电介质层可以是HfO层和ZrO层的组合层。例如，下电介质层可具有叠层结构，在该结构中HfO层和ZrO层交替重复地堆迭。
在其它实施例中，中间电介质层可以选自由氧化钽层、氧化钛层、BST(Ba，Sr，TiO3)层、STO(Sr，TiO3)层、PZT(Pb，Zr，TiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层。
在又一其它实施例中，上电介质层可以是氧化铪(HfO)层、氧化锆(ZrO)层和氧化铪锆(HfZrO)层中的一种。另外，上电介质层可以是HfO层和ZrO层的组合层。例如，下电介质层可具有叠层结构，在该结构中HfO层和ZrO层交替重复地堆迭。
在另一方面，本发明提出制造具有混合电介质层的半导体集成电路器件的方法。这些方法包括在集成电路衬底上形成包含铪(Hf)或锆(Zr)的下电介质层。在下电介质层上形成中间电介质层。中间电介质层由具有比下电介质层的低的依赖于电压的电容变化的材料层形成。在中间电介质层上形成包含Hf或Zr的上电介质层。
在一些实施例中，下电介质层可由氧化铪(HfO)层、氧化锆(ZrO)层和氧化铪锆(HfZrO)层中的一种形成。另外，下电介质层可以由HfO层和ZrO层的组合层形成。例如，下电介质层可由叠层结构形成，在该结构中HfO层和ZrO层交替重复地堆迭。可使用原子层沉积(ALD)技术或化学气相沉积(CVD)技术来形成下电介质层。
在其它实施例中，中间电介质层可以由选自由氧化钽层、氧化钛层、BST(BaSrTiO3)层、STO(SrTiO3)层、PZT(PbZrTiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层形成。可使用ALD技术或CVD技术来形成中间电介质层。
在又一其它实施例中，上电介质层可由氧化铪(HfO)层、氧化锆(ZrO)层和氧化铪锆(HfZrO)层中的一种形成。另外，上电介质层可由HfO层和ZrO层的组合层形成。例如，上电介质层可由叠层结构形成，在该结构中HfO层和ZrO层交替重复地堆迭。可使用ALD技术或CVD技术来形成上电介质层。
另一方面，本发明提出一种电容器，包括：在集成电路衬底上的下电极；在下电极上的下电介质层图案，下电极层包含铪(Hf)或锆(Zr)；在下电介质层图案上的中间电介质层图案，中间电介质层的依赖于电压的电容变化比下电介质层图案的低；在中间电介质层图案上的上电介质层图案，上电介质层包含铪(Hf)或锆(Zr)；以及在上电介质层图案上的上电极。
在一实施例中，下电极和上电极是金属层。
在另一方面，本发明提出一种电容器的制造方法，包括：在集成电路衬底上形成下电极层；在下电极上形成下电介质层，下电介质层包含铪(Hf)和锆(Zr)中的任一种；在下电介质层上形成中间电介质层，中间电介质层由这样的材料层形成，该材料层随着电压的改变而产生的电容的改变比下电介质层的低；在中间电介质层上形成上电介质层，上电介质层包含铪(Hf)和锆(Zr)中的任一种；在上电介质层上形成上电极；并且图案化上电极层、上电介质层、中间电介质层、下电介质层和下电极层以形成按顺序堆迭的下电极、下电介质层图案、中间电介质层图案、上电介质层图案和上电极。
在一实施例中，下电极层和上电极层由金属层形成。
附图说明
从对本发明优选实施例的更具体描述，如附图中说明的，本发明的前述的以及其它的目的、特征和优点将变得显而易见，在附图中，相同的参考符号在全部的不同图中指的是相同的部分。附图不必是按比例的，主要是为了说明本发明的原理。
图1和图2是示出依照本发明的实施例形成电容器的方法的剖面图。
图3和图4是示出依照本发明的另一实施例形成电容器的方法的剖面图。
图5是比较依照传统方法和依照本发明的实施例制造的电容器的漏电流特性的曲线图。
图6是示出依照传统方法和依照本发明的实施例制造的电容器的随着电压而改变的电容特性的曲线图。
具体实施方式
在下文中将参考附图更全面地描述本发明，其中示出了本发明的优选实施例。然而，可以以不同的形式来具体化本发明并且不应解释为限制于此处给出的实施例。而是给出这些实施例以使该公开变得彻底和完全。在附图中，为了清楚起见，层和区域的厚度被夸大了。整个说明书，相同的数字指相同的元件。
图1和图2是示出依照本发明的实施例形成电容器的方法的剖面图。
参考图1，在集成电路衬底1上形成层间绝缘层3。在层间绝缘层3上按顺序形成下电极层5、下电介质层7、中间电介质层9、上电介质层11和上电极层13。下电介质层7、中间电介质层9和上电介质层11构成混合电介质层12。下电介质层5和上电极层13可由金属层形成。例如，下电极层5和上电极层13中的每个都可由选自由钛(Ti)层、钽(Ta)层、氮化钛(TiN)、氮化钽(TaN)层、钨(W)层、氮化钨(WN)层、铝(Al)层、铜(Cu)层、钌(Ru)层、氧化钌(RuO)层、铂(Pt)层、铱(Ir)层和氧化铱(IrO)层组成的组中的至少一层形成。另外，例如，可使用物理气相沉积技术、原子层沉积(ALD)技术或金属有机CVD技术来形成下电极层5和上电极层13。
下电介质层7和上电介质层11由呈现比中间电介质层9相对更低的漏电流的材料层形成。换句话说，下电介质层7和上电介质层11由具有比中间电介质层9更大的能带隙的材料层形成。例如，下电介质层7和上电介质层11可由包含铪(Hf)或锆(Zr)的材料层形成。详细地，下电介质层7和上电介质层11可由氧化铪(HfO)层、氧化锆(ZrO)层和氧化铪锆(HfZrO)层中的一种形成。可选择地，下电介质层7可由HfO层和ZrO层的组合层形成。例如，可通过交替且重复地沉积HfO层和ZrO层来形成下电介质层7。即，下电介质层可由HfO层和ZrO层的叠层形成。上电介质层也可由HfO层和ZrO层的叠层形成。可在25℃到500℃的低温下使用原子层沉积(ALD)技术或CVD技术来形成下电介质层7和上电介质层11。
中间电介质层9由这样的材料层构成，该材料层随着电压的改变而产生的电容改变比下电介质层7和上电介质层11小。随着电压的改变而产生的电容改变是指当施加在电介质层上的电压增加或减少时电介质层的归一化(normalized)电容的变化。因此，中间电介质层9优选由具有不受电压影响的不变的电容的高k电介质层形成。例如，中间电介质层9可由选自由氧化钽层、氧化钛层、BST(BaSrTiO3)层、STO(SrTiO3)层、PZT(PbZrTiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层形成。
可在25℃到500℃的低温下任选使用原子层沉积技术或CVD技术来形成中间电介质层9。另外，在形成上电介质层11之前，可使用含氧的气体来热处理中间电介质层9。例如，可在100℃到500℃的低温下使用臭氧气体、氧等离子体或N2O等离子体来热处理中间电介质层9。热处理工艺增强了中间电介质层9的漏电流特性。
参考图2，图案化上电极层13、混合电介质层12和下电极层5以形成按顺序堆迭的下电极层5a、下电介质层图案7a、中间电介质层图案9a、上电介质层图案11a和上电极13a。下电介质层图案7a、中间电介质层图案9a和上电介质层图案11a构成混合电介质层图案12a。
同时，当下电极层5由例如铜层的金属层形成时，使用传统的光刻和蚀刻工艺很难图案化铜层。在这种情况下，可使用如图3和4中示出的镶嵌工艺来形成下电极5a。
参考图3和4，在集成电路衬底21上形成层间绝缘层23。层间绝缘层23的预定区域被部分蚀刻以形成沟槽区域。在具有沟槽区域的衬底上形成填充沟槽区域的下电极层，例如铜层。可在形成铜层之前形成扩散阻挡层。扩散阻挡层可由金属氮化层形成，例如TiN层或TaN层。然后使用化学机械抛光(CMP)技术平整化下电极层和扩散阻挡层以暴露层间绝缘层23的上表面。结果，形成了覆盖沟槽区域内壁的扩散阻挡层图案25和被扩散阻挡层图案25围绕的下电极27(即，铜电极)。扩散阻挡层图案25防止铜电极27中的铜原子被扩散进入层间绝缘层23。
随后，使用参照图1和2所述的相同方法，在铜电极27上形成混合电介质层图案12a和上电极13a。
<实例>
在下文中，将描述依照上述实施例和传统技术制造的混合电介质层的电学特性。
图5是依照本发明的实施例和依照传统方法制造的电容器的漏电流特性的比较图。在图5中，横坐标表示施加在电容器的上电极上的电压VA，并且纵坐标表示流经电介质层的漏电流密度IL。在125℃的温度下测量漏电流密度IL。
使用在下面的表1中描述的关键工艺条件来制造电容器，该电容器呈现图5的测量结果。
表1
         工艺参数 传统技术1 传统技术2 本发明
          下电极 TiN层(PVD)
电介质层   下电介质层 TaO层(600，MOCVD) HfO层(420，ALD) HfO层(50，ALD)
  中间电介质层 TaO层(480，MOCVD)
  上电介质层 HfO层(50，ALD)
          上电极 TiN层(PVD)
如从表1中可看出，形成的所有电介质层，无论是依照传统方法还是依照本发明，都形成具有大约84的相同的氧化物厚度。
参考表1和图5，当-8V或+8V的电压VA施加在使用单一氧化钽层作为电介质层的传统电容器上时，传统电容器呈现出大约1×10-3安培/cm2到1×10-1安培/cm2的漏电流密度IL。相反，使用单一氧化铪层作为电介质层的另一传统电容器在-8V或+8V的电压下呈现出大约1×10-7安培/cm2的低漏电流密度IL。另外，使用具有依照本发明的氧化铪层、氧化钽层和二氧化铪层堆迭结构的混合电介质层的电容器也呈现出在-8V或+8V的电压VA下大约1×10-7安培/cm2的低漏电流密度IL。结果，单一氧化铪层或包含单一氧化铪层的混合电介质层相比于单一氧化钽层呈现出明显的低漏电流密度IL。
图6是比较依照本发明的实施例制造的电容器和依照传统方法制造的电容器其电容随电压(CV)变化的曲线图。换句话说，图6是示出随电压变化的电容变化特性的曲线图。通过对电容器施加频率为100KHz的信号测量该电容。在图6中，横坐标表示施加在电容器的上电极上的电压VA，并且纵坐标表示电容器的归一化电容量(CN)。
使用如表1所述的相同的工艺条件来制造呈现图6的测量结果的电容器。
参考图6，当对单一氧化铪层施加的电压VA从0V增加到+8V时，归一化电容量CN增加了大约0.0075。相反，当对单一氧化钽层施加的电压VA从0V增加到+8V时，归一化电容量CN增加了大约0.0015。另外，当对具有氧化铪层、氧化钽层和氧化铪层的堆迭结构的混合电介质层施加的电压从0V增加到+8V时，归一化电容量(CN)增加了大约0.0025。结果，氧化钽层或包含氧化钽层的混合电介质层相比单一氧化铪层呈现出相对低的依赖于电压的电容变化。
总之，如可以从图5和6看到的，具有氧化铪层、氧化钽层和氧化铪层堆迭结构的混合电介质层不仅呈现出低漏电流而且呈现出低的依赖于电压的电容变化。
依照如上面所述的本发明，给出了具有相对低的依赖于电压的电容变化的中间电介质层和具有相对低漏电流的上和下电介质层的混合电介质层。因此，不管对使用混合电介质层的电容器施加的电压的变化，可实现呈现低漏电流和不变的电容量的高性能电容器。
虽然依照优选实施例详细地示出和描述了本发明，但本领域的专业技术人员应该清楚，可以在不脱离如附随的权利要求所定义的精神和范围的前提下，在此进行形式上和细节上的各种改动。
本申请要求2004年7月6日申请的韩国专利申请No.2004-52414的优先权，其整个内容在此合并作为参考。

Claims (26)

1、一种具有混合电介质层的半导体集成电路器件，混合电介质层包括：
包含铪(Hf)或锆(Zr)的下电介质层；
在下电介质层上的中间电介质层，中间电介质层随着电压的变化而产生的电容变化比下电介质层的低；和
在中间电介质层上的上电介质层，上电介质层包含铪(Hf)或锆(Zr)。
2、如权利要求1所述的半导体集成电路器件，其中下电介质层是氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种。
3、如权利要求1所述的半导体集成电路器件，其中中间电介质层是选自由氧化钽层、氧化钛、BST(BaSrTiO3)层、STO(SrTiO3)层、PZT(PbZrTiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层。
4、如权利要求1所述的半导体集成电路器件，其中上电介质层是HfO层、ZrO层、HfZrO层和HfO层与ZrO层的叠层中的一种。
5、一种电容器，包括：
在集成电路衬底上的下电极；
在下电极上的下电介质层图案，下电极层包含铪(Hf)或锆(Zr)；
在下电介质层图案上的中间电介质层图案，中间电介质层随着电压的变化而产生的电容变化比下电介质层图案的低；
在中间电介质层图案上的上电介质层图案，上电介质层包含铪(Hf)或锆(Zr)；以及
在上电介质层图案上的上电极。
6、如权利要求5所述的电容器，其中下电极和上电极是金属层。
7、如权利要求6所述的电容器，其中金属层是选自由钛(Ti)层、钽(Ta)层、氮化钛(TiN)、氮化钽(TaN)层、钨(W)层、氮化钨(WN)层、铝(Al)层、铜(Cu)层、钌(Ru)层、氧化钌(RuO)层、铂(Pt)层、铱(Ir)层、和氧化铱(IrO)层组成的组中的至少一层。
8、如权利要求5所述的电容器，其中下电介质层图案是氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种。
9、如权利要求5所述的电容器，其中中间电介质层图案是选自由氧化钽层、氧化钛、BST(BaSrTiO3)层、STO(SrTiO3)层、PZT(PbZrTiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层。
10、如权利要求5所述的电容器，其中上电介质层图案是氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种。
11、一种半导体集成电路器件的制造方法，包括：
在集成电路衬底上形成包含铪(Hf)或锆(Zr)的下电介质层；
在下电介质层上形成中间电介质层，中间电介质层由这样的材料层形成，该材料层随着电压的改变而产生的电容变化比下电介质层的低；以及
在中间电介质层上形成包含铪(Hf)或锆(Zr)的上电介质层。
12、如权利要求11所述的方法，其中下电介质层是由氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种形成。
13、如权利要求12所述的方法，其中使用原子层沉积(ALD)技术或化学气相沉积(CVD)技术来形成下电介质层。
14、如权利要求11所述的方法，其中中间电介质层由选自由氧化钽层、氧化钛、BST(BaSrTiO3)层、STO(SrTiO3)层、PZT(PbZrTiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层形成。
15、如权利要求14所述的方法，其中使用ALD技术或CVD技术来形成中间电介质层。
16、如权利要求11所述的方法，其中上电介质层由氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种形成。
17、如权利要求16所述的方法，其中使用ALD技术或CVD技术来形成上电介质层。
18、一种电容器的制造方法，包括：
在集成电路衬底上形成下电极层；
在下电极上形成下电介质层，下电介质层包含铪(Hf)和锆(Zr)中的任一种；
在下电介质层上形成中间电介质层，中间电介质层由由这样的材料层形成，该材料层随着电压的改变而产生的电容变化比下电介质层的低；
在中间电介质层上形成上电介质层，上电介质层包含Hf和Zr中的任一种；
在上电介质层上形成上电极；和
图案化上电极层、上电介质层、中间电介质层、下电介质层和下电极层，以形成按顺序堆迭的下电极、下电介质层图案、中间电介质层图案、上电介质层图案和上电极。
19、如权利要求18所述的方法，其中下电极和上电极由金属层形成。
20、如权利要求19所述的方法，其中金属层由选自由钛(Ti)层、钽(Ta)层、氮化钛(TiN)、氮化钽(TaN)层、钨(W)层、氮化钨(WN)层、铝(Al)层、铜(Cu)层、钌(Ru)层、氧化钌(RuO)层、铂(Pt)层、铱(Ir)层和氧化铱(IrO)层组成的组中的至少一层形成。
21、如权利要求18所述的方法，其中下电介质层由氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种形成。
22、如权利要求21所述的方法，其中使用原子层沉积(ALD)技术或化学气相沉积(CVD)技术来形成下电介质层。
23、如权利要求18所述的方法，其中中间电介质层由选自由氧化钽层、氧化钛、BST(BaSrTiO3)层、STO(SrTiO3)层、PZT(PbZrTiO3)层、TaON层、掺杂Nb的TaO层和掺杂Ti的TaO层组成的组中的至少一层形成。
24、如权利要求23所述的方法，其中使用ALD技术或CVD技术来形成中间电介质层。
25、如权利要求18所述的方法，其中上电介质层由氧化铪(HfO)层、氧化锆(ZrO)层、氧化铪锆(HfZrO)层和HfO层与ZrO层的叠层中的一种形成。
26、如权利要求25所述的方法，其中使用ALD技术或CVD技术来形成上电介质层。
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