CN1691291A - 制造半导体器件的方法 - Google Patents
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- 229920001296 polysiloxane Polymers 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
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- 238000010586 diagram Methods 0.000 description 8
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Abstract
本发明公开一种制造半导体器件的方法。该方法包括步骤:a)在其上形成有晶体管的硅衬底上相继沉积镍层及钴层;b)通过快速热处理,由沉积在该硅衬底上的该镍层及该钴层形成硅化物层;以及c)退火并湿蚀刻步骤b)中获得的半导体器件。因为形成镍/钴双层,减小了N多晶硅与P多晶硅之间的电阻差,并增强了形成硅化物后的后续热处理工艺期间的热稳定性。
Description
技术领域
本发明关于一种制造半导体器件的方法,具体而言,本发明关于一种制造半导体器件的方法,该方法形成镍/钴(Ni/Co)双层,而不是形成现有半导体器件中使用的钴/镍(Co/Ni)双层,藉此减小N多晶硅与P多晶硅之间的电阻差,并且确保热处理期间的增强的热稳定性。
背景技术
一般而言,硅化物工艺所表示的工艺为,当在硅衬底上沉积如钴、镍、钛及类似物等金属后,通过热处理与硅形成反应化合物。
由于近来半导体器件领域的深亚微米设计趋势,线宽被缩小,造成频繁的凝聚现象(cohesion phenomenon),其中硅化物线凝聚,然后在后续热处理工艺期间截断。
具体而言,在最近未来的纳米级半导体中,由于缩短栅长度所造成的短沟道效应,必须对该半导体应用浅结。在浅结中,需要提供硅化镍,在形成硅化物时,硅化镍所消耗的镍量少于硅化钴。
因此,现行0.13μm(微米)或以下的逻辑技术方面的持续趋势为,使用硅化镍来取代硅化钴,藉此增强短沟道效应。硅化镍的优点在于,硅化镍在小于0.10μm的精细线宽方面具有依据线宽的恒定薄片电阻、以及低的硅消耗率及低的比电阻,因此硅化镍的应用正扩展至纳米CMOS(complementaryMetal Oxide Semiconductor;互补金属氧化物半导体)。
然而,硅化镍对于形成硅化物之后的热处理工艺呈现非常弱的热特性。
即,因后续热处理工艺,硅化镍的晶粒会局部重新组合,从而形成较大的晶粒,这造成聚集现象,其中晶粒的均匀度恶化且线被截断。
因此,一种传统方法运用钴/镍双层来形成硅化物,藉此解决此问题。即,虽然现有的硅化镍会因后续热处理工艺而结合为由一硅化镍转化成的二硅化镍,但是当藉由添加钴来形成硅化物时,就可以抑制二硅化镍,并且即使形成二硅化镍,二硅化钴会起降低总电阻的作用。
然而,当先沉积钴再沉积镍时,硅化钴先于硅化镍形成,导致大量消耗硅,这尤其在多晶硅层的情况下发生,因而造成N多晶硅与P多晶硅间的电阻不同的问题。
图1是示出使用如上所述的传统钴/镍双层时多晶硅之间的大的电阻差的图示。
如图1所示,当使用传统钴/镍双层时,存在多晶硅之间的大电阻差的问题。
另外,图2是说明通过如上所述的传统钴/镍双层所形成的N有源层的不稳定的热特性的图示。
如图2所示,当使用传统钴/镍双层时,由于异常氧化而无法侦测该N有源层的薄片电阻,因而造成钴/镍结构中N有源层的热特性不稳定的问题。
发明内容
本发明的设计是为了解决前面提及的问题,并且本发明的目的是提供一种制造半导体器件的方法,该方法形成镍/钴(Ni/Co)双层,而不是形成现有半导体器件中使用的钴/镍双层,藉此减小N多晶硅与P多晶硅之间的电阻差,并确保热处理期间的增强的热稳定性。
根据本发明的一个方面,前述及其他目的可通过提供一种制造半导体器件的方法来实现,该方法包括步骤:a)在其上形成有晶体管的硅衬底上相继沉积镍层及钴层;b)通过快速热处理(RTP)由沉积在该硅衬底上的该镍层及该钴层来形成硅化物层;以及c)退火及湿蚀刻步骤b)所获得的该半导体器件。
可以在1mTorr真空压力及15cm衬底距离的条件下,在与硅衬底的温度相同的温度沉积镍至100埃的厚度。
可以在1mTorr真空压力及15cm衬底距离的条件下,在与硅衬底的温度相同的温度沉积钴至10埃的厚度。
可在500至700℃的温度执行RTP 30秒、60秒或90秒。
可在650或700℃的温度执行退火处理30分钟。
可使用比率为4∶1的H2SO4和H2O2的混合物来执行湿蚀刻工艺15分钟。
根据本发明的方法,提供的优异效果在于形成镍/钴双层,从而减小N多晶硅与P多晶硅之间的电阻差,减少浅结的硅消耗,并提高形成硅化物之后的后续热处理工艺过程中的热稳定性。
附图说明
由以下参考附图的详细说明,可更清楚地理解本发明的上述及其他目的及特征,其中:
图1是说明由传统钴/镍双层形成的多晶硅层之间的电阻差的图示;
图2是说明由传统钴/镍双层形成的N有源层的不稳定热特性的图示;
图3a到3c是断面图,示出根据本发明的制造半导体器件的步骤;
图4为一图示,说明使用根据本发明的镍/钴双层时,多晶硅层之间的电阻差;以及
图5为一图示,说明使用根据本发明的镍/钴双层时,N有源层的稳定的热特性。
附图标记说明
10硅衬底 15器件分隔膜
20栅氧化物膜 30多晶硅
40源极/漏极区 45间隔物
50镍层 55硅化物层
60钴层
具体实施方式
现在将参考附图来详细说明优选实施例。所提供的实施例是为了说明的目的,并且不应认为本发明范畴受限于实施例。
图3a到3c是显示根据本发明的制造半导体器件的步骤的断面图。
首先,如图3a所示,在形成有器件分隔膜15且定义有P阱的硅衬底10上,形成由栅氧化物膜20及多晶硅30所组成的栅极,接着在该栅极的两侧形成介电膜间隔物45。接着,在该栅极两侧的下部处的硅衬底10中注入杂质,形成源极/漏极区40以提供一晶体管。
接着,如图3b所示,在该晶体管上相继沉积镍层50及钴层60,使得该镍层50的厚度为100埃,该钴层60的厚度为10埃。
另外,优选地,在3E-7Torr基础压力(base pressure)、1mTorr真空压力、及沉积源(图中未描绘)与硅衬底之间15cm衬底距离的条件下,在与硅衬底的温度相同的温度沉积镍层50及钴层60。
接着,在550℃的温度以快速热处理(RTP)来热处理沉积在该衬底上的镍层50及钴层60持续60秒,形成硅化物层。
于是,如图3c所示,在有硅存在之处,通过镍层50及钴层60的选择性反应形成硅化物层55。
此处,优选地,在500至700℃的温度执行RTP热处理30秒、60秒或90秒。
接着,对该衬底上的该硅化物层55执行退火处理以评估热稳定性,然后执行湿蚀刻工艺以去除剩下的残余物。
此处,可在650或700℃的温度执行退火处理30分钟,并可用比率为4∶1的H2SO4和H2O2的混合物来执行湿蚀刻工艺15分钟。
图4为一图示,示出使用如上所述的本发明的镍/钴双层时,多晶硅层之间的薄片电阻差减小。
参考图4,与图1相比,当使用根据本发明的镍/钴双层时,N多晶硅与P多晶硅之间的薄片电阻显著降低,并且与热处理前的电阻相比,热处理后的电阻几乎不增加。
即,在本发明中,镍先于钴沉积,形成硅化钴之前形成硅化镍,从而硅消耗量相对降低。
另外,图5为一图示,表明当使用如上所述的本发明的镍/钴双层时,获得N有源层的稳定的热特性。
如图5所示,与传统钴/镍双层(其中如图2所示未侦测到N有源层的薄片电阻)比较,当使用根据本发明的镍/钴双层时,在热处理后侦测到N有源层的薄片电阻,从而提供了热稳定性。
即,通过在现有硅化镍上额外沉积Co层,利用硅化钴的特性,本发明使得低薄片电阻能得以维持,硅化钴的该特性是,当硅化钴在高温热处理后转化成二硅化物时,由于CoSi2(二硅化物)相的低薄片电阻而能达成热稳定性。
另外,关于镍/钴与硅的组合所造成的新相,形成三元相(Ni1-xCox)Si2,而不会形成具有高薄片电阻的NiSi2(二硅化物)相,从而维护低薄片电阻及热稳定性。
从前文的说明可得知,根据本发明,形成镍/钴双层,因而减小N多晶硅与P多晶硅之间的电阻差,减少浅结的硅消耗量,并且增强形成硅化物后的后续热处理工艺期间的热稳定性。
应明白,如上文所述的实施例及附图中已基于解说目的予以描述,并且本发明仅受限于随附的权利要求。另外,本领域技术人员应明白,还可进行各种修改、增加及代替方案,而不会脱离如随附的权利要求所提出的本发明范畴与精神。
Claims (6)
1.一种制造半导体器件的方法,包括步骤:
a)在其上形成有晶体管的硅衬底上相继沉积镍层及钴层;
b)通过快速热处理(RTP),由沉积在该硅衬底上的该镍层及该钴层形成硅化物层;以及
c)退火并湿蚀刻。
2.如权利要求1的方法,其中在1mTorr真空压力及15cm衬底距离的条件下,在与该硅衬底的温度相同的温度沉积镍至100埃的厚度。
3.如权利要求1的方法,其中在1mTorr真空压力及15cm衬底距离的条件下,在与该硅衬底的温度相同的温度沉积钴至10埃的厚度。
4.如权利要求1的方法,其中在500至700℃的温度进行该RTP热处理30秒、60秒或90秒。
5.如权利要求1的方法,其中在650或700℃的温度进行该退火处理30分钟。
6.如权利要求1的方法,其中使用比率为4∶1的H2SO4和H2O2的混合物来执行该湿蚀刻工艺15分钟。
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KR1020040024597A KR20050099326A (ko) | 2004-04-09 | 2004-04-09 | 반도체 소자의 제조 방법 |
KR24597/04 | 2004-04-09 |
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CN1691291A true CN1691291A (zh) | 2005-11-02 |
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CNA2005100641020A Pending CN1691291A (zh) | 2004-04-09 | 2005-04-11 | 制造半导体器件的方法 |
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US (1) | US20050227469A1 (zh) |
KR (1) | KR20050099326A (zh) |
CN (1) | CN1691291A (zh) |
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US6426291B1 (en) * | 2000-08-31 | 2002-07-30 | Micron Technology, Inc. | Method of co-deposition to form ultra-shallow junctions in MOS devices using electroless or electrodeposition |
US6528402B2 (en) * | 2001-02-23 | 2003-03-04 | Vanguard International Semiconductor Corporation | Dual salicidation process |
US6534871B2 (en) * | 2001-05-14 | 2003-03-18 | Sharp Laboratories Of America, Inc. | Device including an epitaxial nickel silicide on (100) Si or stable nickel silicide on amorphous Si and a method of fabricating the same |
JP2005504885A (ja) * | 2001-07-25 | 2005-02-17 | アプライド マテリアルズ インコーポレイテッド | 新規なスパッタ堆積方法を使用したバリア形成 |
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2004
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- 2004-11-17 US US10/990,922 patent/US20050227469A1/en not_active Abandoned
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US20050227469A1 (en) | 2005-10-13 |
KR20050099326A (ko) | 2005-10-13 |
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