CN1639581A - 具有测试电路的集成电路 - Google Patents
具有测试电路的集成电路 Download PDFInfo
- Publication number
- CN1639581A CN1639581A CNA038048787A CN03804878A CN1639581A CN 1639581 A CN1639581 A CN 1639581A CN A038048787 A CNA038048787 A CN A038048787A CN 03804878 A CN03804878 A CN 03804878A CN 1639581 A CN1639581 A CN 1639581A
- Authority
- CN
- China
- Prior art keywords
- circuit
- test
- test pattern
- logic
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10209078A DE10209078A1 (de) | 2002-03-01 | 2002-03-01 | Integrierter Schaltkreis mit Testschaltung |
DE10209078.5 | 2002-03-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1639581A true CN1639581A (zh) | 2005-07-13 |
CN100357754C CN100357754C (zh) | 2007-12-26 |
Family
ID=27762582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038048787A Expired - Fee Related CN100357754C (zh) | 2002-03-01 | 2003-02-26 | 具有测试电路的集成电路 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7139953B2 (zh) |
EP (1) | EP1483596B1 (zh) |
JP (1) | JP2005519286A (zh) |
CN (1) | CN100357754C (zh) |
AT (1) | ATE384957T1 (zh) |
AU (1) | AU2003206075A1 (zh) |
DE (2) | DE10209078A1 (zh) |
WO (1) | WO2003075028A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102207537A (zh) * | 2009-12-22 | 2011-10-05 | Nxp股份有限公司 | 测试电路和方法 |
CN101359033B (zh) * | 2007-07-03 | 2012-07-04 | 阿尔特拉公司 | 用于可编程逻辑器件的高速串行接口的信号丢失检测器 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7234092B2 (en) | 2002-06-11 | 2007-06-19 | On-Chip Technologies, Inc. | Variable clocked scan test circuitry and method |
TWI242121B (en) * | 2004-08-20 | 2005-10-21 | Via Tech Inc | Testing method for reconstructing unit |
WO2008096209A1 (en) * | 2007-02-09 | 2008-08-14 | Freescale Semiconductor, Inc. | Device and method for testing a circuit |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4503537A (en) * | 1982-11-08 | 1985-03-05 | International Business Machines Corporation | Parallel path self-testing system |
JPS6329276A (ja) * | 1986-07-23 | 1988-02-06 | Hitachi Ltd | 論理lsi |
US4974184A (en) * | 1988-05-05 | 1990-11-27 | Honeywell Inc. | Maximum length pseudo-random test pattern generator via feedback network modification |
CA1298668C (en) * | 1988-05-05 | 1992-04-07 | Lanae Avra | Maximum length pseudo-random test pattern generator via feedback network modification |
JP3308099B2 (ja) * | 1993-06-16 | 2002-07-29 | 花王株式会社 | キャップ |
KR100208043B1 (ko) * | 1996-01-12 | 1999-07-15 | 오우라 히로시 | 시험 패턴 발생기 |
KR100245795B1 (ko) * | 1997-06-30 | 2000-03-02 | 윤종용 | 테스트의 동작 오류 검사 방법 |
DE19917884C1 (de) * | 1999-04-20 | 2000-11-16 | Siemens Ag | Schaltung mit eingebautem Selbsttest |
DE10038327A1 (de) * | 2000-08-05 | 2002-02-14 | Philips Corp Intellectual Pty | Integrierter Schaltkreis mit Selbsttest-Schaltung |
-
2002
- 2002-03-01 DE DE10209078A patent/DE10209078A1/de not_active Withdrawn
-
2003
- 2003-02-26 AT AT03702959T patent/ATE384957T1/de not_active IP Right Cessation
- 2003-02-26 US US10/506,234 patent/US7139953B2/en not_active Expired - Fee Related
- 2003-02-26 AU AU2003206075A patent/AU2003206075A1/en not_active Abandoned
- 2003-02-26 JP JP2003573435A patent/JP2005519286A/ja not_active Ceased
- 2003-02-26 DE DE60318820T patent/DE60318820T2/de not_active Expired - Lifetime
- 2003-02-26 EP EP03702959A patent/EP1483596B1/en not_active Expired - Lifetime
- 2003-02-26 CN CNB038048787A patent/CN100357754C/zh not_active Expired - Fee Related
- 2003-02-26 WO PCT/IB2003/000760 patent/WO2003075028A1/en active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101359033B (zh) * | 2007-07-03 | 2012-07-04 | 阿尔特拉公司 | 用于可编程逻辑器件的高速串行接口的信号丢失检测器 |
CN102207537A (zh) * | 2009-12-22 | 2011-10-05 | Nxp股份有限公司 | 测试电路和方法 |
Also Published As
Publication number | Publication date |
---|---|
CN100357754C (zh) | 2007-12-26 |
DE10209078A1 (de) | 2003-09-18 |
AU2003206075A1 (en) | 2003-09-16 |
EP1483596A1 (en) | 2004-12-08 |
DE60318820D1 (de) | 2008-03-13 |
WO2003075028A1 (en) | 2003-09-12 |
JP2005519286A (ja) | 2005-06-30 |
EP1483596B1 (en) | 2008-01-23 |
US7139953B2 (en) | 2006-11-21 |
ATE384957T1 (de) | 2008-02-15 |
DE60318820T2 (de) | 2009-01-22 |
US20050160338A1 (en) | 2005-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6769084B2 (en) | Built-in self test circuit employing a linear feedback shift register | |
US6975978B1 (en) | Method and apparatus for fault simulation of semiconductor integrated circuit | |
CN101413990A (zh) | 一种现场可编程门阵列的测试方法及系统 | |
JPH10214175A (ja) | 線形帰還シフトレジスタ,多重入力記号レジスタ及びこれらを用いた内蔵自己診断回路 | |
US8671320B2 (en) | Integrated circuit comprising scan test circuitry with controllable number of capture pulses | |
CN101238382A (zh) | 测试包含秘密信息的集成电路的方法 | |
CN100380807C (zh) | 扫描路径电路和包括该扫描路径电路的半导体集成电路 | |
US6789221B2 (en) | Integrated circuit with self-test circuit | |
CN1639581A (zh) | 具有测试电路的集成电路 | |
US20100095173A1 (en) | Matrix system and method for debugging scan structure | |
Goessel et al. | A New Method for Concurrent Checking by Use of a 1-out-of-4 Code | |
US6681357B2 (en) | MISR simulation tool for memory BIST application | |
WO2005015249A2 (de) | Elektronisches element mit einem zu testenden elektronischen schaltkreis und testsystem-anordnung zum testen des elektronischen elements | |
EP1763677A2 (en) | Circuit arrangement and method of testing an application circuit provided in said circuit arrangement | |
JPH0991997A (ja) | メモリテスト回路 | |
US7039844B2 (en) | Integrated circuit with self-testing circuit | |
Polian et al. | Efficient bridging fault simulation of sequential circuits based on multi-valued logics | |
Makar et al. | Iddq test pattern generation for scan chain latches and flip-flops | |
KR100444763B1 (ko) | 내장된 자체테스트 기법을 위한 결정패턴 생성기 | |
Trivedi et al. | Implementation of Low-Power BIST Using Bit Swapping Complete Feedback Shift Register (BSCFSR) | |
US7080298B2 (en) | Circuit apparatus and method for testing integrated circuits using weighted pseudo-random test patterns | |
US20020199144A1 (en) | Scan path test method | |
Wingfield et al. | Function-based dynamic compaction and its impact on test set sizes | |
JPH063875B2 (ja) | 論理装置 | |
WO2000008479A1 (de) | Integrierte schaltung mit eingebautem baugruppentest |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: KALAI HANXILE CO., LTD. Free format text: FORMER OWNER: KONINKL PHILIPS ELECTRONICS NV Effective date: 20120210 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20120210 Address after: American Delaware Patentee after: NXP BV Address before: Holland Ian Deho Finn Patentee before: Koninkl Philips Electronics NV |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071226 Termination date: 20160226 |
|
CF01 | Termination of patent right due to non-payment of annual fee |