CN1632757A - Primary particle inversion resistant memory error correction and detection and automatic write back method for spacial computer - Google Patents

Abstract

This invention relates to a memory error-finding and writing back of the automatic space computer anti-reversing of single particle. In the whole error-finding process, the memory controller codes the thirty-two digit data written into the memory according to improved Hemming form and writes the correction codes and original data into the designed memory unit. In the data reading process, the memory controller corrects the data and correction codes. When finding the data digit error, it turns for microprocessor. When finding the more than two digit error, it turns for microprocessor trap software.

Description

Primary particle inversion resistant storer error correction and detection of space computer and automatic write back method

Technical field

The invention belongs to field of computer technology, relate to the design and the manufacturing of Memory Controller in a kind of SPARC V8 compatible type space computer microprocessor, primary particle inversion resistant storer error correction and detection of particularly a kind of space computer and automatic write back method.

Background technology

Space computer raying influence may cause semiconductor circuit wrong logic state to occur, even cause the semiconductor material permanent damage.Especially the various high energy particles in the space (comprising high energy proton, neutron, α particle etc.) can cause memory contents to be suddenlyd change between ' 0 ', ' 1 ', influence the function of semiconductor devices, are referred to as single-particle inversion (SEU) usually.For space computer, the most dangerous SEU occurs in central processing unit and the storer.SPARC V8 compatible type space computer microprocessor is supported 8,16 and 32 three kinds of forms, and the mistake that is caused by SEU may be unit mistake, dibit mistake or multidigit mistake.Need take aggregate measures in order to solve space computer radioresistance problem, comprise integral protection, design redundancy etc., then adopt methods such as backup, coding to utilize information redundancy reply SEU phenomenon usually concrete storer.

The backup method that is adopted for solution SEU problem mainly contained triplication redundancy (TMR) method in the past, comprised modularity redundancy (Module redundancy), device level redundancy (Device redundancy) and three kinds of forms of gate leve redundancy (Gate-level redundancy).This method has control characteristics simple, that easily realize, but also exists following shortcoming:

(1) the redundant huge increase that directly brings circuit scale, thus the expense of system design increased, also increased probability of errors.

(2) for supporting the redundant special voting circuit control data output of design that needs, increased design complexity.

(3) the TMR method all needs refresh memory unit again each the discovery after the mistake, has wasted a large amount of system times.

(4) because the TMR method adopts the value of two unanimities in three values as true value, so when the SEU phenomenon is serious, may leads to errors and can't find.

Coding is in the widely used error detection/correction method of field of data storage.The ultimate principle of error control coding is will be through storing after the supervision of the information code element sequence affix after the information source coding (redundancy) code element, and these supervise code elements and information code element exist certain definite interrelated.Read and to judge in storage/reading of data process whether make mistakes with consistent during whether with coding by related between supervise code element relatively and the information code element.After finding wrong code element, also can it be corrected according to encryption algorithm.Error correction and detection sign indicating number commonly used has parity check code, Hamming code, R-S sign indicating number etc.Expansion Hamming code in the Hamming code and best strange weighted code can both detect two dislocations, and can the unit's of correction mistake, are called for short and entangle two yards (SEC-DED) of an inspection.In the storer of microprocessor, adopt the method for Error Correction of Coding to realize wrong automatic detection and correction, can under the situation that does not increase extra radiation hardening processing, realize the obvious lifting of computer system security.At present, main implementation be in the processor outside to the data back write store of encoding, when sense data, carry out the EDC error detection and correction of data according to encryption algorithm.When detecting mistake, produce trap, by trap process software correction data, and with data write store again.The major defect of this method is as follows:

(1) no matter be that data or check code make a mistake, all need updated stored device content, it is more to take cpu resource, reduces the processor operating rate.

(2) by trap process software correction of data mistake, system design difficulty and time overhead have been increased greatly.

Utilize existing backup and coding method can solve the SEU problem of storer substantially, but can't satisfy space computer at all for performance requirements such as the operating rate of microprocessor, chip areas.For this reason, need the error correction coding of accumulator system level be incorporated into memory chip inside, improve the anti-single particle overturn ability of storer at processor structure.

Summary of the invention

At the shortcomings and deficiencies that above-mentioned prior art exists, the object of the present invention is to provide a kind of SPARC of being applicable to V8 compatible type space computer microprocessor, at memory chip inner that realize, effectively primary particle inversion resistant storer error correction and detection of space computer and automatic write back method at a high speed.

Realize that foregoing invention purpose technical scheme is such: primary particle inversion resistant storer error correction and detection of space computer and automatic write back method, it is characterized in that, in whole error correction and detection process, under the situation of non-processor direct intervention, by the entangle inspection two of the Memory Controller support in the microprocessor for 32 bit data, when a dislocation takes place when, realize the automatic correction and direct write-back of data by memorizer control circuit, specifically comprise the following steps:

1) error correction and detection and the automatic memorizer control circuit of write-back are set between internal bus and external bus, this circuit comprises error correction and detection circuit, state transitions control circuit, 2 data registers, multiplexer circuit, coding circuit; The error correction circuit module is communicated with external bus, state transitions control circuit and a data register respectively, by this data register data are passed to internal bus, the state transitions control circuit links to each other with multiplexer circuit, and write signal, enable signal and chip selection signal delivered to external bus respectively, multiplexer circuit also connects with another data register that is connected with internal bus, and the data of output are sent external bus back to by coding circuit;

2) in microprocessor, 32 bit data of wanting write store are encoded according to the Hamming code form by Memory Controller, generate 8 bit check sign indicating numbers, and check code is together write in the memory cell of appointment together with raw data, finish the write operation of data;

3) in the data readout, by Memory Controller data and check code are carried out verification, finish error correction and detection coding, verification and automatic write-back.

Data and check code carry out verification and follow these steps to carry out:

1. when finding that data bit unit staggers the time, earlier the error bit negate is corrected, directly be written back to storage unit then, and give microprocessor and handle;

2. when finding that check bit unit staggers the time, need not correct, regenerate check bit by raw data, the write store unit is sent to microprocessor with data simultaneously then;

3. when finding that error bit surpasses two, can't determine the position of makeing mistakes, to handle by the corresponding trap software that produces in the microprocessor so produce multidigit mistake trap by current error correction and detection coding method.

Primary particle inversion resistant storer error correction and detection of this space computer and automatic write back method are realized by the Memory Controller in the SPARC V8 compatible type microprocessor, support the inspection two of entangling for 32 bit data; When a dislocation takes place, can realize the automatic correction and the direct write-back of data by memorizer control circuit.

Primary particle inversion resistant storer error correction and detection of space computer of the present invention and automatic write back method have the following advantages:

(1) the Hamming code error correction and detection coding techniques that this method adopted can be checked out unit and multi-bit error, and the position of accurately definite unit mistake, adopt the method for direct write-back to realize proofreading and correct for the data sheet dislocation, reduce the accumulation of single bit error in system, thereby improved the treatment effeciency of unit mistake greatly.

(2) this method is divided into data bit unit's mistake, check bit unit's mistake with mistake and the wrong three kinds of situations of multidigit are handled respectively, by the direct unit's of the processing mistake of Memory Controller, thereby reduced the time overhead that processor produces because of repair data, and effectively reduced the complexity of Design of System Software.

(3) this method adopts the mode of monitoring bus to come the refresh memory content, after Memory Controller is finished the automatic write-back of data, again data is sent to bus, realizes the read operation of data, thereby makes that total line traffic control is simple, realizes easily.

(4) this method at the compatible SPARC V8 of microprocessor architecture, the AMBA bus on chip standard application that is wherein adopted is extensive, make this method have extremely strong versatility, adopt the memory controller circuit module of this method design also can in multiple processor, carry out directly multiplexing.

(5) this method designs at a kind of space computer microprocessor, realization is to the correction of unit mistake, and can detect 2 to 8 dislocations, satisfied the requirement of space computer, and promoted this performance of processors greatly aspect execution speed and the chip area two for the anti-single particle ability.

Description of drawings

Fig. 1 is error correction and detection and automatic write-back algorithm flow chart;

Fig. 2 is the read-write operation state transition diagram of realizing in the Memory Controller of the present invention in microprocessor; Jump condition 1 among the figure is sent the read operation request for CPU, and jump condition is for correctly finishing read operation/occur unit read error; Write-back when jump condition 3 misreads for CPU sends write operation requests/unit; Jump condition 4 is for correctly finishing the wrong write-back of the write operation/unit of finishing; Jump condition 5 the multidigit mistake occurs for read operation; Jump condition 6 is the read-write operation error in address; Jump condition 7 is returned after finishing for fault processing.

Fig. 3 is the oscillogram of normally reading data manipulation;

Fig. 4 is the oscillogram that sense data generation unit staggers the time.

Fig. 5 is a kind of circuit diagram of realizing error correction and detection and automatic write back method.

Embodiment

For a more clear understanding of the present invention, the present invention is described in further detail below in conjunction with accompanying drawing.

In the Memory Controller of SPARC V8 compatible type microprocessor, adopt Hamming code to carry out error correction and detection coding, verification and automatic write-back.This microprocessor is supported 32 bit data forms, to detect and from one 2 of normal moveout correction ^R-1〉=k+r mistake, and can find two dislocations, just require the figure place r of check bit and the figure place k of data bit to satisfy relation, so r is at least 7,8 bit check positions are set in this algorithm.Referring to Fig. 1 its algorithm is described.

The generator matrix of supposing Hamming code is A, and data are D, check code C, wherein

$A=\left(\begin{array}{cccccccccccccccccccccccccccccccc}0& 0& 0& 0& 1& 1& 1& 1& 0& 1& 1& 0& 0& 0& 1& 1& 0& 1& 0& 1& 1& 0& 0& 0& 1& 1& 0& 0& 0& 1& 1& 1\\ 1& 1& 1& 1& 1& 0& 0& 0& 1& 1& 0& 0& 1& 1& 1& 1& 1& 0& 0& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 0\\ 1& 0& 0& 0& 0& 1& 1& 0& 1& 0& 1& 1& 0& 1& 0& 0& 0& 1& 1& 0& 1& 1& 1& 1& 0& 1& 1& 0& 0& 0& 0& 1\\ 0& 1& 1& 0& 1& 1& 1& 1& 0& 0& 1& 0& 1& 0& 1& 0& 0& 0& 0& 1& 0& 1& 1& 0& 0& 0& 0& 1& 1& 1& 0& 1\\ 1& 1& 0& 0& 1& 0& 0& 0& 1& 1& 0& 0& 1& 0& 0& 0& 1& 1& 1& 1& 0& 1& 1& 1& 1& 0& 0& 1& 0& 0& 0& 1\\ 1& 0& 0& 0& 0& 1& 0& 0& 0& 1& 0& 0& 1& 1& 0& 1& 1& 1& 0& 0& 0& 1& 0& 1& 0& 1& 1& 1& 1& 1& 1& 0\\ 0& 1& 0& 1& 0& 0& 1& 1& 0& 0& 0& 1& 0& 0& 1& 1& 1& 0& 1& 1& 0& 0& 1& 1& 1& 1& 0& 1& 1& 0& 0& 0\\ 1& 1& 1& 1& 0& 0& 0& 1& 0& 0& 1& 1& 1& 0& 0& 0& 1& 0& 0& 0& 1& 1& 1& 1& 0& 0& 1& 1& 0& 0& 1& 0\end{array}\right)$

Obtain data D from bus and send into register Ri.Generate formula C=AD according to check code, generate check code C, data D and check code C together among the write store unit L, are finished data write operation by the data D in the register.Error correction and detection in the data read operation is with the write-back algorithm is as follows automatically:

1. sense data D ' and check code C ' from memory cell L generate check bit C according to formula C=AD by D ' ", by check code C ' and check bit C " XOR generation S (s=S ₀∪ S ₁∪ S ₂, S wherein ₀Represent error-free situation, S ₁The wrong situation of representation unit, S ₂The wrong situation of expression multidigit).

2. if

Error in data then occurs, go to 3.; If s ∈ s ₀, then the no datat mistake writes data D ' among the register Ro, goes to 6.;

3. if s ∈ s ₁, be the unit mistake then, go to 4.; If s ∈ s ₂, be the multidigit mistake then, go to 7.;

4. determine the position of unit mistake according to S, if the data bit mistake is sent among register Ri and the Ro after the value negate correction of the data bit that will make mistakes; If the check bit mistake is write direct data D ' among register Ri and the Ro;

5. with among data among the register Ri and the generation check code write store unit L, finish the write-back of data;

6. the data among the register Ro are outputed to bus, finish the data read operation, finish;

7. produce the wrong trap of multidigit, handle, finish by system.

The error correction and detection of support unit's data in the Memory Controller of SPARC V8 compatible type microprocessor, and can check out 2 to 8 error in data, produce corresponding software processes trap.The state of a control of the read-write operation of being realized in the Memory Controller comprises idle condition (IDLE), read states (READ), writes state (WRITE) and error condition (ERROR) as shown in Figure 2.Enter the IDLE state after the system reset, and keep this state, data transfer request is arranged up to this microprocessor.When this microprocessor requires to write data manipulation, enter the WRITE state; When requiring the sense data operation, enter the READ state.Correctly finish writing/sense data operation after, directly enter the IDLE state; Otherwise enter the ERROR state, carry out entering the IDLE state after corresponding error is handled.The process of state transitions can be divided into following several situation:

1. microprocessor is when storer writes data, and the state transitions process is IDLE → WRITE → IDLE;

2. during correct sense data, the state transitions process is IDLE → READ → IDLE to microprocessor from storer, and as can be seen from Fig. 3, data directly have been sent to the LSFT32 microprocessor by bus;

When 3. mistake appearred in the address realm of microprocessor read/write operation, the state transitions process was IDLE → ERROR → IDLE;

4. when appearring in sense data, unit staggers the time, the state transitions process is IDLE → READ → IDLE → WRITE → IDLE, as can be seen from Fig. 4, be written to the same address location of storer after the error bit in the data is corrected by negate again, be sent in the microprocessor by bus then;

5. stagger the time when multidigit appears in sense data, the state transitions process is IDLE → READ → ERROR → IDLE.

Fig. 5 is a kind of circuit diagram of realizing error correction and detection and automatic write back method, and it comprises error correction and detection circuit, state transitions control circuit, 2 data registers, multiplexer circuit, coding circuit; The error correction circuit module is communicated with external bus, state transitions control circuit and data register 1 respectively, the state transitions control circuit links to each other with multiplexer circuit, and write signal, enable signal and chip selection signal delivered to external bus respectively, multiplexer circuit also is connected with data register 2, and the data of output are sent external bus back to by coding circuit.

The course of work of this circuit is, error correction circuit is converted to 32 bit data with 40 bit data of external bus, be transferred to the state transitions control circuit and give a register holds, this register is delivered to data internal bus and multiplexer circuit simultaneously, multiplexer circuit receives 32 bit data of being sent here by register 2 by internal bus and the data of being sent here by the state transitions control circuit simultaneously, is converted to 40 bit data by the output of multiplexer circuit by coding circuit then and sends external bus back to.Wherein, as shown in Figure 2, comprise idle condition (IDLE), read states (READ), write state (WRITE) and error condition (ERROR) by the state of a control of read-write operation in the state transitions control circuit control store controller.

Claims (2)

1. primary particle inversion resistant storer error correction and detection of space computer and automatic write back method, it is characterized in that, in whole error correction and detection process, under the situation of non-processor direct intervention, by the entangle inspection two of the Memory Controller support in the microprocessor for 32 bit data, when a dislocation takes place when, realize the automatic correction and direct write-back of data by memorizer control circuit, specifically comprise the following steps:

1) error correction and detection and the automatic memorizer control circuit of write-back are set between internal bus and external bus, this circuit comprises error correction and detection circuit, state transitions control circuit, 2 data registers, multiplexer circuit, coding circuit; The error correction circuit module is communicated with external bus, state transitions control circuit and a data register respectively, by this data register data are passed to internal bus, the state transitions control circuit links to each other with multiplexer circuit, and write signal, enable signal and chip selection signal delivered to external bus respectively, multiplexer circuit also connects with another data register that is connected with internal bus, and the data of output are sent external bus back to by coding circuit;

2) in microprocessor, 32 bit data of wanting write store are encoded according to the Hamming code form by Memory Controller, generate 8 bit check sign indicating numbers, and check code is together write in the memory cell of appointment together with raw data, finish the write operation of data;

3) in the data readout, by Memory Controller data and check code are carried out verification, finish error correction and detection coding, verification and automatic write-back.

2. the method for claim 1 is characterized in that, data and check code is carried out verification follow these steps to carry out:

1),, finishes the data read operation with data output if when not having mistake;

2), then carry out error correction and detection coding, verification and automatic write-back by following different situations if mistake occurs;

1. when finding that data bit unit staggers the time, earlier the error bit negate is corrected, directly be written back to storage unit then, and give microprocessor and handle;

2. when finding that check bit unit staggers the time, need not correct, regenerate check bit by raw data, the write store unit is sent to microprocessor with data simultaneously then;

3. when finding that error bit surpasses two, can't determine the position of makeing mistakes, to handle by the corresponding trap software that produces in the microprocessor so produce multidigit mistake trap by current error correction and detection coding method.

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