CN105022675B - The correcting device and method of 4 Data flipping mistakes of embedded microprocessor cache - Google Patents
The correcting device and method of 4 Data flipping mistakes of embedded microprocessor cache Download PDFInfo
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Abstract
A kind of correcting device of 4 Data flipping mistakes of embedded microprocessor cache, it is characterised in that：Including tag encoder, mark memory, mark decoder, data encoder, data storage, data decoder, hit comparator and data selector, according to selected Cache management strategies, most 4 error in data in Cache mark memories and data storage are corrected using binary system Bose-Chaudhuri-Hocquenghem Code.
Description
Technical field
The present invention relates to a kind of correcting device of microprocessor cache error in data, more particularly to a kind of insertion to decline
The correcting device of processor cache long numeric data upset mistake.It is slow at a high speed the invention further relates to a kind of embedded microprocessor
Deposit the correcting method of long numeric data upset mistake.
Background technology
Single-particle inversion (SEU) is under space application environment, because single-particle incidence causes to store list in integrated circuit
Member occur Data flipping mistake event, be under space environment electronic system break down with the major incentive of operation irregularity it
One.Conventional SEU is mainly shown as the unit data upset failure of single memory cell, but uses nanometer technology in integrated circuit
Afterwards, with the reduction of feature sizes of semiconductor devices, the rising of working frequency and the reduction of node operating voltage, in cache
Etc. (Cache) in regular memory unit, SEU triggers the probability of Multiple-bit upsets (MBU) to greatly improve, can cause most 8 with
Machine Data flipping mistake, bigger harm is produced to the electronic system of space application.
As an important component in Modern microprocessor, Cache completes the buffering of program code and data, to
Processor cores (such as streamline) provide instruction code and data.If error in data occurs for the memory cell in Cache, will
The instruction that microprocessor performs mistake is directly resulted in, or computing is carried out to the data of mistake, and then produces the implementing result of mistake.
Therefore, for the highly reliable microprocessor of space application, the error in data for carrying out Cache systems is corrected with important automatically
Meaning.
Existing general purpose microprocessor (such as alpha21264, Itanium, Powerpc-a10) mainly uses odd even school
Test the error protection that Cache is realized with ECC (Error Correcting Codes, error correcting code) check code, its limitation
Property be can only correct single-bit error and detection double-bit errors.The MS-ECC that Chishti et al. is proposed based on cache lines granularity
Scheme, area and performance cost are very big.The two-dimentional check code that Kim et al. is proposed can correct multi-bit error, but it for point
Scattered random error is less efficient.Intel proposed VS-ECC schemes in 2011, and error correction energy is used for different Cache blocks
The different algorithm of power, area and performance cost that algorithm is brought are reduced, but still had in terms of fault-tolerant ability to be hoisted.Based on point
The data heavy duty strategy of group even-odd check is currently used for a variety of space microprocessors, for the error in data progress to Cache
It is fault-tolerant, but this method can only solve the problems, such as 1 bit-errors in group, can not tackle the multidigit random error of single-particle induction.In a word,
Existing technical scheme lacks effective fault-tolerant networks for the 2-4 positions random error that MBU triggers.
Using Cache data error detections, force Cache to be not hit by error, data mistake is corrected by resetting Cache
Miss, and a kind of fault-tolerance approach of effective Cache Data flippings failure.But this method can reduce Cache life
Middle rate, in the system using the DRAM class memories being widely used at present, Cache failure expenses are general all bigger, meanwhile,
Under nanometer technology, SEU causes the probability of error in data to greatly improve, therefore, this to be dropped based on Cache refittings fault-tolerance approach
The execution efficiency of low processor.
The content of the invention
It is an object of the invention to design in a kind of cache of embedded microprocessor anti-single particle upset effect most
The correcting device and method of more 4 Data flipping failures, most 4 random data upset mistakes caused by SEU can be carried out
Automatically correct.
A kind of 4 Data flipping error correcting devices of embedded microprocessor cache, it is characterised in that：Including mark
Encoder, mark memory, mark decoder, data encoder, data storage, data decoder, hit comparator sum
According to selector；The tag encoder is when carrying out Cache write operations, to the Cache address marks and row effective marker of write-in
Binary system Bose-Chaudhuri-Hocquenghem Code is carried out, check code is generated, mark memory is stored in together with address mark；The mark memory is used for
According to Cache management strategies, point 1 tunnel, 2 tunnels or 4 tunnels storage marker word and its BCH check codes, the marker word include address
Mark and row effective marker two parts；The mark decoder is when carrying out Cache access, to the mark of mark memory output
Word and check code carry out BCH verifications, and 1 to 4 random error in marker word is corrected, and will verify correct or correct wrong
Lose one's life middle comparator of marker word after by mistake carries out Cache hits and judged；The data encoder when carrying out Cache write operations,
Binary system Bose-Chaudhuri-Hocquenghem Code is carried out to input data, check code is generated, data storage is stored in together with input data；The data
Memory is used for according to Cache management strategies, point 1 tunnel, 2 tunnels or 4 tunnels storage Cache data words and its BCH check codes；It is described
For data decoder when carrying out Cache read operations, data word and check code to data storage output carry out BCH verifications, right
1 to 4 random error in data word is corrected, and send the data word verified correctly or after correction mistake to data selector
Export to processor cores；The comparator that hits is by the mark part in the storage address of input and each mark decoder
The marker word of output is compared, and judges whether Cache hits, and exports hit in tag, and control data selector selection data are defeated
Go out；The hit selection signal that the data selector is sent according to hit comparator, is selected from the output of multiple data decoders
Real hiting data is selected to export to processor cores.
A kind of 4 Data flipping error correction methods of embedded microprocessor cache, it is characterised in that：The data are turned over
Turn error correction method and be used for 4 Data flipping error correcting devices of embedded microprocessor cache, the Data flipping
Error correcting device includes tag encoder, mark memory, mark decoder, data encoder, data storage, data and translated
Code device, hit comparator and data selector；The Data flipping error correction method is using following steps with method to Cache
In most 4 error in data detected and corrected：
(1) during initial reset, all marks in mark memory are write into full 0, it is invalid that all row effective markers are set to,
The check code of all marker words is disposed as effective BCH check codes；
(2) when processor enters line storage and reads or writes access, storage address is divided into address mark, Cache indexes
With address three parts in row, according to Cache indexes from mark memory, point 1 tunnel, 2 tunnels or 4 tunnels read Cache marks, row has
Valid flag and check code, send each mark decoder to carry out BCH decodings, mark BCH generator polynomial of the decoder according to selection,
BCH fast decodings are carried out using parallel algorithm, if without error in data, Cache marks and row effective marker is exported immediately, turns
Step (3)；If there is 1 to 4 error in data, after mark decoder is corrected to it, exporting correct Cache marks and row has
Valid flag, go to step (3)；
(3) each Cache for reading step (2) is marked in comparator is hit, with the address label in storage address
Note part is compared, if some Cache marks are equal with address mark, and row effective marker corresponding to address is in row
During effective status, Cache hits, the effective hit indication signal of hit comparator output and hit selection signal are represented, turns step
Suddenly (4)；Otherwise, Cache is not hit by, and hit comparator will hit instruction output signal and hit selection signal is set to invalid shape
State, go to step (4)；
(4) when processor access type is memory write access, go to step (5), processor access type is read for memory
During access, go to step (6)；
(5) when memory write operation starts, input data that data encoder sends processor, according to the BCH of selection
Generator polynomial, BCH check codes corresponding to generation, and data are sent into each road input of data storage together, if Cache is ordered
In, input data and check code are write in data storage together, writing position by hit selection signal, Cache indexes and
Address determines jointly in row, then terminates the operation to Cache；If be not hit by, directly terminate the operation to Cache；
(6) after storage address is effective, immediately the Cache indexes in storage address and row in address, from data
In memory, point 1 tunnel, 2 tunnels or 4 tunnels read data word and check code, send each data decoder to carry out BCH decodings, and data are translated
Code device carries out BCH fast decodings according to the BCH generator polynomials of selection using parallel algorithm, if without error in data, immediately
Output data word is to data selector；If there is 1 to 4 error in data, after data decoder is corrected to it, output is correct
Data word is to data selector；After comparator completion hit is hit relatively, if being not hit by going to step (7)；If hit, root
The data of the data word selection hit exported according to hit selection signal from each data decoder, are exported to processor cores, knot
Operation of the beam to Cache；
(7) when reading to be not hit by, the storage address sent according to processor cores, read from main storage with
The data word of the identical quantity of Cache row sizes, data word is sent successively data encoder generate BCH check codes, by data word and
Check code is write in data storage together, and writing position determines according to Cache replacement policies and Cache indexes；Then basis
Storage address produces corresponding address mark, send tag encoder to generate marker word together address mark and row effective marker
BCH check codes, the check code of address mark, row effective marker and generation is write into mark memory relevant position together, write
Enter position to be determined according to Cache replacement policies and Cache indexes, complete the renewal of Cache rows；Meanwhile plan is accessed according to Cache
Slightly, by data word corresponding to storage address through data decoder, data selector sending processor kernel, terminate to Cache's
Operation.
The correcting device and method of 4 Data flipping mistakes of embedded microprocessor cache that the present invention realizes,
Can be corrected in embedded microprocessor 1 to 4 that Cache mark memory and data storage trigger due to SEU it is random
Mistake, the reliability that microprocessor is applied under the adverse circumstances such as space can be improved.
Brief description of the drawings
When Fig. 1 is that cache uses direct image, according to the correcting device structure of 4 Data flipping mistakes of the present invention
Figure；
When Fig. 2 is that cache is connected using two-way group, according to 4 Data flipping error correcting device structures of the present invention
Figure；
When Fig. 3 is that cache is connected using four tunnel groups, according to 4 Data flipping error correcting device structures of the present invention
Figure.
Embodiment
The present embodiment combines a kind of specific embodiment party of embedded microprocessor of SPARC V8 architectures to the present invention
Formula illustrates.The embedded microprocessor of the SPARC V8 architectures, using 32 RISC Architectures, Instruction Cache sum
Direct image mode is used according to Cache, capacity is all 2K bytes, and Cache row sizes are 4 words, and word is wide 32.Do not consider to hold
During wrong measure, Cache mark memory capacity is 128 words, word width 25, wherein address mark 21, row significant notation 4
Position, represent whether each word is effective in row respectively.
When processor cores carry out memory access, after Cache is given in 32 bit memory addresses, address mark is divided into
Address (position 3-0, totally 4, low 2 useless) three in (position 31-11, totally 21), Cache indexes (position 10-4, totally 7) and row
Point, wherein address mark compares for Cache hits, and address is as mark memory and data storage in Cache indexes and row
The reference address of device.
Generally Cache mainly includes three parts：Cache controllers, Cache mark memories and Cache data
Memory, the part for being influenceed to cause error in data by SEU is mainly mark memory and data storage.Go out in mark memory
During existing error in data, Cache hit or miss effect by mistake can be caused, miss effect is only generally to influence Cache hit rates,
Cause the reduction of Cache access performances, the result of mistake will not be caused；Hit can then cause Cache by the data of mistake or refer to by mistake
Order is supplied to processor cores, so as to cause the implementing result of mistake.When occurring wrong in Cache data storages, Jiu Hui
The data or instruction code of mistake are provided during hit to processor cores, cause the implementing result of mistake.
For the needs of highly reliable application under the environment such as space, Bose-Chaudhuri-Hocquenghem Code mode can be used to Cache data storages
Protected with Cache mark memories.It is limited that BCH (Bose-Chaudhuri-Hocquenheim) codings are that one kind is defined on
Linear cyclic block code on domain GF (q), multiple mistakes in packet can be corrected.Binary BCH codes are a kind of
The BCH code being defined on finite field gf (2), it can detect and correct the error control code of the multidigit random error in packet,
Have the advantages that error correcting capability is strong, construction is convenient, it is simple to encode, in the communications field (such as digital broadcasting, 3G network, optic communication)
It is widely used.
The present embodiment uses binary BCH codes, to 32 data and Cache mark memories of Cache data storages
25 data carry out the automatic correction of most 4 bit-errors.Determine Bose-Chaudhuri-Hocquenghem Code code length n=63, select primitive polynomial p (x)=
x6+ x+1, check bit number n-k=24, maximum information bit length k=39, minimum distance dmin=9.And then determine that generation is multinomial
Formula is as follows：
G (x)=1+x+x2+x4+x5+x6+x8+x9+x10+x13+x16+x17+x19+x20+x22+x23+x24
The generator matrix G of [63,39] BCH code can be obtained39×63It is as follows：
Because the data bit width of Cache data storages and Cache mark memories is 32 and 25 respectively, to [63,
39] BCH code is shortened, the generator matrix G after being shortened32×56And G25×49.If m is 32 or 25 to be encoded
Data, code word C=mG are corresponding Bose-Chaudhuri-Hocquenghem Code, wherein verification bit width is 24.
It is not difficult to obtain the BCH check matrixes of Cache data storages and Cache mark memories according to generator matrix G
H24×56And H24×49, check code will be included from 56 or 49 of Cache data storages or the reading of Cache mark memories
Data are designated as R, calculate syndrome S=RHTIf S is full null vector, illustrate that R does not have mistake, otherwise illustrating R, there occurs 1 to 4
It bit-errors, can be solved to obtain error location polynomial by syndrome S, iteration or algebraic approach are used according to error location polynomial
The purpose of error correcting can be can reach by being negated to error bit in the hope of errors present.
Based on above-mentioned general principle with setting, 4 Data flipping mistakes of embedded microprocessor cache of the invention
A kind of embodiment of correcting device is as follows：
In the embedded microprocessor of SPARC V8 architectures, cache is arranged to 4 digits as shown in Figure 1
According to upset error correcting device, including tag encoder, mark memory, mark decoder, hit comparator, data encoding
Device, data storage, data decoder and data selector.
Tag encoder uses generator matrix G when carrying out Cache write operations25×49, to the address mark and row of write-in
Effective marker carries out binary system Bose-Chaudhuri-Hocquenghem Code, generates check code, mark memory is stored in together with address mark.
Due to using direct image algorithm, mark memory uses the memory of 128 word × 49, stored by sequence of addresses
Marker word (25) and its BCH check codes (24), wherein marker word include address mark (21) and row effective marker (4
Position) two parts.
Due to using direct image algorithm, 4 Data flipping error correcting devices set 1 mark decoder, carried out
When Cache is accessed, check matrix H is used24×49, marker word and check code to mark memory output carry out BCH verifications, right
1 to 4 random error in marker word is corrected, and will be verified correct or corrected the marker word after mistake and lose one's life middle comparator
Cache hits are carried out to judge.
Comparator is hit to carry out the mark part in the storage address of input and the marker word of mark decoder output
Compare, if equal, represent Cache hits, export hit in tag, control data selector selection data output；If not phase
Deng then Cache is not hit by.
Data encoder uses generator matrix G when carrying out Cache write operations32×56, binary system is carried out to input data
Bose-Chaudhuri-Hocquenghem Code, 24 bit check codes are generated, data storage is stored in together with input data.
Data storage uses the memory of 512 word × 56, for storing 32 Cache data words and its 24
BCH check codes.
Due to using direct image algorithm, 4 Data flipping error correcting devices set 1 data decoder, carried out
During Cache read operations, check matrix H is used24×56, BCH verifications are carried out to the data word and check code of data storage output,
1 to 4 random error in data word is corrected, and send data to select the data word verified correctly or after correction mistake
Device is exported to processor cores.
Hit the hit selection signal sent of comparator it is effective when, data that data selector exports data decoder
Give processor cores.
4 Data flipping error correcting devices of embedded microprocessor cache of the SPARC V8 architectures are adopted
The error in data in Cache is detected and corrected with method with following steps：
(1) during initial reset, by tag encoder, all Cache marks in mark memory are write into full 0, institute
There is row effective marker to be set to invalid, the BCH check codes of all marker words are disposed as effective BCH check codes.
(2) when processor enters line storage and reads or writes access, 32 bit memory addresses are divided into 21 bit address mark, 7
Address three parts in position Cache indexes and 4 rows, Cache marks are read from mark memory according to Cache indexes, row has
Valid flag and check code, send mark decoder to carry out BCH decodings, and mark decoder uses according to the BCH generator polynomials of selection
Parallel algorithm carries out BCH fast decodings, if without error in data, exports Cache marks and row effective marker immediately, goes to step
(3)；If there is 1 to 4 error in data, after mark decoder is corrected to it, exporting correct Cache marks and row has criterion
Will, go to step (3)；
(3) Cache for reading step (2) is marked in comparator is hit, with the address mark portion in storage address
Divide and be compared, if Cache marks are equal with address mark, and row effective marker corresponding to address is effective status in row
When, Cache hits, the effective hit indication signal of hit comparator output and hit selection signal are represented, is gone to step (4)；It is no
Then, Cache is not hit by, and hit comparator will hit instruction output signal and hit selection signal is set to disarmed state, go to step
(4)；
(4) when processor access type is memory write access, go to step (5), processor access type is read for memory
During access, go to step (6)；
(5) when memory write operation starts, input data that data encoder immediately sends processor, according to selection
BCH generator polynomials, BCH check codes corresponding to generation, and data are sent into each road input of data storage together, if
Cache is hit, and input data and check code is write in data storage together, writing position is by hit selection signal, Cache
Address determines jointly in index and row, then terminates the operation to Cache；If be not hit by, directly terminate the behaviour to Cache
Make；
(6) after storage address is effective, immediately the Cache indexes in storage address and row in address, from data
Data word and check code are read in memory, send data decoder to carry out BCH decodings, data decoder is given birth to according to the BCH of selection
Into multinomial, BCH fast decodings are carried out using parallel algorithm, if without error in data, output data word gives data choosing immediately
Select device；If there is 1 to 4 error in data, after data decoder is corrected to it, export correct data word and selected to data
Device；After hit compares completion hit relatively, if being not hit by going to step (7)；If hit, according to hit selection signal from number
According to the data of the data word selection hit of decoder output, export to processor cores, terminate the operation to Cache；
(7) when reading to be not hit by, the storage address sent according to processor cores, read from main storage with
The data word of the identical quantity of Cache row sizes, data word is sent successively data encoder generate BCH check codes, by data word and
Check code writes the position that Cache indexes indicate in data storage together；Then produced accordingly according to storage address
Location marks, and address mark and row effective marker is sent to the BCH check codes of tag encoder generation marker word together, by address label
Note, row effective marker and the check code of generation write Cache indexes defined location in mark memory together, complete Cache
Capable renewal；Meanwhile by data word corresponding to storage address through data decoder, data selector sending processor kernel, knot
Operation of the beam to Cache.
As a result of foregoing [63,39] BCH code generator polynomial, the present embodiment can to Cache data storages and
Any 1 to 4 random error in Cache mark memories is corrected.
The mapping rule of 4 Data flipping error correcting devices of embedded microprocessor cache can only select directly to reflect
Picture, two-way group is connected or four tunnel groups are connected.Using direct image Cache mapping rules when, embedded microprocessor is slow at a high speed
The structure for depositing 4 Data flipping error correcting devices is as shown in Figure 1；It is embedded during the Cache mapping rules being connected using two-way group
The structure of 4 Data flipping error correcting devices of microsever cache is as shown in Figure 2；It is connected using four tunnel groups
During Cache mapping rules, the structure of 4 Data flipping error correcting devices of embedded microprocessor cache is as shown in Figure 3.
4 Data flipping error correcting devices of embedded microprocessor cache and method that the present invention realizes, solve
The detection of 1 to 4 random data mistake corrects problem with automatic in embedded microprocessor cache, can improve insertion
The reliability and process performance that microsever works under space environment.
Without departing from the spirit of the scope of the invention, the present invention can have various deformation, such as：Cache volume changes, reflect
Selection as rule etc., can change in different implementation.These deformations are also contained in scope of the present invention
Within.
Claims (4)
- A kind of 1. 4 Data flipping error correcting devices of embedded microprocessor cache, it is characterised in that：Compiled including mark Code device, mark memory, mark decoder, data encoder, data storage, data decoder, hit comparator and data Selector；The tag encoder enters when carrying out Cache write operations to the Cache address marks and row effective marker of write-in Row binary system Bose-Chaudhuri-Hocquenghem Code, check code is generated, mark memory is stored in together with address mark；The mark memory is used for root According to Cache management strategies, point 1 tunnel, 2 tunnels or 4 tunnels storage marker word and its BCH check codes, the marker word include address label Note and row effective marker two parts；The mark decoder is when carrying out Cache access, to the marker word of mark memory output And check code carries out BCH verifications, and 1 to 4 random error in marker word is corrected, and correct or correction mistake will be verified Lose one's life middle comparator of marker word afterwards carries out Cache hits and judged；The data encoder is right when carrying out Cache write operations Input data carries out binary system Bose-Chaudhuri-Hocquenghem Code, generates check code, data storage is stored in together with input data；The data are deposited Reservoir is used for according to Cache management strategies, point 1 tunnel, 2 tunnels or 4 tunnels storage Cache data words and its BCH check codes；The number According to decoder when carrying out Cache read operations, BCH verifications, logarithm are carried out to the data word and check code of data storage output Corrected according to 1 to 4 random error in word, and send data selector defeated the data word verified correctly or after correction mistake Go out to processor cores；The hit comparator is defeated by the mark part in the storage address of input and each mark decoder The marker word gone out is compared, and judges whether Cache hits, and exports hit in tag, control data selector selection data output； The hit selection signal that the data selector is sent according to hit comparator, selected from the output of multiple data decoders true Positive hiting data is exported to processor cores.
- 2. 4 Data flipping error correcting devices according to claim 1, it is characterised in that：The mark decoder Quantity is 1,2 or 4, and the output all the way to mark memory respectively is verified and error correction；The data decoder Quantity is 1,2 or 4, and the output all the way to data storage respectively is verified and error correction.
- 3. 4 Data flipping error correcting devices according to claim 2, it is characterised in that：The mark memory, number According to storage way and mark decoder, the quantity of data decoder of memory, determined by selected Cache mapping rulers, Selectable Cache mapping rulers are direct image, two-way group is connected or four tunnel groups are connected.
- A kind of 4. 4 Data flipping error correction methods of embedded microprocessor cache, it is characterised in that：The Data flipping Error correction method is used for 4 Data flipping error correcting devices of embedded microprocessor cache, and the Data flipping is wrong Correcting device includes tag encoder, mark memory, mark decoder, data encoder, data storage, data decoding by mistake Device, hit comparator and data selector；The Data flipping error correction method is using following steps with method in Cache Most 4 error in data detected and corrected：(1) during initial reset, all marks in mark memory are write into full 0, it is invalid that all row effective markers are set to, and owns The check code of marker word is disposed as effective BCH check codes；(2) when processor enters line storage and reads or writes access, storage address is divided into address mark, Cache indexes and row Interior address three parts, according to Cache indexes from mark memory, point 1 tunnel, 2 tunnels or 4 tunnels read Cache marks, row has criterion Will and check code, send each mark decoder to carry out BCH decodings, and mark decoder uses according to the BCH generator polynomials of selection Parallel algorithm carries out BCH fast decodings, if without error in data, exports Cache marks and row effective marker immediately, goes to step (3)；If there is 1 to 4 error in data, after mark decoder is corrected to it, exporting correct Cache marks and row has criterion Will, go to step (3)；(3) each Cache for reading step (2) is marked in comparator is hit, with the address mark portion in storage address Divide and be compared, if some Cache marks are equal with address mark, and row effective marker corresponding to address is effective in row During state, Cache hits, the effective hit indication signal of hit comparator output and hit selection signal are represented, is gone to step (4)；Otherwise, Cache is not hit by, and hit comparator will hit instruction output signal and hit selection signal is set to disarmed state, Go to step (4)；(4) when processor access type is memory write access, go to step (5), processor access type is memory read access When, go to step (6)；(5) when memory write operation starts, input data that data encoder sends processor, generated according to the BCH of selection Multinomial, BCH check codes corresponding to generation, and data are sent into each road input of data storage together, if Cache is hit, Input data and check code are write in data storage together, writing position is by hit selection signal, Cache indexes and row Address determines jointly, then terminates the operation to Cache；If be not hit by, directly terminate the operation to Cache；(6) after storage address is effective, immediately the Cache indexes in storage address and row in address, from data storage In device, point 1 tunnel, 2 tunnels or 4 tunnels read data word and check code, send each data decoder to carry out BCH decodings, data decoder According to the BCH generator polynomials of selection, BCH fast decodings are carried out using parallel algorithm, if without error in data, exported immediately Data word is to data selector；If there is 1 to 4 error in data, after data decoder is corrected to it, correct data are exported Word is to data selector；After comparator completion hit is hit relatively, if being not hit by going to step (7)；If hit, according to life The data for the data word selection hit that middle selection signal exports from each data decoder, are exported to processor cores, end pair Cache operation；(7) when reading to be not hit by, the storage address sent according to processor cores, read and Cache rows from main storage The data word of the identical quantity of size, data word is sent successively data encoder generate BCH check codes, by data word and check code one Rise in write-in data storage, writing position determines according to Cache replacement policies and Cache indexes；Then according to memory Location produces corresponding address mark, and address mark and row effective marker are sent to the BCH schools of tag encoder generation marker word together Code is tested, the check code of address mark, row effective marker and generation is write into mark memory relevant position, writing position root together Determined according to Cache replacement policies and Cache indexes, complete the renewal of Cache rows；Meanwhile according to Cache access strategies, it will deposit Data word corresponding to memory address terminates the operation to Cache through data decoder, data selector sending processor kernel.
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| CN108897701B (en) * | 2018-06-20 | 2020-07-14 | 珠海市杰理科技股份有限公司 | cache storage device |
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| US8762821B2 (en) * | 2012-03-30 | 2014-06-24 | Intel Corporation | Method of correcting adjacent errors by using BCH-based error correction coding |
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| CN101980339A (en) * | 2010-11-04 | 2011-02-23 | 浙江大学 | Error correction encoding method for dynamic random access memory (DRAM) buffer |
| CN102545914A (en) * | 2010-12-27 | 2012-07-04 | 联芯科技有限公司 | BCH (Broadcast Channel) encoding and decoding method and device |
| CN204833244U (en) * | 2015-08-19 | 2015-12-02 | 首都师范大学 | Embedded microprocessor cache 4 figure place is according to wrong correction device of upset |
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