CN204833243U - Embedded microprocessor cache's hybrid error correction device - Google Patents
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Abstract
The utility model provides an embedded microprocessor cache's hybrid error correction device which characterized in that: including EDAC label coding ware, BCH label coding ware, the mark memory, EDAC mark decoder, BCH mark decoder, the EDAC data code ware, the BCH data code ware, a data memory, EDAC data decoder, BCH data decoder, hit judgement ware and data selector, adopt EDAC and the mixed coding method of the binary system BCH long numeric data mistake in to cache mark memory and data memory to carry out the error correction, and can carry out quick error correction according to the mistake to 1 figure place.
Description
Technical field
The utility model relates to a kind of error correction device of microprocessor cache error in data, particularly relates to a kind of error correction device of embedded microprocessor high-speed cache long numeric data mistake.
Background technology
Single-particle inversion (SEU) is under the applied environment of space, because single-particle incidence causes the event of storage unit generation Data flipping mistake in integrated circuit, is that under space environment, electronic system breaks down and one of the major incentive of operation irregularity.SEU main manifestations was the unit data upset fault of single storage unit in the past, but after integrated circuit adopts nanometer technology, along with the reduction of the reduction of feature sizes of semiconductor devices, the rising of frequency of operation and node operating voltage, in the memory unit that high-speed cache (Cache) etc. is regular, the probability that SEU causes Multiple-bit upsets (MBU) improves greatly, maximum 8 random data upset mistake can be caused, larger harm is produced to the electronic system of space application.
As the important component part of in Modern microprocessor, Cache completes the buffering of program code and data, provides instruction code and data to processor cores (as streamline).If the storage unit generation error in data in Cache, directly will cause the instruction of microprocessor execution error, or carries out computing to the data of mistake, and then produce the execution result of mistake.Therefore, for the highly reliable microprocessor of space application, the error in data carrying out Cache system is automatically corrected and is had great importance.
Existing general purpose microprocessor (as alpha21264, Itanium, Powerpc-a10 etc.) mainly adopts parity check sum ECC (ErrorCorrectingCodes; error correcting code) check code realizes the error protection of Cache, and its limitation can only be corrected single-bit error and detect double-bit errors.The MS-ECC scheme that the people such as Chishti propose based on cache lines granularity, area and performance cost are very large.The people such as Kim propose two-dimentional check code can correct multi-bit error, but it is lower for the random error efficiency of dispersion.Intel proposed VS-ECC scheme in 2011, used for different Cache blocks the algorithm that error correcting capability is different, reduced area and performance cost that algorithm brings, but still had to be hoisted in fault-tolerant ability.Data heavy duty strategy based on grouping parity checking is used to multiple space microprocessor at present, and for carrying out fault-tolerant to the error in data of Cache, but the method can only solve 1 bit-errors problem in group, cannot tackle the multidigit random error that single-particle brings out.In a word, the 2-4 position random error that existing technical scheme causes for MBU lacks effective fault-tolerant networks.
Adopting Cache data error detection, forcing Cache not hit when makeing mistakes, by refitting Cache correction of data mistake, is also a kind of fault-tolerance approach of effective Cache Data flipping fault.But this method can reduce the hit rate of Cache, in the system of DRAM class storer using current widespread use, Cache inefficacy expense is general all larger, simultaneously, under nanometer technology, SEU causes the probability of error in data greatly to improve, therefore, and this execution efficiency that can reduce processor based on Cache refitting fault-tolerance approach.
For the needs of application highly reliable under the environment such as space, Bose-Chaudhuri-Hocquenghem Code mode can be adopted to protect Cache data-carrier store and Cache mark memory.BCH (Bose-Chaudhuri-Hocquenheim) coding is that one is defined in finite field gf (q) Linear cyclic block code, can correct the multiple mistakes in packet.Binary BCH codes is the BCH code that one is defined on finite field gf (2), the error control code of the multidigit random error in also correction of data grouping can be detected, have that error correcting capability is strong, structure is convenient, the advantage such as simple of encoding, in the communications field, (as digital broadcasting, 3G network, optical communication etc.) are widely used.
Error correction method based on BCH encoding and decoding can carry out the long numeric data mistake in Cache detecting and correct, and avoids Cache data to reset the overhead brought.But BCH decoding algorithm is comparatively complicated, when making a mistake, need to take multiple clock period, complete syndrome calculating, error location polynomial calculates, errors present solves multiple step and just can complete error correcting.For a bit-errors and multi-bit error, BCH decode procedure is identical, after all needing to wait for that decode procedure completes, could provide data to CPU core, cause the streamline of CPU core to insert the time-out in multiple cycle during error correction.
Although under nanoscaled process, SEU probability of happening improves greatly, and can cause long numeric data upset, the upset mistake that SEU causes individual data position remains cardinal error pattern, accounts for larger proportion.For individual data bit-errors, adopt the Error Checking and Correcting (EDAC based on expanded Hamming code, ErrorDetectionandCorrection) algorithm has better error correction efficiency, and the make-up time is shorter, only has and needs 5-6 level gate delay to complete.Like this, when individual data bit-errors, if adopt EDAC algorithm, the data after correction can be provided to CPU core rapidly, not need to insert latent period on the streamline of CPU core, or only have insertion 1 latent period.If different Processing Algorithm can be taked for different type of error, reduce the latency delays of processor pipeline under SEU malfunction, just can improve the execution speed of microprocessor under space environment.
Summary of the invention
The purpose of this utility model is to design the quick correcting device of long numeric data upset fault in a kind of high-speed cache of embedded microprocessor anti-single particle overturn effect, the multidigit random data upset mistake that can cause SEU is corrected automatically, and can carry out quick error correction to a data mistake.
A hybrid error correction device for embedded microprocessor high-speed cache, is characterized in that: comprise EDAC tag encoder, BCH tag encoder, mark memory, EDAC marks code translator, BCH marks code translator, EDAC data encoder, BCH data encoder, data-carrier store, EDAC data decoder, BCH data decoder, hit decision device and data selector; Described EDAC tag encoder, when carrying out Cache write operation, is encoded to the address mark write and row effective marker, generates EDAC check code, stored in mark memory together with address mark; Described BCH tag encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to the address mark write, row effective marker and EDAC check code, generates BCH check code, stored in mark memory; Described mark memory is used for storage mark word and its EDAC check code and BCH check code, and described marker word comprises address mark and row effective marker two parts; Described EDAC marks code translator when carrying out Cache access, the marker word export mark memory and EDAC check code verify, 1 bit data mistake in marker word is corrected fast, and middle decision device of the marker word after error correction being lost one's life carries out Cache hit judgement; Described BCH marks code translator when carrying out Cache access, marker word, EDAC check code and BCH check code that mark memory exports are verified, generation error error correction mark, correct the multidigit random error in marker word, middle decision device of the marker word after error correction being lost one's life carries out Cache hit judgement; Described EDAC data encoder, when carrying out Cache write operation, is encoded to input data, is generated EDAC check code, stored in data-carrier store together with input data; Described BCH data encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to input data and EDAC check code, generates BCH check code, stored in data-carrier store; Described data-carrier store is for storing Cache data word and its EDAC check code and BCH check code; Described EDAC data decoder is when carrying out Cache read operation, and the data word export data-carrier store and EDAC check code verify, and correct the random error of 1 in data word, and send data selector by the data word after correcting; Described BCH data decoder is when carrying out Cache read operation, data word, EDAC check code and BCH check code that data-carrier store exports are verified, generation error error correction mark, corrects the multidigit random error in data word, and send data selector by the data word after correcting; Described hit decision device is by the mark part in the storage address of input, according to the instruction of BCH data decoder, compare with the output of EDAC data decoder or BCH data decoder, judge whether Cache hits, export hit Warning Mark, the data of control data selector switch export; The error indication signal that described data selector selects signal and BCH data decoder to send here according to the hit that hit decision device is sent here, when Cache hits, selects the data of EDAC data decoder or BCH data decoder, exports to processor cores.
The hybrid error correction device of the embedded microprocessor high-speed cache that the utility model realizes, the multidigit random error that the mark memory of Cache and data-carrier store cause due to SEU can be corrected in embedded microprocessor, and quick error correction can be carried out to single bit error wherein, reliability and handling property that microprocessor applies under the rugged surroundings such as space can be improved.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the Cache data error correcting device adopting single error correction method;
Fig. 2 is according to hybrid error correction structure drawing of device of the present utility model.
Embodiment
The present embodiment is described embodiment of the present utility model in conjunction with a kind of embedded microprocessor of SPARCV8 architecture.The embedded microprocessor of this SPARCV8 architecture, adopt 32 RISC frameworks, Instruction Cache and data Cache all adopt direct image mode, and capacity is all 2K byte, and the capable size of Cache is 4 words, and word is wide 32.When not considering fault-tolerant measure, the mark memory capacity of Cache is 128 words, word width 25, wherein address mark 21, row significant notation 4, represents that in row, whether each word is effective respectively.
When processor cores carries out memory access, after Cache is given in 32 bit memory addresses, be divided into address mark (position 31-11, totally 21), Cache index (position 10-4, totally 7) and row in address (position 3-0, totally 4, low 2 useless) three parts, wherein address mark is used for Cache hit and compares, and in Cache index and row, address is as the reference address of mark memory and data-carrier store.
Generally Cache mainly comprises three parts: Cache controller, Cache mark memory and Cache data-carrier store, affects part mainly mark memory and the data-carrier store causing error in data by SEU.When there is error in data in mark memory, can cause Cache hit or miss effect by mistake, miss effect is only generally affect Cache hit rate, causes Cache access performance to reduce, the result that can not lead to errors; Hit then can cause Cache that the data of mistake or instruction are supplied to processor cores by mistake, thus the execution result led to errors.When there is mistake in Cache data-carrier store, data or the instruction code of mistake will be provided to processor cores when hitting, the execution result led to errors.
For the needs of application highly reliable under the environment such as space, apparatus structure as shown in Figure 1 can be adopted, by EDAC coded system or Bose-Chaudhuri-Hocquenghem Code mode, Cache data-carrier store and Cache mark memory be protected.EDAC coded system can realize, to the error correction of single error in protection word, to be had and realizes simple, fireballing feature.Binary BCH codes is that a kind of energy detect and correct the error control code of multidigit random error, has the advantage that structure is convenient and error correcting capability is strong, and shortcoming is that error correction algorithm is complicated, and speed is slow.The present embodiment adopts EDAC and BCH hybrid coding mode to protect the mark memory of Cache and data-carrier store, adopting EDAC to correct fast, adopting BCH to carry out multicycle error correction to other multi-bit error to there is more a data mistake.Because BCH code translator needs multiple cycle just can complete error correction, when carrying out multidigit error correction, processor cores is placed in waiting status.
The present embodiment EDAC encodes and adopts expanded Hamming code mode, and generator matrix is defined as G
eDAC, check matrix is H
eDAC, 7 bit check codes are generated to 32 Cache data and 25 marker word, a bit-errors can be corrected.Data word (marker word) after EDAC has encoded and check code, then send Bose-Chaudhuri-Hocquenghem Code device to carry out secondary coding.Therefore, Bose-Chaudhuri-Hocquenghem Code is not only protected data word (marker word), also protects EDAC check code.
The present embodiment Bose-Chaudhuri-Hocquenghem Code adopts binary BCH codes, can correct maximum 4 bit-errors in 32 bit data (25 marker word and 7 EDAC check codes) of 39 bit data of Cache data-carrier store (32 bit data word and 7 EDAC check codes) or Cache mark memory.Bose-Chaudhuri-Hocquenghem Code code length n=63, selects primitive polynomial p (x)=x
6+ x+1, check bit number n-k=24, maximum information bit length k=39, minimum distance d
min=9.And then determine that generator polynomial is as follows:
G (x)=1+x+x
2+ x
4+ x
5+ x
6+ x
8+ x
9+ x
10+ x
13+ x
16+ x
17+ x
19+ x
20+ x
22+ x
23+ x
24the generator matrix G of [63,39] BCH code can be obtained
39 × 63as follows:
Because the data bit width of Cache data-carrier store and Cache mark memory is 39 and 32, when protecting Cache mark memory respectively, [63,39] BCH code is shortened, use the generator matrix G after shortening
32 × 56.If m is 39 or 32 bit data for coding, code word C=mG is corresponding Bose-Chaudhuri-Hocquenghem Code, and wherein check bit width is 24.
Be not difficult to obtain the BCH check matrix H of Cache data-carrier store and Cache mark memory according to generator matrix G
24 × 63and H
24 × 56, 63 that read or 56 data comprising check code are designated as R, calculate syndrome S=RH from Cache data-carrier stores or Cache mark memory
tif S is full null vector, illustrate that R does not have mistake, otherwise illustrate that R there occurs 1 to 4 bit-errors, can be solved by syndrome S and obtain error location polynomial, adopt iteration or algebraic approach all can in the hope of errors present according to error location polynomial, by can reach the object of error correcting to error bit negate.
Based on above-mentioned ultimate principle and setting, a kind of embodiment of the hybrid error correction device of embedded microprocessor high-speed cache of the present utility model is as follows:
In the embedded microprocessor of SPARCV8 architecture, high-speed cache is set to hybrid error correction device as shown in Figure 2, comprises EDAC tag encoder, BCH tag encoder, mark memory, EDAC marks code translator, BCH marks code translator, EDAC data encoder, BCH data encoder, data-carrier store, EDAC data decoder, BCH data decoder, hit decision device and data selector.
EDAC tag encoder, when carrying out Cache write operation, presses generator matrix G to the address mark write and row effective marker
eDACencode, generate 7 EDAC check codes, stored in mark memory together with address mark;
BCH tag encoder, when carrying out Cache write operation, uses generator matrix G
32 × 56, scale-of-two Bose-Chaudhuri-Hocquenghem Code is carried out to 21 bit address marks of write, 4 row effective markers and 7 EDAC check codes, generates 24 BCH check codes, stored in mark memory.
Because Cache adopts algorithm of directly videoing, mark memory adopts the storer of 128 word × 56, by sequence of addresses storage mark word (25) and its EDAC check code (7), BCH check code (24), wherein marker word comprises address mark (21) and row effective marker (4) two parts.
EDAC marks code translator when carrying out Cache access, uses check matrix H
eDACthe marker word export mark memory and EDAC check code verify, and correct fast 1 bit data mistake in marker word, and middle decision device of the marker word after error correction being lost one's life carries out Cache hit judgement.
BCH marks code translator when carrying out Cache access, uses check matrix H
24 × 56, verify marker word, EDAC check code and the BCH check code that mark memory exports, generation error error correction mark, corrects the multidigit random error in marker word, and middle decision device of the marker word after error correction being lost one's life carries out Cache hit judgement.
Hit decision device, by the mark part in the storage address of input, according to the instruction of BCH data decoder, compares with the output of EDAC data decoder or BCH data decoder, if equal, represent Cache hit, export hit in tag, control data selector switch selects data to export; If unequal, then Cache does not hit.
EDAC data encoder, when carrying out Cache write operation, uses generator matrix G
eDAC, 32 input data are encoded, generate 7 EDAC check codes, stored in data-carrier store together with input data.
BCH data encoder, when carrying out Cache write operation, uses generator matrix G
39 × 63, scale-of-two Bose-Chaudhuri-Hocquenghem Code is carried out to 32 input data and 7 EDAC check codes, generates 24 BCH check codes, stored in data-carrier store
Data-carrier store adopts the storer of 512 word × 63, for storing 32 Cache data words and its 7 EDAC check codes and 24 BCH check codes.
EDAC data decoder, when carrying out Cache read operation, uses check matrix H
eDAC, the data word export data-carrier store and EDAC check code verify, and correct the random error of 1 in data word, and send data selector by the data word after correcting.
BCH data decoder, when carrying out Cache read operation, uses check matrix H
24 × 63, verify data word, EDAC check code and the BCH check code that data-carrier store exports, generation error error correction mark, corrects the random error of 2 to 4 in data word, and send data selector by the data word after correcting.
The error indication signal that data selector selects signal and BCH data decoder to send here according to the hit that hit decision device is sent here, when Cache hits, selects the data of EDAC data decoder or BCH data decoder, exports to processor cores.
The hybrid error correction device of the embedded microprocessor high-speed cache of described SPARCV8 architecture adopts following steps and method carry out detecting to the error in data in Cache and correct:
(1) during initial reset, marks all in mark memory are all write full 0, it is invalid that all row effective markers are set to, and all check codes are all set to effective check code; Data words all in data-carrier store are all set to full 0, and all check codes are all set to effective check code;
(2) processor carries out storer when reading or writing access, 32 bit memory addresses are divided into address three part in 21 bit address marks, 7 Cache indexes and 4 row, according to Cache index from mark memory, read 25 marker word and 7 EDAC check codes and 24 BCH check codes, send EDAC to mark code translator and BCH mark code translator, go to step (3);
(3) EDAC mark code translator and the decoding of BCH mark verify marker word according to corresponding decoding rule respectively, and correct a mistake, if there is no mistake, EDAC marks code translator and BCH marks the direct output token word of code translator to hit decision device, BCH marks code translator and exports without mismark, goes to step (4); If there is a bit-errors, EDAC marks code translator and corrects fast mistake, and the marker word after error correction is exported to hit decision device, and BCH marks code translator and exports a bit-errors mark, goes to step (4); If there are 2 to 4 bit-errors, BCH mark code translator exports multi-bit error mark, and the marker word after error correction is exported to hit decision device, go to step (4) after correcting mistake;
(4) if BCH mark that code translator exports effective without mismark or a bit-errors mark, the marker word that hit decision device uses EDAC to mark code translator output is immediately carried out hit and is compared, and goes to step (5); If the multi-bit error mark that BCH mark code translator exports effectively, after hit decision device waits for that BCH mark code translator completes error correction, the marker word using BCH mark code translator to export is carried out hit and is compared, and goes to step (5); If a bit-errors mark or the multi-bit error mark of the output of BCH mark code translator are effective, EDAC tag encoder and BCH tag encoder is sent by the marker word after correcting, generate corresponding check code, re-write mark memory together with the marker word after correcting, correct the mistake in mark memory;
(5) 21 bit address in address mark (21) and the storage address in the marker word after correcting are marked compare, if equal, and when in row, row effective marker corresponding to address is effective status, represent Cache hit, hit comparer exports effective hit and selects signal to data selector, goes to step (6); Otherwise Cache does not hit, hit instruction output signal and hit select signal to be set to disarmed state by hit comparer, go to step (6);
(6), when processor access type is memory write access, go to step (7); When processor access type is storer read access, if Cache hit, goes to step (8), if do not hit, go to step (10);
(7) when memory write operation starts, EDAC data encoder is encoded to 32 Input Data words that processor is sent here immediately, generate 7 EDAC check codes, send data-carrier store and BCH data encoder, BCH data encoder is encoded to 32 Input Data words and 7 EDAC check codes, generates 24 BCH check codes; If Cache hits, will input data, EDAC check code and BCH check code and write together with totally 63 in data-carrier store, writing position selects address in signal, Cache index and row jointly to determine by hitting, and then terminates the operation to Cache; If Cache does not hit, directly terminate the operation to Cache;
(8) storage address effectively after, immediately according to address in the Cache index in storage address and row, sense data word, EDAC check code and BCH check code from data-carrier store, send EDAC data decoder and BCH data decoder, uses check matrix H respectively
eDACand check matrix H
24 × 63verify data word, and correct a mistake, if do not have mistake, EDAC data decoder and the direct output data word of BCH data decoder are to data selector, and BCH data decoder exports data without mismark, goes to step (9); If there is a bit-errors, EDAC data note code translator is corrected fast to mistake, and the data word after error correction is exported to data selector, and BCH data decoder exports a bit-errors mark, goes to step (9); If there are 2 to 4 bit-errors, BCH data decoder exports multi-bit error mark, and starts error correction process, goes to step (9);
(9) if BCH data decoder export without mismark or a bit-errors mark effective, the data word that EDAC data decoder exports is exported to processor cores by data selector immediately, hit decision device exports hit indicator signal, terminates the operation of Cache; If the multi-bit error mark that BCH data decoder exports is effective, after waiting for that BCH data decoder completes error correction procedure, the data word that BCH data decoder exports is exported to processor cores by data selector, and hit decision device exports hit indicator signal, terminates the operation of Cache; If a bit-errors mark or the multi-bit error mark of the output of BCH data decoder are effective, when terminating Cache operation, EDAC data encoder and BCH data encoder is sent by the data word after correcting, generate corresponding EDAC check code and BCH check code, data-carrier store is re-write, the mistake in correction of data storer together with the data word after correcting;
(10) when reading not hit, according to the storage address that processor cores is sent here, the data word with the capable size equal number of Cache is read from primary memory, EDAC data encoder data word is sent to generate EDAC check code successively, BCH data encoder data word and EDAC check code is sent to generate BCH check code again, then write in data-carrier store by data word, EDAC check code together with BCH check code, writing position is determined by Cache index; Then corresponding address mark is produced according to storage address, address mark and row effective marker are formed marker word together, EDAC tag encoder and BCH tag encoder is sent to generate EDAC check code and BCH check code, the EDAC check code of marker word and generation is write the position that in mark memory, Cache index is specified together with BCH check code, completes the renewal that Cache is capable; Meanwhile, by data word corresponding for storage address through EDAC data decoder, data selector sending processor kernel, in mission, decision device exports hit indicator signal, terminates the operation to Cache.
The hybrid error correction device of the embedded microprocessor high-speed cache that the utility model realizes, can carry out detecting to multidigit random data mistake in embedded microprocessor high-speed cache and correct, can correct fast the more a data mistake of generation, reliability and handling property that embedded microprocessor works under space environment can be improved.
In the scope not departing from the utility model spirit, the utility model can have various deformation, as: the selection etc. of Cache volume change, EDAC generator polynomial, BCH generator matrix, all can change in different enforcement.These distortion are also contained within the utility model scope required for protection.
Claims (1)
1. a hybrid error correction device for embedded microprocessor high-speed cache, is characterized in that: comprise EDAC tag encoder, BCH tag encoder, mark memory, EDAC marks code translator, BCH marks code translator, EDAC data encoder, BCH data encoder, data-carrier store, EDAC data decoder, BCH data decoder, hit decision device and data selector; Described EDAC tag encoder, when carrying out Cache write operation, is encoded to the address mark write and row effective marker, generates EDAC check code, stored in mark memory together with address mark; Described BCH tag encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to the address mark write, row effective marker and EDAC check code, generates BCH check code, stored in mark memory; Described mark memory is used for storage mark word and its EDAC check code and BCH check code, and described marker word comprises address mark and row effective marker two parts; Described EDAC marks code translator when carrying out Cache access, the marker word export mark memory and EDAC check code verify, 1 bit data mistake in marker word is corrected fast, and middle decision device of the marker word after error correction being lost one's life carries out Cache hit judgement; Described BCH marks code translator when carrying out Cache access, marker word, EDAC check code and BCH check code that mark memory exports are verified, generation error error correction mark, correct the multidigit random error in marker word, middle decision device of the marker word after error correction being lost one's life carries out Cache hit judgement; Described EDAC data encoder, when carrying out Cache write operation, is encoded to input data, is generated EDAC check code, stored in data-carrier store together with input data; Described BCH data encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to input data and EDAC check code, generates BCH check code, stored in data-carrier store; Described data-carrier store is for storing Cache data word and its EDAC check code and BCH check code; Described EDAC data decoder is when carrying out Cache read operation, and the data word export data-carrier store and EDAC check code verify, and correct the random error of 1 in data word, and send data selector by the data word after correcting; Described BCH data decoder is when carrying out Cache read operation, data word, EDAC check code and BCH check code that data-carrier store exports are verified, generation error error correction mark, corrects the multidigit random error in data word, and send data selector by the data word after correcting; Described hit decision device is by the mark part in the storage address of input, according to the instruction of BCH data decoder, compare with the output of EDAC data decoder or BCH data decoder, judge whether Cache hits, export hit Warning Mark, the data of control data selector switch export; The error indication signal that described data selector selects signal and BCH data decoder to send here according to the hit that hit decision device is sent here, when Cache hits, selects the data of EDAC data decoder or BCH data decoder, exports to processor cores.
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| CN105138412B (en) * | 2015-08-19 | 2018-03-20 | 首都师范大学 | The hybrid error correction apparatus and method of embedded microprocessor cache |
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