CN105022675A - Correcting device and method for caching 4-bit data flipping errors of embedded microprocessor - Google Patents
Correcting device and method for caching 4-bit data flipping errors of embedded microprocessor Download PDFInfo
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Abstract
A correcting device for caching 4-bit data flipping errors of an embedded microprocessor is characterized by comprising a mark encoder, a mark memory, a mark decoder, a data encoder, a data memory, a data decoder, a hitting comparator and a data selector. At most 4-bit data errors in the Cache mark memory and the data memory are corrected by using binary system BCH codes according to a selected Cache management strategy.
Description
Technical field
The present invention relates to a kind of correcting device of microprocessor cache error in data, particularly relate to the correcting device of a kind of embedded microprocessor high-speed cache long numeric data upset mistake.The invention still further relates to the correcting method of a kind of embedded microprocessor high-speed cache long numeric data upset mistake.
Background technology
Single-particle inversion (SEU) is under the applied environment of space, because single-particle incidence causes the event of storage unit generation Data flipping mistake in integrated circuit, is that under space environment, electronic system breaks down and one of the major incentive of operation irregularity.SEU main manifestations was the unit data upset fault of single storage unit in the past, but after integrated circuit adopts nanometer technology, along with the reduction of the reduction of feature sizes of semiconductor devices, the rising of frequency of operation and node operating voltage, in the memory unit that high-speed cache (Cache) etc. is regular, the probability that SEU causes Multiple-bit upsets (MBU) improves greatly, maximum 8 random data upset mistake can be caused, larger harm is produced to the electronic system of space application.
As the important component part of in Modern microprocessor, Cache completes the buffering of program code and data, provides instruction code and data to processor cores (as streamline).If the storage unit generation error in data in Cache, directly will cause the instruction of microprocessor execution error, or carries out computing to the data of mistake, and then produce the execution result of mistake.Therefore, for the highly reliable microprocessor of space application, the error in data carrying out Cache system is automatically corrected and is had great importance.
Existing general purpose microprocessor (as alpha21264, Itanium, Powerpc-a10 etc.) mainly adopts parity check sum ECC (Error Correcting Codes; error correcting code) check code realizes the error protection of Cache, and its limitation can only be corrected single-bit error and detect double-bit errors.The MS-ECC scheme that the people such as Chishti propose based on cache lines granularity, area and performance cost are very large.The people such as Kim propose two-dimentional check code can correct multi-bit error, but it is lower for the random error efficiency of dispersion.Intel proposed VS-ECC scheme in 2011, used for different Cache blocks the algorithm that error correcting capability is different, reduced area and performance cost that algorithm brings, but still had to be hoisted in fault-tolerant ability.Data heavy duty strategy based on grouping parity checking is used to multiple space microprocessor at present, and for carrying out fault-tolerant to the error in data of Cache, but the method can only solve 1 bit-errors problem in group, cannot tackle the multidigit random error that single-particle brings out.In a word, the 2-4 position random error that existing technical scheme causes for MBU lacks effective fault-tolerant networks.
Adopting Cache data error detection, forcing Cache not hit when makeing mistakes, by refitting Cache correction of data mistake, is also a kind of fault-tolerance approach of effective Cache Data flipping fault.But this method can reduce the hit rate of Cache, in the system of DRAM class storer using current widespread use, Cache inefficacy expense is general all larger, simultaneously, under nanometer technology, SEU causes the probability of error in data greatly to improve, therefore, and this execution efficiency that can reduce processor based on Cache refitting fault-tolerance approach.
Summary of the invention
The object of the invention is to design correcting device and the method for maximum 4 bit data upset faults in a kind of high-speed cache of embedded microprocessor anti-single particle overturn effect, can maximum 4 random data upset mistakes that SEU cause be corrected automatically.
A kind of embedded microprocessor high-speed cache 4 bit data upset error correcting device, is characterized in that: comprise tag encoder, mark memory, mark code translator, data encoder, data-carrier store, data decoder, hit comparer and data selector; Described tag encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to the Cache address mark write and row effective marker, generates check code, stored in mark memory together with address mark; Described mark memory is used for according to Cache operating strategy, point 1 tunnel, 2 roads or 4 tunnel storage mark words and its BCH check code, and described marker word comprises address mark and row effective marker two parts; Described mark code translator is when carrying out Cache access, the marker word export mark memory and check code carry out BCH verification, correct the random error of 1 to 4 in marker word, and verification is correct or after correcting a mistake marker word is lost one's life, middle comparer carries out Cache hit judgement; Described data encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to input data, generates check code, stored in data-carrier store together with input data; Described data-carrier store is used for according to Cache operating strategy, and point 1 tunnel, 2 roads or 4 tunnels store Cache data word and its BCH check code; Described data decoder is when carrying out Cache read operation, the data export data-carrier store and word check code carry out BCH verification, in data word 1 to 4 random error is corrected, and verification is correct or after correcting a mistake data word send data selector to export to processor cores; Mark part in the storage address of input and each are marked the marker word that code translator exports and compare by described hit comparer, judge whether Cache hits, and export hit in tag, and control data selector switch selects data to export; Signal is selected in the hit that described data selector is sent here according to hit comparer, from the output of multiple data decoder, select real hiting data to export to processor cores.
A kind of embedded microprocessor high-speed cache 4 bit data upset error correction method, is characterized in that: described embedded microprocessor high-speed cache 4 bit data upset error correcting device comprises tag encoder, mark memory, mark code translator, data encoder, data-carrier store, data decoder, hit comparer and data selector; Described embedded microprocessor high-speed cache 4 bit data upset error correcting device adopts following steps and method carry out detecting to the maximum 4 bit data mistakes in Cache and correct:
(1) during initial reset, marks all in mark memory are all write full 0, it is invalid that all row effective markers are set to, and the check code of all marker word is all set to effective BCH check code;
(2) processor carries out storer when reading or writing access, storage address is divided into address three part in address mark, Cache index and row, according to Cache index from mark memory, 1 tunnel, 2 roads or 4 tunnels are divided to read Cache mark, row effective marker and check code, each mark code translator is given to carry out BCH decoding, mark code translator is according to the BCH generator polynomial selected, parallel algorithm is adopted to carry out BCH fast decoding, if there is no error in data, export Cache mark and row effective marker immediately, go to step (3); If there is 1 to 4 bit data mistake, after mark code translator is corrected it, export correct Cache mark and row effective marker, go to step (3);
(3) each Cache that step (2) reads is marked in hit comparer, compare with the address tag portion in storage address, if some Cache marks are equal with address mark, and when in row, row effective marker corresponding to address is effective status, represent Cache hit, hit comparer exports effective hit indicator signal and signal is selected in hit, goes to step (4); Otherwise Cache does not hit, hit instruction output signal and hit select signal to be set to disarmed state by hit comparer, go to step (4);
(4) when processor access type is memory write access, go to step (5), when processor access type is storer read access, go to step (6);
(5) when memory write operation starts, the input data that processor is sent here by data encoder, according to the BCH generator polynomial selected, generate corresponding BCH check code, send into each road input of data-carrier store together with data, if Cache hit, input data are write in data-carrier store together with check code, writing position selects address in signal, Cache index and row jointly to determine by hitting, and then terminates the operation to Cache; If do not hit, directly terminate the operation to Cache;
(6) storage address effectively after, immediately according to address in the Cache index in storage address and row, from data-carrier store, divide 1 tunnel, 2 roads or 4 tunnel sense data word and check codes, give each data decoder to carry out BCH decoding, data decoder, according to the BCH generator polynomial selected, adopts parallel algorithm to carry out BCH fast decoding, if do not have error in data, output data word is to data selector immediately; If there is 1 to 4 bit data mistake, data decoder exports correct data word to data selector after correcting it; After hit comparer completes hit relatively, go to step (7) if do not hit; If hit, select signal to select the data of hit from the data word that each data decoder exports according to hit, export to processor cores, terminate the operation to Cache;
(7) when reading not hit, according to the storage address that processor cores is sent here, the data word with the capable size equal number of Cache is read from primary memory, data encoder data word is sent to generate BCH check code successively, data word and check code are write together in data-carrier store, writing position is determined according to Cache replacement policy and Cache index; Then corresponding address mark is produced according to storage address, tag encoder address mark and row effective marker is sent to generate the BCH check code of marker word together, the check code of address mark, row effective marker and generation is write mark memory relevant position together, writing position is determined according to Cache replacement policy and Cache index, completes the renewal that Cache is capable; Meanwhile, according to Cache access strategy, by data word corresponding for storage address through data decoder, data selector sending processor kernel, terminate the operation to Cache.
The correcting device of the embedded microprocessor high-speed cache 4 bit data upset mistake that the present invention realizes and method, 1 to 4 random error that the mark memory of Cache and data-carrier store cause due to SEU can be corrected in embedded microprocessor, the reliability that microprocessor is applied under the rugged surroundings such as space can be improved.
Accompanying drawing explanation
Fig. 1 is that high-speed cache adopts when directly videoing, according to the correcting device structural drawing of 4 bit data upset mistakes according to the present invention;
When Fig. 2 is high-speed cache employing two-way set associative, according to 4 bit data upset error correcting device structural drawing according to the present invention;
Fig. 3 is high-speed cache when adopting four road set associatives, according to 4 bit data upset error correcting device structural drawing according to the present invention.
Embodiment
The present embodiment is described the specific embodiment of the present invention in conjunction with a kind of embedded microprocessor of SPARC V8 architecture.The embedded microprocessor of this SPARC V8 architecture, adopt 32 RISC frameworks, Instruction Cache and data Cache all adopt direct image mode, and capacity is all 2K byte, and the capable size of Cache is 4 words, and word is wide 32.When not considering fault-tolerant measure, the mark memory capacity of Cache is 128 words, word width 25, wherein address mark 21, row significant notation 4, represents that in row, whether each word is effective respectively.
When processor cores carries out memory access, after Cache is given in 32 bit memory addresses, be divided into address mark (position 31-11, totally 21), Cache index (position 10-4, totally 7) and row in address (position 3-0, totally 4, low 2 useless) three parts, wherein address mark is used for Cache hit and compares, and in Cache index and row, address is as the reference address of mark memory and data-carrier store.
Generally Cache mainly comprises three parts: Cache controller, Cache mark memory and Cache data-carrier store, affects part mainly mark memory and the data-carrier store causing error in data by SEU.When there is error in data in mark memory, can cause Cache hit or miss effect by mistake, miss effect is only generally affect Cache hit rate, causes Cache access performance to reduce, the result that can not lead to errors; Hit then can cause Cache that the data of mistake or instruction are supplied to processor cores by mistake, thus the execution result led to errors.When there is mistake in Cache data-carrier store, data or the instruction code of mistake will be provided to processor cores when hitting, the execution result led to errors.
For the needs of application highly reliable under the environment such as space, Bose-Chaudhuri-Hocquenghem Code mode can be adopted to protect Cache data-carrier store and Cache mark memory.BCH (Bose-Chaudhuri-Hocquenheim) coding is that one is defined in finite field gf (q) Linear cyclic block code, can correct the multiple mistakes in packet.Binary BCH codes is the BCH code that one is defined on finite field gf (2), the error control code of the multidigit random error in also correction of data grouping can be detected, have that error correcting capability is strong, structure is convenient, the advantage such as simple of encoding, in the communications field, (as digital broadcasting, 3G network, optical communication etc.) are widely used.
The present embodiment adopts binary BCH codes, 32 bit data of Cache data-carrier store and 25 bit data of Cache mark memory is carried out to the automatic correction of maximum 4 bit-errors.Determine Bose-Chaudhuri-Hocquenghem Code code length n=63, select primitive polynomial p (x)=x
6+ x+1, check bit number n-k=24, maximum information bit length k=39, minimum distance d
min=9.And then determine that generator polynomial is as follows:
G (x)=1+x+x
2+ x
4+ x
5+ x
6+ x
8+ x
9+ x
10+ x
13+ x
16+ x
17+ x
19+ x
20+ x
22+ x
23+ x
24the generator matrix G of [63,39] BCH code can be obtained
39 × 63as follows:
Because the data bit width of Cache data-carrier store and Cache mark memory is 32 and 25 respectively, [63,39] BCH code is shortened, just can obtain the generator matrix G after shortening
32 × 56and G
25 × 49.If m is 32 or 25 bit data for coding, code word C=mG is corresponding Bose-Chaudhuri-Hocquenghem Code, and wherein check bit width is 24.
Be not difficult to obtain the BCH check matrix H of Cache data-carrier store and Cache mark memory according to generator matrix G
24 × 56and H
24 × 49, 56 that read or 49 data comprising check code are designated as R, calculate syndrome S=RH from Cache data-carrier stores or Cache mark memory
tif S is full null vector, illustrate that R does not have mistake, otherwise illustrate that R there occurs 1 to 4 bit-errors, can be solved by syndrome S and obtain error location polynomial, adopt iteration or algebraic approach all can in the hope of errors present according to error location polynomial, by can reach the object of error correcting to error bit negate.
Based on above-mentioned ultimate principle and setting, a kind of embodiment of embedded microprocessor high-speed cache 4 bit data upset error correcting device of the present invention is as follows:
In the embedded microprocessor of SPARC V8 architecture, high-speed cache is set to 4 bit data upset error correcting devices as shown in Figure 1, comprises tag encoder, mark memory, mark code translator, hit comparer, data encoder, data-carrier store, data decoder and data selector.
Tag encoder, when carrying out Cache write operation, uses generator matrix G
25 × 49, scale-of-two Bose-Chaudhuri-Hocquenghem Code is carried out to the address mark write and row effective marker, generates check code, stored in mark memory together with address mark.
Owing to adopting algorithm of directly videoing, mark memory adopts the storer of 128 word × 49, by sequence of addresses storage mark word (25) and its BCH check code (24), wherein marker word comprises address mark (21) and row effective marker (4) two parts.
Owing to adopting algorithm of directly videoing, 4 bit data upset error correcting devices arrange 1 mark code translator, when carrying out Cache access, use check matrix H
24 × 49, the marker word export mark memory and check code carry out BCH verification, correct the random error of 1 to 4 in marker word, and verification is correct or after correcting a mistake marker word is lost one's life, middle comparer carries out Cache hit judgement.
The marker word that mark part in the storage address of input and mark code translator export compares by hit comparer, if equal, represent Cache hit, export hit in tag, control data selector switch selects data to export; If unequal, then Cache does not hit.
Data encoder, when carrying out Cache write operation, uses generator matrix G
32 × 56, scale-of-two Bose-Chaudhuri-Hocquenghem Code is carried out to input data, generates 24 bit check codes, stored in data-carrier store together with input data.
Data-carrier store adopts the storer of 512 word × 56, for storing 32 Cache data words and its 24 BCH check codes.
Owing to adopting algorithm of directly videoing, 4 bit data upset error correcting devices arrange 1 data decoder, when carrying out Cache read operation, use check matrix H
24 × 56, the data word export data-carrier store and check code carry out BCH verification, correct the random error of 1 to 4 in data word, and verification is correct or after correcting a mistake data word send data selector to export to processor cores.
When the hit that hit comparer is sent here selects signal effective, the data that data decoder exports are given processor cores by data selector.
The embedded microprocessor high-speed cache 4 bit data upset error correcting device of described SPARC V8 architecture adopts following steps and method carry out detecting to the error in data in Cache and correct:
(1) during initial reset, by tag encoder, Cache marks all in mark memory are all write full 0, and it is invalid that all row effective markers are all set to, and the BCH check code of all marker word is all set to effective BCH check code.
(2) processor carries out storer when reading or writing access, 32 bit memory addresses are divided into address three part in 21 bit address marks, 7 Cache indexes and 4 row, from mark memory, Cache mark, row effective marker and check code is read according to Cache index, mark code translator is sent to carry out BCH decoding, mark code translator is according to the BCH generator polynomial selected, parallel algorithm is adopted to carry out BCH fast decoding, if there is no error in data, export Cache mark and row effective marker immediately, go to step (3); If there is 1 to 4 bit data mistake, after mark code translator is corrected it, export correct Cache mark and row effective marker, go to step (3);
(3) Cache that step (2) reads is marked in hit comparer, compare with the address tag portion in storage address, if Cache mark is equal with address mark, and when in row, row effective marker corresponding to address is effective status, represent Cache hit, hit comparer exports effective hit indicator signal and signal is selected in hit, goes to step (4); Otherwise Cache does not hit, hit instruction output signal and hit select signal to be set to disarmed state by hit comparer, go to step (4);
(4) when processor access type is memory write access, go to step (5), when processor access type is storer read access, go to step (6);
(5) when memory write operation starts, the input data that processor is sent here by data encoder immediately, according to the BCH generator polynomial selected, generate corresponding BCH check code, send into each road input of data-carrier store together with data, if Cache hit, input data are write in data-carrier store together with check code, writing position selects address in signal, Cache index and row jointly to determine by hitting, and then terminates the operation to Cache; If do not hit, directly terminate the operation to Cache;
(6) storage address effectively after, immediately according to address in the Cache index in storage address and row, sense data word and check code from data-carrier store, data decoder is sent to carry out BCH decoding, data decoder is according to the BCH generator polynomial selected, adopt parallel algorithm to carry out BCH fast decoding, if do not have error in data, output data word is to data selector immediately; If there is 1 to 4 bit data mistake, data decoder exports correct data word to data selector after correcting it; After hit has relatively been compared in hit, go to step (7) if do not hit; If hit, select signal to select the data of hit from the data word that data decoder exports according to hit, export to processor cores, terminate the operation to Cache;
(7) when reading not hit, according to the storage address that processor cores is sent here, the data word with the capable size equal number of Cache is read from primary memory, data word sent data encoder to generate BCH check code successively, data word and check code are write the position that in data-carrier store, Cache index indicates together; Then corresponding address mark is produced according to storage address, tag encoder address mark and row effective marker is sent to generate the BCH check code of marker word together, the check code of address mark, row effective marker and generation is write the position that in mark memory, Cache index is determined together, completes the renewal that Cache is capable; Meanwhile, by data word corresponding for storage address through data decoder, data selector sending processor kernel, the operation to Cache is terminated.
Owing to have employed aforementioned [63,39] BCH code generator polynomial, the present embodiment can be corrected any 1 to 4 random error in Cache data-carrier store and Cache mark memory.
The mapping rule of embedded microprocessor high-speed cache 4 bit data upset error correcting device can only select direct reflection, two-way set associative or four road set associatives.When adopting the Cache mapping rule of directly reflection, the structure of embedded microprocessor high-speed cache 4 bit data upset error correcting device as shown in Figure 1; When adopting the Cache mapping rule of two-way set associative, the structure of embedded microprocessor high-speed cache 4 bit data upset error correcting device as shown in Figure 2; When adopting the Cache mapping rule of four road set associatives, the structure of embedded microprocessor high-speed cache 4 bit data upset error correcting device as shown in Figure 3.
The embedded microprocessor high-speed cache 4 bit data upset error correcting device that the present invention realizes and method, solve the detection of 1 to 4 random data mistake in embedded microprocessor high-speed cache and automatic correction problem, reliability and handling property that embedded microprocessor works under space environment can be improved.
Without departing from the spirit of the scope of the invention, the present invention can have various deformation, as: the selection etc. of Cache volume change, mapping rule, all can change in different enforcement.These distortion are also contained within the present invention's scope required for protection.
Claims (4)
1. an embedded microprocessor high-speed cache 4 bit data upset error correcting device, is characterized in that: comprise tag encoder, mark memory, mark code translator, data encoder, data-carrier store, data decoder, hit comparer and data selector; Described tag encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to the Cache address mark write and row effective marker, generates check code, stored in mark memory together with address mark; Described mark memory is used for according to Cache operating strategy, point 1 tunnel, 2 roads or 4 tunnel storage mark words and its BCH check code, and described marker word comprises address mark and row effective marker two parts; Described mark code translator is when carrying out Cache access, the marker word export mark memory and check code carry out BCH verification, correct the random error of 1 to 4 in marker word, and verification is correct or after correcting a mistake marker word is lost one's life, middle comparer carries out Cache hit judgement; Described data encoder, when carrying out Cache write operation, carries out scale-of-two Bose-Chaudhuri-Hocquenghem Code to input data, generates check code, stored in data-carrier store together with input data; Described data-carrier store is used for according to Cache operating strategy, and point 1 tunnel, 2 roads or 4 tunnels store Cache data word and its BCH check code; Described data decoder is when carrying out Cache read operation, the data export data-carrier store and word check code carry out BCH verification, in data word 1 to 4 random error is corrected, and verification is correct or after correcting a mistake data word send data selector to export to processor cores; Mark part in the storage address of input and each are marked the marker word that code translator exports and compare by described hit comparer, judge whether Cache hits, and export hit in tag, and control data selector switch selects data to export; Signal is selected in the hit that described data selector is sent here according to hit comparer, from the output of multiple data decoder, select real hiting data to export to processor cores.
2. 4 bit data upset error correcting devices according to claim 1, is characterized in that: the quantity of described mark code translator is 1,2 or 4, export respectively carry out School Affairs error correction to a road of mark memory; The quantity of described data decoder is 1,2 or 4, exports respectively carry out School Affairs error correction to a road of data-carrier store.
3. 4 bit data upset error correcting devices according to claim 2, it is characterized in that: the quantity of the storage way of described mark memory, data-carrier store and mark code translator, data decoder, determined by selected Cache mapping ruler, selectable Cache mapping ruler is direct reflection, two-way set associative or four road set associatives.
4. an embedded microprocessor high-speed cache 4 bit data upset error correction method, is characterized in that: described embedded microprocessor high-speed cache 4 bit data upset error correcting device comprises tag encoder, mark memory, mark code translator, data encoder, data-carrier store, data decoder, hit comparer and data selector; Described embedded microprocessor high-speed cache 4 bit data upset error correcting device adopts following steps and method carry out detecting to the maximum 4 bit data mistakes in Cache and correct:
(1) during initial reset, marks all in mark memory are all write full 0, it is invalid that all row effective markers are set to, and the check code of all marker word is all set to effective BCH check code;
(2) processor carries out storer when reading or writing access, storage address is divided into address three part in address mark, Cache index and row, according to Cache index from mark memory, 1 tunnel, 2 roads or 4 tunnels are divided to read Cache mark, row effective marker and check code, each mark code translator is given to carry out BCH decoding, mark code translator is according to the BCH generator polynomial selected, parallel algorithm is adopted to carry out BCH fast decoding, if there is no error in data, export Cache mark and row effective marker immediately, go to step (3); If there is 1 to 4 bit data mistake, after mark code translator is corrected it, export correct Cache mark and row effective marker, go to step (3);
(3) each Cache that step (2) reads is marked in hit comparer, compare with the address tag portion in storage address, if some Cache marks are equal with address mark, and when in row, row effective marker corresponding to address is effective status, represent Cache hit, hit comparer exports effective hit indicator signal and signal is selected in hit, goes to step (4); Otherwise Cache does not hit, hit instruction output signal and hit select signal to be set to disarmed state by hit comparer, go to step (4);
(4) when processor access type is memory write access, go to step (5), when processor access type is storer read access, go to step (6);
(5) when memory write operation starts, the input data that processor is sent here by data encoder, according to the BCH generator polynomial selected, generate corresponding BCH check code, send into each road input of data-carrier store together with data, if Cache hit, input data are write in data-carrier store together with check code, writing position selects address in signal, Cache index and row jointly to determine by hitting, and then terminates the operation to Cache; If do not hit, directly terminate the operation to Cache;
(6) storage address effectively after, immediately according to address in the Cache index in storage address and row, from data-carrier store, divide 1 tunnel, 2 roads or 4 tunnel sense data word and check codes, give each data decoder to carry out BCH decoding, data decoder, according to the BCH generator polynomial selected, adopts parallel algorithm to carry out BCH fast decoding, if do not have error in data, output data word is to data selector immediately; If there is 1 to 4 bit data mistake, data decoder exports correct data word to data selector after correcting it; After hit comparer completes hit relatively, go to step (7) if do not hit; If hit, select signal to select the data of hit from the data word that each data decoder exports according to hit, export to processor cores, terminate the operation to Cache;
(7) when reading not hit, according to the storage address that processor cores is sent here, the data word with the capable size equal number of Cache is read from primary memory, data encoder data word is sent to generate BCH check code successively, data word and check code are write together in data-carrier store, writing position is determined according to Cache replacement policy and Cache index; Then corresponding address mark is produced according to storage address, tag encoder address mark and row effective marker is sent to generate the BCH check code of marker word together, the check code of address mark, row effective marker and generation is write mark memory relevant position together, writing position is determined according to Cache replacement policy and Cache index, completes the renewal that Cache is capable; Meanwhile, according to Cache access strategy, by data word corresponding for storage address through data decoder, data selector sending processor kernel, terminate the operation to Cache.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182125A (en) * | 2017-12-27 | 2018-06-19 | 武汉理工大学 | The detection of cache multidigit hard error and fault tolerance facility and method under nearly threshold voltage |
| CN108897701A (en) * | 2018-06-20 | 2018-11-27 | 珠海市杰理科技股份有限公司 | Cache storage architecture |
| CN112181712A (en) * | 2020-09-28 | 2021-01-05 | 中国人民解放军国防科技大学 | Method and device for improving reliability of processor core |
| WO2022143690A1 (en) * | 2020-12-31 | 2022-07-07 | 华为技术有限公司 | Coding method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980339A (en) * | 2010-11-04 | 2011-02-23 | 浙江大学 | Error correction encoding method for dynamic random access memory (DRAM) buffer |
| CN102545914A (en) * | 2010-12-27 | 2012-07-04 | 联芯科技有限公司 | BCH (Broadcast Channel) encoding and decoding method and device |
| US20130262957A1 (en) * | 2012-03-30 | 2013-10-03 | Wei Wu | Method Of Correcting Adjacent Errors By Using BCH-Based Error Correction Coding |
| CN204833244U (en) * | 2015-08-19 | 2015-12-02 | 首都师范大学 | Embedded microprocessor cache 4 figure place is according to wrong correction device of upset |
-
2015
- 2015-08-19 CN CN201510508446.XA patent/CN105022675B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980339A (en) * | 2010-11-04 | 2011-02-23 | 浙江大学 | Error correction encoding method for dynamic random access memory (DRAM) buffer |
| CN102545914A (en) * | 2010-12-27 | 2012-07-04 | 联芯科技有限公司 | BCH (Broadcast Channel) encoding and decoding method and device |
| US20130262957A1 (en) * | 2012-03-30 | 2013-10-03 | Wei Wu | Method Of Correcting Adjacent Errors By Using BCH-Based Error Correction Coding |
| CN204833244U (en) * | 2015-08-19 | 2015-12-02 | 首都师范大学 | Embedded microprocessor cache 4 figure place is according to wrong correction device of upset |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182125A (en) * | 2017-12-27 | 2018-06-19 | 武汉理工大学 | The detection of cache multidigit hard error and fault tolerance facility and method under nearly threshold voltage |
| CN108182125B (en) * | 2017-12-27 | 2021-05-18 | 武汉理工大学 | Apparatus and method for detecting and fault-tolerant multi-bit hard errors of cache memory under near threshold voltage |
| CN108897701A (en) * | 2018-06-20 | 2018-11-27 | 珠海市杰理科技股份有限公司 | Cache storage architecture |
| CN108897701B (en) * | 2018-06-20 | 2020-07-14 | 珠海市杰理科技股份有限公司 | cache storage device |
| CN112181712A (en) * | 2020-09-28 | 2021-01-05 | 中国人民解放军国防科技大学 | Method and device for improving reliability of processor core |
| CN112181712B (en) * | 2020-09-28 | 2022-02-22 | 中国人民解放军国防科技大学 | Method and device for improving reliability of processor core |
| WO2022143690A1 (en) * | 2020-12-31 | 2022-07-07 | 华为技术有限公司 | Coding method and device |
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| CN105022675B (en) | 2017-12-08 |
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