CN112181709A - RAM storage area single event effect fault tolerance method of FPGA chip - Google Patents
RAM storage area single event effect fault tolerance method of FPGA chip Download PDFInfo
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
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Abstract
The invention discloses a single event effect fault-tolerant method for an RAM storage area of an FPGA chip, which realizes single event effect error detection of any bit of a full storage area by a compressed redundancy mode, carries out check code calculation on data of unit length based on a pipeline mode, and completes check code generation and comparison in a single clock cycle so as to achieve the aims of quick error detection and immediate error correction of the data. The method disclosed by the invention has the advantages of less consumed hardware resources and higher real-time performance, is suitable for error recovery of FPGA chip storage area data, and can improve the design reliability, thereby ensuring the operation performance and reliability of the power secondary equipment system.
Description
Technical Field
The invention relates to an integrated chip single event effect on-line error detection and correction method, in particular to a single event effect fault-tolerant method for a RAM storage area of an FPGA chip.
Background
With the comprehensive promotion of intelligent power grid construction, an integrated chip is adopted in a substation secondary device in a large scale, wherein a programmable logic gate array (FPGA chip) is taken as one of representatives, and the integrated chip has a series of advantages of heavy load, expansion flexibility, parallel high processing performance and the like and is widely applied.
However, compared to the conventional analog circuit, the FPGA chip applied to the secondary device of the power system is generally an FPGA chip applied in a large scale based on the SRAM process based on the requirements of cost, area and configurability. Because the SRAM type FPGA chip adopts the storage technology of the static RAM to store the configuration data information, the working voltage is lower, and the interference of space electromagnetic signals is easier. Although the ground environment in which the power secondary device operates has a protective environment of the earth magnetic field and the atmosphere with respect to the space environment, the particle radiation level is relatively low, but a small amount of radiation particles can still penetrate the earth magnetic field and the atmosphere, thereby affecting the integrated circuit in the power secondary device. Single event effects can cause transients in circuit node voltages and transients in current flow through the nodes, causing temporary or permanent changes in the stored data bits in an SRAM type FPGA chip.
And complicated calculation and logic processing are decomposed into a plurality of interface function circuit modules by utilizing the real-time performance and concurrency of the FPGA chip circuit work and an internal ultra-large-scale programmable logic module (CLB), so that protocol conversion among all buses is realized in sequence, and data sharing is realized. In addition, for the control or preprocessing algorithm with a large number of real-time data paths and a simple realization principle but a large calculation amount, when a plurality of machines are occupied by processing in a general processor, the control or preprocessing algorithm cannot meet the control frequency requirements of a direct current control protection system and the like with the highest 100 KHz. The parallel characteristic of the FPGA chip can process multi-path data in parallel, and the design modes such as a production line are adopted, so that extra computing power can be provided for a general processor, the CPU design is simplified, and the CPU design is more focused on the realization of a complex algorithm. Therefore, one of the main functions of the FPGA chip in the power secondary equipment is realized by an applied extended communication interface or algorithm.
The implementation basis of the above functions depends on a large amount of real-time data storage, and therefore, the real-time data storage quality is closely related to the system reliability. The storage data in the FPGA chip of the power secondary equipment is changed, so that important SV and GOOSE communication data are wrong or even lost, and the control algorithm calculation result is abnormal, so that misoperation and other serious consequences are caused. In particular, recent research finds that a storage region in an integrated chip is one of the most susceptible parts to a single event effect, so that it is necessary to carry out deep research on the technology of resisting the space radiation interference of the FPGA chip to improve the operation reliability of the FPGA chip.
Most researches on the single event effect error detection and correction method of the existing FPGA chip storage area are focused on aerospace application in a high-radiation environment, and error detection and correction of storage area data are generally carried out by adopting triple modular redundancy, ECC or a mode of adding EDAC codes in a data stream.
The thesis "design of embedded reinforcement system based on FPGA chip" performs triple modular redundancy design and (12,8) design reinforcement of EDAC coding of Hamming code on the memory cell. However, the triple modular redundancy mode has the problems of high hardware resource overhead and low resource utilization rate, and is not suitable for the field of power secondary equipment with higher requirements on cost and power consumption.
Patent CN201610939803.2 discloses that Hsiao code is used as error correction code to realize the coding and decoding operations of EDAC circuit, and realize the function of correcting one bit and two bits of data. However, the EDAC method using the encoding method needs to add an error correction code to the stored data, and the implementation principle is similar to the ECC method, and although the hardware resource consumption is low, the error detection and correction capability is general, and the interval time between the error detection and correction is long, and thus the EDAC method is not suitable for applications with high real-time performance requirements.
Patent CN201910305781.8 discloses a single event effect fault-tolerant method for dual port RAM modules. The method uses the second port as a refresh port, thereby operating independently from the user port and realizing real-time error detection and correction of data. However, the error detection and correction capability of the method is still low, and the application requirements of the dual-port independent clock and different rates cannot be met.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a single event effect fault-tolerant method for a RAM storage area of an FPGA chip, which has the advantages of being capable of achieving the purposes of rapid error detection and timely error correction of data, consuming less hardware resources, having higher real-time performance, being suitable for error recovery of the data in the storage area of the FPGA chip, improving the design reliability and further ensuring the operation performance and the reliability of a power secondary equipment system.
The technical scheme is as follows: the invention discloses a single event effect fault-tolerant method for an RAM storage area of an FPGA chip, which comprises the following steps:
(1) the storage write controller writes the real-time data into the first storage area; meanwhile, the storage write controller also processes real-time data in a compression redundancy mode, and writes the obtained compressed data and check codes into a second storage area and a third storage area respectively;
(2) after the storage reading controller sends a signal for reading data, the compressed data of the second storage area starts to be read, and decompression and data restoration are carried out on the compressed data;
(3) calculating check codes of unit length data in the decompressed and restored data;
(4) when the fixed decompression period T is reached, the storage and reading controller reads the real-time data of the first storage area; processing the real-time data of the first storage area and then generating a check code; meanwhile, the storage reading controller reads the check code stored in the third storage area;
(5) the data error detection module cross-verifies whether the real-time data of the first storage area is the decompressed and restored data of the second storage area, the check code generated by the first storage area is the check code stored in the third storage area, and the decompressed and restored data of the second storage area is the same as the check code stored in the third storage area, and outputs a comparison result;
(6) if the error detection information appears in the step (5), determining whether data recovery operation needs to be carried out through a data error recovery module after judging the writing state of the input end of the corresponding error storage area;
(7) and after the error data is recovered, the recovered data is checked and compared with the correct data, and the correctness of the data recovery is verified.
The storage write controller comprises a data write control module, a data compression module and a check code generation module, and the data write control module writes real-time data into a first storage area;
in the step (1), the data compression module compresses the real-time data to obtain compressed data, and the compressed data is sequentially written into the second storage area.
In the step (1), the data compression module compresses the real-time data by adopting a lossless compression algorithm to obtain compressed data.
In the step (1), the check code generation module performs check code calculation on the unit length data in the real-time data to generate check codes, and the check codes are sequentially written into the third storage area.
In the step (1), the check code generation module processes the data of unit length in the real-time data by adopting a cyclic redundancy check rule.
In the step (2), after the storage and reading controller sends out a signal for reading data, the reading address is firstly mapped to the second storage area to generate a reading control signal for reading the data in the second storage area, and then the compressed data in the second storage area is read.
In the step (6), judging the writing state of the input end of the corresponding error storage area according to the writing signal; if the storage area is in a busy state, the data is updated, and the data recovery operation is abandoned; if the storage area is in an idle state, judging whether the data has write operation according to whether a write signal is effective during data reading; if the write operation occurs, indicating that the data is updated, and abandoning the data recovery; if the write operation does not occur, the data error recovery module generates a write control signal, writes correct data according to the address provided by the error detection information, and recovers the error data of the corresponding error storage area.
In the step (7), after the error data is recovered, the data error recovery module generates a read control signal, reads the recovered data, and then compares the recovered data with the correct data.
Has the advantages that: compared with the prior art, the invention has the beneficial effects that: (1) hardware resources are reduced by one third compared with a triple modular redundancy mode, an error data recovery mechanism is provided, and a single-bit error accumulation effect which is easy to occur in a storage area is eliminated; (2) the error detection and correction can be carried out on any number of data affected by the single event effect, and the error detection and correction capability is strong; (3) the whole delay of the real-time data only depends on the decompression delay, and the real-time performance of the data is less influenced.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
FIG. 2 is a flow chart of data error detection and recovery in the present invention.
Detailed Description
The invention is described in further detail below with reference to specific embodiments and the attached drawings.
As shown in fig. 1, the FPGA chip in the power secondary device of the present invention includes a storage write controller, a storage area, a storage read controller, a data error detection module, and a data error recovery module. The storage write controller realizes real-time data write enable control and provides a write state, and comprises a data write control module, a data compression module and a check code generation module. The data writing control module provides a real-time data writing state output port and an error data recovery writing port, if the real-time data writing is enabled, a real-time data receiving request is initiated, and a writing control signal is generated; and if the error data recovers the write enable, performing data write operation of the fixed address according to the port address and the data. For the write status output port definition, it is defined as "idle" status when there is no write enable, otherwise it is "busy" status.
The storage area is divided into three parts of space according to the address space: the system comprises a first storage area, a second storage area and a third storage area, wherein the first storage area stores real-time data, the second storage area stores compressed data, and the third storage area stores check codes. The storage area is set as a double-port RAM, the address and data interface is connected to the data error recovery module, and the width of the address and data port is 64 bits.
The storage and reading controller mainly responds to a storage data real-time reading request and outputs a reading control signal and an address, and comprises a data reading control module, a data decompression module and a check code generation module, and provides real-time data, decompressed data and a check code to a data error detection module. And the data error detection module selects a data source and outputs correct data and error detection information after the read control signal is effective. The error detection information includes a data status and an error data address. The data error recovery module performs error data recovery when the storage area is idle by judging the writing state, and the writing performance of the storage area is not influenced.
As shown in fig. 1 and 2, the method for single event effect fault tolerance of the RAM storage area of the FPGA chip of the present invention specifically includes the following steps:
(1) a data writing control module in the storage writing controller writes real-time data into a first storage area; meanwhile, a data compression module in the storage writing controller adopts an RLE (run Length encoding) lossless compression algorithm to compress the real-time data to obtain compressed data, and the compressed data are sequentially written into a second storage area; the check code generation module adopts a CRC-8 cyclic redundancy check rule to perform check code calculation on data of unit length in the real-time data to generate check codes, and the check codes are sequentially written into a third storage area; the steps adopt parallel operation, in the embodiment, the length of the unit-length data is the bit width of a data port of the data reading controller, and a check code of 1 byte is generated for 64-bit-width data;
(2) after the storage and reading controller sends a signal for reading data, firstly mapping a reading address to a second storage area, generating a reading control signal for reading the data in the second storage area, starting to read the compressed data in the second storage area, and decompressing and restoring the compressed data according to a lossless compression algorithm;
(3) the check code generation module adopts a CRC-8 cyclic redundancy check rule for the decompressed and restored data and generates a check code of 1 byte for the data with the length being the bit width of the data reading port;
(4) when the fixed 64 clock decompression periods T are reached, the storage and reading controller maps the reading address to the first data area, generates a first data area reading control signal and controls the reading of real-time data of the first data area; generating a check code of 1 byte for the 64-bit wide data by adopting a CRC-8 cyclic redundancy check rule for the real-time data of the first storage area; meanwhile, the storage and reading controller maps the reading address to a third data area and reads the check code stored in the third storage area;
(5) the data error detection module cross-verifies whether the real-time data of the first storage area is the decompressed and restored data of the second storage area, the check code generated by the first storage area is the same as the check code stored in the third storage area, and the decompressed and restored data of the second storage area is the same as the check code stored in the third storage area, and outputs a comparison result, wherein 0 is output identically, and 1 is output if the two are different; and then data and state output is carried out according to the following judgment formula:
(6) if the error detection information appears in the step (5), judging the writing state of the input end of the corresponding error storage area according to the writing signal; if the storage area is in a busy state, the data is updated, and the data recovery operation is abandoned; if the storage area is in an idle state, judging whether the data has write operation according to whether a write signal is effective during data reading;
if the write operation occurs, indicating that the data is updated, and abandoning the data recovery; if the write operation does not occur, the data error recovery module generates a write control signal, writes correct data according to the address provided by the error detection information, and recovers the error data of the corresponding error storage area;
(7) after the error data is recovered, the data error recovery module generates a read control signal, reads the recovered data, compares the recovered data with the correct data, and verifies the correctness of the data recovery.
The invention can be applied to an intelligent bus relay protection device. The intelligent bus relay protection device is designed in a plug-in mode and comprises a power supply board card, a CPU board card, an SV board card, a GOOSE board card and an input/output board card. The CPU board card realizes the realization of a relay protection algorithm and outputs a protection action signal, the control frequency is 1.2KHz, and the system clock is 125 MHz. The CPU board card adopts a structure of 'CPU + FPGA chip'. The FPGA chip is an Xilinx FPGA chip of a certain model, the CPU and the FPGA chip communicate with each other through an AXI high-speed bus, and the protection application is realized in the CPU general processor. The FPGA chip mainly realizes a time synchronization and time keeping module based on an external time synchronization signal, and a 3-path SV, GOOSE and MMS three-in-one real-time communication Ethernet module which is used as an output expansion input and output module of a trip signal. The storage area RAM is mainly used by Ethernet communication modules such as SV and GOOSE, and the delay requirement of the data of the link layer is not more than 1 us. The Ethernet sets the cache depth to be 32kB, 6 buffer areas, 2kB in a single buffer area is a main storage area, 2kB is a compressed data storage area, and 1kB is a check code storage area.
Claims (9)
1. A single event effect fault-tolerant method for a RAM storage area of an FPGA chip is characterized by comprising the following steps:
(1) the storage write controller writes the real-time data into the first storage area; meanwhile, the storage write controller also processes real-time data in a compression redundancy mode, and writes the obtained compressed data and check codes into a second storage area and a third storage area respectively;
(2) after the storage reading controller sends a signal for reading data, the compressed data of the second storage area starts to be read, and decompression and data restoration are carried out on the compressed data;
(3) calculating check codes of unit length data in the decompressed and restored data;
(4) when the fixed decompression period T is reached, the storage and reading controller reads the real-time data of the first storage area; processing the real-time data of the first storage area and then generating a check code; meanwhile, the storage reading controller reads the check code stored in the third storage area;
(5) the data error detection module cross-verifies whether the real-time data of the first storage area is the decompressed and restored data of the second storage area, the check code generated by the first storage area is the check code stored in the third storage area, and the decompressed and restored data of the second storage area is the same as the check code stored in the third storage area, and outputs a comparison result;
(6) if the error detection information appears in the step (5), determining whether data recovery operation needs to be carried out through a data error recovery module after judging the writing state of the input end of the corresponding error storage area;
(7) and after the error data is recovered, the recovered data is checked and compared with the correct data, and the correctness of the data recovery is verified.
2. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip according to claim 1, characterized in that: the storage writing controller comprises a data writing control module, a data compression module and a check code generation module, and the data writing control module writes real-time data into the first storage area.
3. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip as recited in claim 2, wherein: in the step (1), the data compression module compresses the real-time data to obtain compressed data, and the compressed data is sequentially written into the second storage area.
4. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip according to claim 3, characterized in that: in the step (1), the data compression module compresses the real-time data by adopting a lossless compression algorithm to obtain compressed data.
5. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip as recited in claim 2, wherein: in the step (1), the check code generation module performs check code calculation on the unit length data in the real-time data to generate check codes, and the check codes are sequentially written into the third storage area.
6. The RAM storage area single event effect fault-tolerant method of the FPGA chip according to claim 5, characterized in that: in the step (1), the check code generation module processes the data of unit length in the real-time data by adopting a cyclic redundancy check rule.
7. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip according to claim 1, characterized in that: in the step (2), after the storage and reading controller sends out a signal for reading data, the reading address is firstly mapped to the second storage area to generate a reading control signal for reading the data in the second storage area, and then the compressed data in the second storage area is read.
8. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip according to claim 1, characterized in that: in the step (6), judging the writing state of the input end of the corresponding error storage area according to the writing signal; if the storage area is in a busy state, the data is updated, and the data recovery operation is abandoned; if the storage area is in an idle state, judging whether the data has write operation according to whether a write signal is effective during data reading; if the write operation occurs, indicating that the data is updated, and abandoning the data recovery; if the write operation does not occur, the data error recovery module generates a write control signal, writes correct data according to the address provided by the error detection information, and recovers the error data of the corresponding error storage area.
9. The single event effect fault-tolerant method for the RAM storage area of the FPGA chip according to claim 1, characterized in that: in the step (7), after the error data is recovered, the data error recovery module generates a read control signal, reads the recovered data, and then compares the recovered data with the correct data.
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