CN114880163A - ECC use method based on novel memory internal calculation - Google Patents
ECC use method based on novel memory internal calculation Download PDFInfo
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- CN114880163A CN114880163A CN202210633894.2A CN202210633894A CN114880163A CN 114880163 A CN114880163 A CN 114880163A CN 202210633894 A CN202210633894 A CN 202210633894A CN 114880163 A CN114880163 A CN 114880163A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000013461 design Methods 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 claims abstract description 6
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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Abstract
The invention relates to the technical field of computers, and discloses an ECC (error correction code) using method based on novel memory internal calculation, which comprises the following working steps of: the first step is as follows: storing the data; the second step is that: the data enters an ECC encoder for encoding, and enters a memory for calculation processing after being encoded; the third step: after calculation processing, entering an ECC decoder for decoding; the fourth step: and (6) reading data. Compared with the existing memory computing mode, the ECC using method based on the novel memory computing verifies the computing result by using the existing ECC coding for memory reading and writing, so that the memory computing based on the novel memory has higher reliability, and the ECC coding is not required to be carried out independently for computing due to multiplexing of the existing reading and writing ECC coding, thereby greatly saving the design consumption.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an ECC (error correction code) using method based on novel memory internal calculation.
Background
The existing new memory has the problem of reliability, and even if the memory is used as the memory, a certain error rate can occur. As an in-memory/near-memory calculation, adding the values of multiple bitcells results in a higher error rate. The conventional new memory is used as a memory only, and an ecc (error correction code) is used to solve a partial error problem. However, there is no way to use ECC as memory directly in memory calculation, and if ECC is performed for memory/near memory calculation alone, it is not practical because it needs to have both stored ECC and calculated ECC in storage, and a very large proportion of design area is consumed.
To this end, we propose ECC usage methods based on novel memory computations.
Disclosure of Invention
The invention mainly solves the technical problems in the prior art and provides an ECC use method based on novel memory internal calculation.
In order to achieve the purpose, the invention adopts the following technical scheme, and the ECC using method based on the novel memory calculation comprises the following working steps:
the first step is as follows: storing the data;
the second step is that: the data enters an ECC encoder for encoding, and enters a memory for calculation processing after being encoded;
the third step: after calculation processing, entering an ECC decoder for decoding;
the fourth step: and (6) reading data.
Preferably, the second step uses 8 bits or 16 bits or more as a unit according to the number of bits to be calculated, and performs ECC encoding based on the unit, and since the encoding mode depends on the length of the bits, a certain amount of extra ECC data is generated, but the encoder and the decoder do not consume extra design.
Preferably, in the calculation, the calculation is performed using input data of 1bit each time and data in the memory, and the operation of the calculation is performed simultaneously on the original data and the ECC data.
Preferably, when the and 1 operation (i.e., X1) is performed, the original data and the ECC data are kept unchanged, and the calculation result data can be obtained directly by the decoder.
Preferably, when the and operation is performed with 0 (i.e., X0), the output raw data and the ECC computation result are both 0, and the decoder can be used to obtain an output of 0.
Preferably, any in-memory or near-memory calculation that takes the calculation input in units of 1bit can be used in such a way as to obtain an ECC-checked calculation result.
Advantageous effects
The invention provides an ECC use method based on novel memory calculation. The method has the following beneficial effects:
(1) compared with the existing memory computing mode, the ECC using method based on the novel memory computing verifies the computing result by using the existing ECC coding for memory reading and writing, so that the memory computing based on the novel memory has higher reliability, and the ECC coding alone does not need to be carried out for computing due to multiplexing of the existing reading and writing ECC coding, thereby greatly saving the design consumption.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions that the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the effects and the achievable by the present invention, should still fall within the range that the technical contents disclosed in the present invention can cover.
FIG. 1 is a schematic diagram of the memory of the present invention for internally performing a vector-matrix multiplication operation;
FIG. 2 is a diagram illustrating ECC usage for read and write operations of a conventional memory;
FIG. 3 is a flowchart illustrating ECC usage and calculation within a memory according to the present invention;
FIG. 4 is a diagram illustrating an example of the memory internal calculation for storing ECC functions according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
ECC use method based on novel memory calculation, novel memory such as MRAM, RRA M have the advantages such as large capacity, non-memory loss. These advantages make it well suited for use in memory/near memory computing systems where a vector-by-matrix multiplication is performed within the memory by storing the relationship between voltage and current at the value, as shown in figure 1.
The conventional ECC usage for memory read and write is shown in fig. 2, and the conventional ECC usage for memory read and write is shown in the figure, and when data is stored, an ECC code is generated by an encoder, and then when data is read again, correct data can be restored by decoding the data and the ECC code.
Based on the prior art, fig. 3 shows how to utilize the original ECC to solve the problem of calculating the required ECC. The original data are still coded into original data + ECC data, but according to the bit number required to be calculated, data with 8 bits, 16 bits or more are taken as a unit, ECC coding is carried out based on the unit, and because the coding mode depends on the bit length, a certain amount of additional ECC data exist, but the coder and the decoder do not have additional design consumption.
In the calculation, the calculation is performed using the input data of 1bit each time and the data inside the memory, and the operation of the calculation is performed simultaneously on the original data and the ECC data. Taking fig. 4 as an example, when the and 1 (i.e., X1) operation is performed, the original data and the ECC data are kept unchanged, and the calculation result data can be obtained by the decoder directly. When the and 0 operation is performed (i.e., X0), both the output raw data and the ECC calculation result are 0. An output of 0 can be obtained by passing through the decoder as well. Any in-memory or near-memory calculation that performs calculation input in units of 1bit can be used in such a manner to obtain a calculation result that is ECC-checked.
The design is mainly an in-memory/near memory computing design using a novel memory, and the computed reliability problem is solved by using the ECC of the existing memory part without adding an additional ECC of an independent computing part.
Compared with the existing memory computing mode, the memory computing method has the advantages that the existing ECC coding for memory reading and writing is used, the computing result is verified, the memory computing based on the novel memory has higher reliability, and due to the fact that the existing reading and writing ECC coding is multiplexed, independent ECC coding is not needed for computing, and design consumption is greatly reduced.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (6)
1. ECC use method based on novel memory calculation is characterized in that: the method comprises the following working steps:
the first step is as follows: storing the data;
the second step is that: the data enters an ECC encoder for encoding, and enters a memory for calculation processing after being encoded;
the third step: after calculation processing, entering an ECC decoder for decoding;
the fourth step: and (6) reading data.
2. The ECC usage method based on new memory in-memory computation of claim 1, wherein: and in the second step, according to the bit number required to be calculated, 8 bits or 16 bits or more of data are taken as a unit, ECC coding is carried out based on the unit, and because the coding mode depends on the length of the bit number, a certain amount of extra ECC data exists, but the coder and the decoder do not have extra design consumption.
3. The ECC usage method based on new memory in-memory computation of claim 1, wherein: in the calculation, the calculation is performed using the input data of 1bit each time and the data inside the memory, and the operation of the calculation is performed simultaneously on the original data and the ECC data.
4. The ECC usage method based on new memory in-memory computation of claim 3, wherein: when the and 1 operation is performed (i.e., X1), the original data and the ECC data are kept unchanged, and the calculation result data can be obtained by directly passing through the decoder.
5. The ECC usage method based on new memory in-memory computation of claim 3, wherein: when the and 0 operation is performed (i.e., X0), the output raw data and the ECC computation result are both 0, and can be passed through the decoder to obtain an output of 0.
6. The ECC usage method based on new memory in-memory computation of claim 5, wherein: any in-memory or near-memory calculation that performs calculation input in units of 1bit can be used in such a manner to obtain a calculation result that is ECC-checked.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116244108A (en) * | 2023-01-09 | 2023-06-09 | 海光信息技术股份有限公司 | Memory controller, data writing and reading method of memory and memory system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116244108A (en) * | 2023-01-09 | 2023-06-09 | 海光信息技术股份有限公司 | Memory controller, data writing and reading method of memory and memory system |
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