CN113076219B - High-energy-efficiency on-chip memory error detection and correction circuit and implementation method - Google Patents
High-energy-efficiency on-chip memory error detection and correction circuit and implementation method Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
An energy-efficient on-chip memory error detection and correction circuit and an implementation method thereof comprise: the ECC coding selection and generation module is used for determining whether ECC coding is carried out according to information in a memory access request sent by the memory access operation, carrying out ECC coding on the ECC coding effective bit of the memory access data and sending the memory access information and a related ECC coding result to a subsequent memory access decoding module; the access decoding module is used for carrying out access decoding to generate an access port signal of the redundant data memory; the read data decoding and error correcting module is used for carrying out error detection and error correction on the ECC code; and the read data selection module is used for selecting read data according to the access address and the access granularity information sent along the access pipeline. The implementation method is used for the implementation of the circuit. The invention has the advantages of obviously reducing the area of the on-chip memory and the realization area of the ECC circuit, effectively reducing the overall power consumption of the microprocessor and the like.
Description
Technical Field
The invention mainly relates to the field of micro-system structures of microprocessors, in particular to an Error Checking and Correcting (ECC) circuit of an on-chip memory in a microprocessor and an implementation method thereof.
Background
The on-chip memory is an important component of a microprocessor, and efficient and reliable data access is a key factor for determining the normal operation of the microprocessor. On one hand, with the continuous reduction of the semiconductor process size, the integration density of chip transistors is continuously increased, the distance between semiconductor memory units is reduced along with the continuous increase of the density of the memory units, the memory units are more easily affected by environmental interference and space radiation particles to be overturned, and the probability of the operation error of the whole chip is greatly increased due to the soft error caused by a single-particle overturning event, so that the modern microprocessor development has to carry out ECC-based reliability design on an on-chip memory. On the other hand, with the development of microprocessor architecture and application requirements, the area of the on-chip memory of the microprocessor is continuously increased, the on-chip memory of the high-performance microprocessor usually occupies more than 60% of the whole chip area, and when the on-chip memory reliability design based on the ECC is performed, the realization cost of the ECC must be comprehensively considered while the design performance of the microprocessor is not affected, so that the hardware realization area of the memory is reduced, and the overall power consumption of the microprocessor is reduced.
The on-chip memory generally adopts a static random access memory, and the data writing and reading processes are similar to the typical data transmission process, so that random errors of data access are easily generated. The error control strategy aiming at the single event upset of the static random access memory adopts forward error correction, namely, the error correction code is utilized to realize automatic error detection and correction during the reading of the data of the memory. Because linear block code encoding and decoding algorithms are mature, hardware implementation is easy, and normal data access performance is not affected, the ECC design of the current on-chip memory aiming at single-event upset error is usually realized by adopting an error correction coding technology based on linear block codes, and the commonly used linear block codes comprise Hamming codes, Hsiao codes, cyclic codes and the like. Because the general high-performance microprocessor data access is compatible upwards or is interconnected and communicated with other microprocessors with different word widths, various access granularities are often supported, and the sizes of the data access granularities are usually in integral multiple relation, for example, a general CPU supports the data access granularities of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits and the like. If ECC reliability design is implemented for minimum access granularity, although hardware circuits are easy to implement, the following problems can exist:
(1) the coding efficiency is low, the redundancy of hardware is increased, and particularly, the error correcting code needs larger redundant storage capacity.
For example, five data access granularities of 8 bits, 16 bits, 32 bits, 64 bits and 128 bits exist in a certain microprocessor, if Hsiao code-based one-to-two-correction ECC is implemented for the 8-bit data access granularity, each 8-bit data needs 5-bit error correction check codes, namely (13,8) one-to-two-correction ECC encoding, and an on-chip memory needs 5/8 redundant storage capacity storage error correction encoding with the original capacity increased; i.e. if the user requires an on-chip memory data capacity of 32 KB; when the one-to-two ECC reliability design of (13,8) is implemented, a redundant memory space of 20KB needs to be added to store error correction codes, and the total design capacity of the on-chip memory is 52 KB. If the Hsiao code-based one-to-two ECC is realized aiming at the 64-bit data access granularity, each 64-bit data needs 8-bit error correction check codes, namely (72,64) one-to-two ECC coding, and the on-chip memory only needs 1/8 redundant storage capacity for increasing the original capacity to store the error correction codes; the total design capacity of the on-chip memory only needs 36KB of 32KB +4 KB;
(2) in order to support the maximum data access granularity bandwidth, hardware needs a larger number of small-granularity error correction code encoding and decoding circuit modules.
Taking the microprocessor as an example, if one-to-two ECC based on Hsiao code is implemented for 8-bit data access granularity, 16 ECC encoding modules and 16 ECC decoding modules (13 and 8) are needed because the maximum data access granularity is 128 bits; assuming that the microprocessor is a 64-bit microprocessor and mainly faces 64-bit high-performance calculation, if the Hsiao code-based (72,64) one-to-two ECC is selected to be implemented according to the 64-bit data access granularity, only 2 encoding modules and 2 decoding modules of (72,64) error correction codes are needed respectively.
Therefore, the large increase of the memory area and the ECC encoding and decoding module can significantly increase the area and power consumption of the microprocessor.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the energy-efficient on-chip memory error detection and correction circuit and the implementation method thereof, wherein the energy-efficient on-chip memory error detection and correction circuit can obviously reduce the area of an on-chip memory and the implementation area of an ECC circuit, and effectively reduce the overall power consumption of a microprocessor.
In order to solve the technical problem, the invention adopts the following technical scheme:
an energy-efficient on-chip memory error detection and correction circuit comprises the following components according to the memory access process:
the ECC coding selection and generation module is used for determining whether to carry out ECC coding according to information in a memory access request sent by memory access operation, carrying out ECC coding on the effective ECC coding bit of memory access data and sending the memory access information and a related ECC coding result to a subsequent memory access decoding module;
the memory access decoding module is used for performing memory access decoding according to a read-write request and a memory access address to generate a memory access port signal of the redundant data memory;
the read data decoding and error correcting module is used for carrying out error detection and error correction on the read access data ECC coding effective bit ECC coding;
and the read data selection module is used for selecting read data according to the access address and the access granularity information sent along the access pipeline.
As a further improvement of the circuit of the invention: when the memory access instruction carries out the memory access operation of the on-chip memory, whether ECC coding is carried out or not is determined according to a read request, a write request, write data, data memory access granularity and a memory access address in a memory access request sent by the memory access operation.
As a further improvement of the circuit of the invention: if the access request is a write request and the access granularity of the write data is greater than or equal to the data access granularity n determined at the beginning, performing ECC coding on the write data and setting all the bits of the ECC coding valid bit of the access data as valid; and for the write requests with the data access granularity smaller than the data access granularity n, the ECC encoding operation is not carried out on the write data, and the ECC encoding valid positions of the access data are all set to be invalid.
As a further improvement of the circuit of the invention: if the access decoding module is a write request, generating write mask codes according to the write data granularity, and if the access decoding module is a write request with the access granularity not less than n, generating corresponding write mask codes and opening all the write mask codes, namely setting the write mask codes to be in a state of allowing the corresponding storage unit to write; if the access granularity is less than n, the generated write mask code needs to mask the data bits which are not written and the writing of the corresponding ECC coding bits; writing the write data, the ECC coding effective bit and the ECC coding of the write data into a storage unit corresponding to the memory access address according to the mask code; if the memory access address is a read request, all the data, ECC code and memory access data ECC code valid bits of the memory unit corresponding to the memory access address are read out and sent to a read data decoding and error correcting module.
As a further improvement of the circuit of the invention: in the read data decoding and error correcting module, the decoding and error correcting method of the ECC coding effective bit of the 3-bit access data is used for error detection and error correction according to a few majority-obeying judgment principles: that is, if only two values in the 3-bit effective value are the same, the memory access data ECC coding effective value is selected and 1-bit information is reported, and if the 3-bit effective value is the same, no error is reported and no error is corrected.
As a further improvement of the circuit of the invention: the redundant data storage logically comprises three parts per memory cell domain: the ECC coding method comprises the steps of ECC coding, data with the same bit width as the data access granularity corresponding to the ECC coding, wherein the three parts are placed in each storage unit without limitation.
The invention further provides a method for realizing the high-energy-efficiency on-chip memory error detection and correction circuit, which comprises the following steps:
step S1: determining a coding and decoding circuit module of an error correcting code;
step S2: the method comprises the steps that an error correction code encoding and decoding function is embedded into an access pipeline of an on-chip memory, and the error correction code encoding and decoding of access data in the ECC function and the ECC encoding and decoding of the ECC encoding effective bits of the access data are simultaneously realized in the access process, namely, the error detection and error correction are carried out on the access data and the error correction code effective bits;
step S3: when the on-chip memory is accessed for writing, the ECC (error correction code) coding of writing data and the ECC coding of the effective bit of the error correction code are simultaneously carried out according to the access granularity access information;
step S4: ECC error correction of the ECC coding valid bit of the access data;
step S5: when reading and accessing the memory of the on-chip memory, firstly, carrying out error detection and correction on the read 3-bit memory access data ECC coding effective bit; then, ECC decoding and error correction are performed on the read data according to whether the valid bit is valid.
As a further improvement of the implementation method of the invention: in step S3, if the granularity of the access data is not less than n, the ECC coding valid bit of the access data is set to be valid, and the ECC coding valid bit of the access data and the ECC coding of the access data are simultaneously implemented; and if the granularity of the access data is less than n, not carrying out the ECC coding of the access data, setting the ECC coding valid bit of the access data to be invalid, and carrying out the ECC coding valid bit coding of the access data.
As a further improvement of the implementation method of the invention: in step S4, when ECC error correction of the ECC encoding valid bit of the access data is performed, redundant storage and a few error detection and correction modes subject to majority decision are adopted, that is, a logical value of one ECC encoding valid bit is stored in triplicate, that is, 3 access units are written simultaneously to implement error correction code encoding of the ECC encoding valid bit; during the memory access, memory related access signals are generated according to the data access granularity and the access address, and the data of the memory access, the corresponding ECC code and the effective ECC code with the same 3 bits are written into the corresponding position of the on-chip memory corresponding to the target address.
As a further improvement of the implementation method of the invention: in step S5, if the logic values of the read 3-bit access data ECC encoding valid bits are completely the same, the access data ECC encoding valid bit does not report an error and does not correct an error; if the data are different, the ECC coding effective bit of the access data reports errors, and two same values in the 3 read values are selected to finish error correction; after completing the error detection and correction of the ECC coding effective bit of the access data, performing ECC decoding and error correction on the read data according to whether the effective bit is effective or not, if the ECC coding effective bit of the access data after error detection and error correction is effective, performing ECC decoding and error correction on the read data, and selecting the access data according to the access granularity and the access address; if the ECC coding effective bit of the access data is invalid, the access data is read out without error correction code decoding and data error correction, and the access data is selected from the read data directly according to the access granularity and the access address.
Compared with the prior art, the invention has the advantages that:
1. the invention relates to a high-energy-efficiency on-chip memory error detection and correction circuit and an implementation method thereof, which mainly aim at an on-chip memory of a microprocessor which supports various memory access granularities and has the size of different data memory access granularities in integral multiple relation. The invention determines and selects an ECC scheme according to the commonly used larger data access granularity n in microprocessor application, embeds the determined error correction code coding and decoding module circuit into the access pipeline of an on-chip memory, simultaneously performs the reliability design of the access data and the data ECC coding effectiveness, and performs selective ECC coding according to the access granularity and other information: on the basis of carrying out redundant storage on the ECC coding effective bit of the access data, carrying out ECC coding on write requests with the data access granularity not less than n and not carrying out ECC coding on the write requests with the data access granularity less than n, generating a write mask code, and writing the write data, the ECC coding and the ECC coding effective bit of the access data into a redundant data memory together according to the write mask code; for the read request, the read access data ECC coding effective bit is subjected to error detection and error correction by adopting a minority-majority-compliant judgment method, and then the read data ECC coding is subjected to selective decoding and error correction according to the result.
2. The high-energy-efficiency on-chip memory error detection and correction circuit and the implementation method not only can effectively support the ECC function of a microprocessor application with frequently used larger data access granularity, but also have a certain error detection and correction function on small-granularity data access; the redundant data used for the error correcting code is small in storage space, and the advantage of high coding efficiency is achieved; the number of ECC encoding and decoding circuit modules is obviously less than that of ECC encoding and decoding circuit modules required for supporting small-granularity data access; the method can obviously reduce the area of the on-chip memory and the realization area of an ECC circuit, effectively reduce the overall power consumption of the microprocessor, is a high-energy-efficiency ECC design method for the on-chip memory of the microprocessor, and can be widely applied to ECC reliability design of various on-chip memories in the microprocessor.
3. The invention relates to an error detection and correction circuit of an on-chip memory with high energy efficiency and a realization method thereof, which is oriented to a microprocessor with various access and storage granularities and different data access and storage granularities in integral multiple relation, aims at the problem of larger hardware redundancy in the design of an ECC circuit which is adopted by the on-chip memory and supports the minimum data access and storage granularity, and determines an ECC (error correction code) for a larger data access and storage granularity commonly used in the application of the microprocessor, in the memory access process, selective coding, decoding and error correction are carried out according to the memory access granularity and ECC coding effectiveness, so that not only can the ECC function of main data memory access granularity which is not less than the data memory access granularity be supported with lower hardware overhead, but also other partial ECC functions of smaller data memory access granularity can be supported in a limited manner under certain conditions, and the area and power consumption of ECC reliability design of an on-chip memory are obviously reduced.
Drawings
FIG. 1 is a schematic diagram of a circuit topology in a specific application example of the present invention.
FIG. 2 is a schematic diagram showing the domain composition of each memory cell of the redundant data storage in a specific application example of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
As shown in FIG. 1, the energy-efficient on-chip memory error detection and correction circuit of the present invention comprises, according to the memory access process:
the ECC coding selection and generation module is used for determining whether to carry out ECC coding according to information in a memory access request sent by memory access operation, carrying out ECC coding on the effective ECC coding bit of memory access data and sending the memory access information and a related ECC coding result to a subsequent memory access decoding module;
the memory access decoding module is used for performing memory access decoding according to a read-write request and a memory access address to generate a memory access port signal of the redundant data memory;
the read data decoding and error correcting module is used for carrying out error detection and error correction on the read access data ECC coding effective bit ECC coding;
and the read data selection module is used for selecting read data according to the access address and the access granularity information sent along the access pipeline.
In a specific application example, when the memory access instruction carries out memory access operation of an on-chip memory, whether ECC coding is carried out or not is determined according to a read request, a write request, write data, data memory access granularity and a memory access address in a memory access request sent by the memory access operation; if the memory access request is a write request and the data memory access granularity is greater than or equal to the data memory access granularity n determined at the beginning, performing ECC coding on write data and setting all the positions of the memory access data ECC coding valid bits to be valid; for the write requests with the data access granularity smaller than the data access granularity n, the ECC encoding operation is not carried out on the write data, and the ECC encoding valid positions of the access data are all set to be invalid; ECC encoding is carried out on the ECC encoding valid bit of the access data in both cases; and then the access information and the related ECC encoding result are sent to a following access decoding module.
In a specific application example, the memory access decoding module performs memory access decoding according to the read-write request and the memory access address to generate a memory access port signal of the redundant data memory. If the request is a write request, generating write mask codes according to the write data granularity, and if the request is a write request with the access granularity not less than n, generating corresponding write mask codes which are all opened, namely setting the write request in a state of allowing the corresponding storage unit to write; if the access granularity is less than n, the generated write mask code needs to mask the write-in of the unwritten data bit and the corresponding ECC coding bit; and then writing the write data, the ECC coding valid bit and the ECC coding of the write data into the memory cell corresponding to the memory access address according to the mask code. If the memory address is a read request, all the data, ECC code and memory data ECC code valid bits of the memory cell corresponding to the memory address are read out and sent to a read data decoding and error correcting module.
In a specific application example, the read data decoding and error correcting module firstly performs error detection and error correction on the read access data ECC coding valid bit ECC coding. Wherein, the decoding and error correction method of the 3-bit access data ECC coding effective bit ECC coding is used for error detection and error correction according to the majority decision principle: that is, if only two values in the 3-bit effective value are the same, the memory access data ECC coding effective value is selected and 1-bit information is reported, and if the 3-bit effective value is the same, no error is reported and no error is corrected.
In a specific application example, as shown in fig. 2, a composition example of each memory cell domain in the redundant data storage logic includes three parts: the three parts are put at each memory unit position without limitation, so that the bit width of each memory unit of the redundant data memory is m + n + 3.
The invention further provides a method for implementing the high-energy-efficiency on-chip memory error detection and correction circuit, which comprises the following steps:
step S1: determining a coding and decoding circuit module of an error correcting code;
namely, according to the larger data access granularity (assumed as n bits of a positive integer) which is most frequently used in the designed microprocessor application, selecting an error correcting code which determines the proper error correcting capability aiming at the data granularity n, thereby determining the encoding and decoding circuit module of the error correcting code;
step S2: the method comprises the steps that an error correction code encoding and decoding function is embedded into an access pipeline of an on-chip memory, and the error correction code encoding and decoding of access data in the ECC function and the ECC encoding and decoding of the ECC encoding effective bits of the access data are simultaneously realized in the access process, namely, the error detection and error correction are carried out on the access data and the error correction code effective bits;
step S3: when the memory access of the on-chip memory is carried out, the ECC coding of writing data and the ECC coding of the effective bit of the error correcting code are carried out simultaneously according to the memory access information such as the memory access granularity;
if the granularity of the access data is not less than n, firstly setting the ECC coding valid bit of the access data to be valid, and simultaneously realizing the ECC coding valid bit of the access data and the ECC coding of the access data; if the granularity of the access and memory data is less than n, the access and memory data ECC coding is not carried out, the effective bit of the access and memory data ECC coding is set to be invalid, and the access and memory data ECC coding effective bit coding is carried out;
step S4: ECC error correction of the ECC coding valid bit of the access data;
when the ECC of the ECC coding effective bit of the access data is corrected, a redundant storage mode and a few error detection and correction modes which obey majority judgment are directly adopted, namely, the logic value of one ECC coding effective bit is stored in three parts at the same time, namely 3 access units are written at the same time to realize the error correction coding of the ECC coding effective bit. During the memory access, memory related access signals are generated according to the data access granularity and the access address, and the data of the memory access, the corresponding ECC code and the effective ECC code with the same 3 bits are written into the corresponding position of the on-chip memory corresponding to the target address.
Step S5: when reading and accessing the memory of the on-chip memory, firstly, carrying out error detection and correction on the read 3-bit memory access data ECC coding effective bit; then, performing ECC decoding and error correction on the read data according to whether the valid bit is valid;
that is, if the logic values of the valid bits of the read 3-bit access data ECC coding are completely the same, the valid bits of the access data ECC coding do not report errors and correct errors; if the data are different, the ECC coding effective bit of the access data reports errors, and two same values in the 3 read values are selected to finish error correction; after completing the error detection and correction of the ECC coding effective bit of the access data, performing ECC decoding and error correction on the read data according to whether the effective bit is effective or not, if the ECC coding effective bit of the access data after error detection and error correction is effective, performing ECC decoding and error correction on the read data, and selecting the access data according to the access granularity and the access address; if the ECC coding effective bit of the access data is invalid, the access data is read out without error correction code decoding and data error correction, and the access data is directly selected from the read data according to the access granularity and the access address.
For a microprocessor with various access granularities and different data access granularities in integral multiple relation, in order to improve the access bandwidth efficiency and the overall computing performance of the microprocessor, most of the applications of the microprocessor use larger request access granularities, and the research also finds that the number of read requests in the application is usually far more than the number of write requests. Aiming at the characteristics of the microprocessor, the invention provides the ECC implementation method of the on-chip memory with high energy efficiency, which can directly support the main ECC function with larger data access granularity and can also support part of the ECC function with smaller access granularity in a limited way with obviously lower hardware cost, thereby improving the efficiency of an ECC circuit.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (8)
1. An energy-efficient on-chip memory error detection and correction circuit is characterized by comprising the following steps according to the memory access process:
the ECC coding selection and generation module is used for determining whether to carry out ECC coding according to information in a memory access request sent by memory access operation, carrying out ECC coding on an ECC coding effective bit of memory access data, and sending the memory access information and a related ECC coding result to a subsequent memory access decoding module; for the write requests with the data access granularity smaller than the data access granularity n, the ECC encoding operation is not carried out on the write data, and the ECC encoding valid positions of the access data are all set to be invalid;
the memory access decoding module is used for performing memory access decoding according to a read-write request and a memory access address to generate a memory access port signal of the redundant data memory;
the read data decoding and error correcting module is used for carrying out error detection and error correction on the read access data ECC coding effective bit ECC coding;
and the read data selection module is used for selecting read data according to the access address and the access granularity information sent along the access pipeline.
2. The energy-efficient on-chip memory error detection and correction circuit according to claim 1, wherein if the access decoding module is a write request, a write mask is generated according to a write data granularity, and if the access decoding module is a write request with an access granularity not less than n, the corresponding write mask is generated to be fully opened, that is, set to a state allowing the corresponding memory cell bit to be written in; if the access granularity is less than n, the generated write mask code needs to mask the data bits which are not written and the writing of the corresponding ECC coding bits; writing the write data, the ECC coding effective bit and the ECC coding of the write data into a storage unit corresponding to the memory access address according to the mask code; if the memory address is a read request, all the data, ECC code and memory data ECC code valid bits of the memory cell corresponding to the memory address are read out and sent to a read data decoding and error correcting module.
3. The energy efficient on-chip memory error detection and correction circuit of claim 1, wherein in said read data decoding and correction module, the 3-bit access data ECC encoding valid bit ECC encoding decoding and correction method performs error detection and correction according to a minority majority-compliant decision principle: that is, if only two values in the 3-bit effective value are the same, the memory access data ECC coding effective value is selected and 1-bit information is reported, and if the 3-bit effective value is the same, no error is reported and no error is corrected.
4. The energy efficient on-chip memory error detection and correction circuit of claim 1, wherein the redundant data memory logically comprises three portions per memory cell domain: the ECC coding method comprises the steps of ECC coding, data with the same bit width as the data access granularity corresponding to the ECC coding, wherein the three parts are placed in each storage unit without limitation.
5. A method for implementing the energy-efficient on-chip memory error detection and correction circuit of any one of claims 1-4, wherein the process comprises:
step S1: determining a coding and decoding circuit module of an error correcting code;
step S2: the method comprises the steps that an error correction code encoding and decoding function is embedded into an access pipeline of an on-chip memory, and the error correction code encoding and decoding of access data in the ECC function and the ECC encoding and decoding of the ECC encoding effective bits of the access data are simultaneously realized in the access process, namely, the error detection and error correction are carried out on the access data and the error correction code effective bits;
step S3: when the on-chip memory is accessed for writing, the ECC (error correction code) coding of writing data and the ECC coding of the effective bit of the error correction code are simultaneously carried out according to the access granularity access information;
step S4: ECC error correction of the ECC coding valid bit of the access data;
step S5: when reading access of an on-chip memory is carried out, firstly carrying out error detection and correction on the read 3-bit access data ECC coding effective bits; then, ECC decoding and error correction are performed on the read data according to whether the valid bit is valid.
6. The method for implementing the energy-efficient on-chip memory error detection and correction circuit according to claim 5, wherein in step S3, if the granularity of the memory access data is not less than n, the memory access data ECC coding valid bit is set to be valid, and the memory access data ECC coding valid bit and the memory access data ECC coding are implemented at the same time; and if the granularity of the access and memory data is less than n, not performing ECC coding on the access and memory data, setting the ECC coding valid bit of the access and memory data to be invalid, and performing ECC coding valid bit coding on the access and memory data.
7. The method for implementing the energy-efficient on-chip memory error detection and correction circuit as claimed in claim 6, wherein in step S4, when the ECC correction of the ECC encoding valid bit of the access data is performed, a redundant storage and a few error detection and correction modes subject to majority decision are adopted, that is, a logic value of one ECC encoding valid bit is stored in three copies, that is, 3 access units are written simultaneously to implement the error correction code encoding of the ECC encoding valid bit; during the memory access, memory related access signals are generated according to the data access granularity and the access address, and the data of the memory access, the corresponding ECC code and the effective ECC code with the same 3 bits are written into the corresponding position of the on-chip memory corresponding to the target address.
8. The method for implementing the energy-efficient on-chip memory error detection and correction circuit according to claim 5, wherein in step S5, if the logic values of the read 3-bit access data ECC encoding valid bits are completely the same, the access data ECC encoding valid bits do not report errors and do not correct errors; if the data are different, the ECC coding effective bit of the access data reports errors, and two same values in the 3 read values are selected to finish error correction; after completing the error detection and error correction of the ECC coding effective bit of the access data, performing ECC decoding and error correction on the read data according to whether the effective bit is effective or not, if the ECC coding effective bit of the access data after error detection and error correction is effective, performing ECC decoding and error correction on the read data, and selecting the access data according to the access granularity and the access address; if the ECC coding effective bit of the access data is invalid, the access data is read out without error correction code decoding and data error correction, and the access data is directly selected from the read data according to the access granularity and the access address.
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