CN114974353A

CN114974353A - Single event upset resistance reinforcing method and system based on dynamic ECC

Info

Publication number: CN114974353A
Application number: CN202210396978.9A
Authority: CN
Inventors: 刘红侠; 周育伦; 王树龙; 陈树鹏; 李志强; 韩婷婷; 田密
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2022-04-15
Filing date: 2022-04-15
Publication date: 2022-08-30

Abstract

The invention discloses a single event upset resistance reinforcing method and a single event upset resistance reinforcing system based on dynamic ECC (error correction code), wherein the method comprises the following steps: setting a system state; when the system needs to store data: if the system is in an ECC closed state, writing original CPU data into a first memory; if the system is in an ECC (error correction code) opening state, writing original CPU data into a first memory, and simultaneously writing a check code generated for the original CPU data according to a current ECC protection mode into a corresponding memory cell in a second memory; when the system needs to read data: if the system is in an ECC closed state, directly reading original CPU data in the first memory; and if the system is in an ECC (error correction code) opening state, reading the original CPU data in the first memory and the check code in the second memory respectively, processing the original CPU data by using the check codes, and outputting the processed CPU data. The single event upset resistance reinforcing method provided by the invention can be switched in various ECC modes, and is more flexible when a system faces different application scenes.

Description

Single event upset resistance reinforcing method and system based on dynamic ECC

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a single event upset resistance reinforcing method and system based on dynamic ECC.

Background

A large number of high-energy radiation particles exist in the cosmic space, and when the radiation particles bombard an SRAM (Static Random-Access Memory), charges are accumulated at a sensitive node of the SRAM, and once the charge accumulation exceeds a threshold, the stored potential is inverted, that is, Single Event Upset (SEU). In the CPU, the area of the Cache (Cache memory) already occupies nearly half of the CPU area, and the storage part of the Cache is composed of the SRAM, so that it is important to guarantee the reliability of the SRAM in the Cache. With the development of aerospace industry, the reliability of circuits becomes more important, so that a reinforcement method needs to be adopted in the design of integrated circuits to prevent the phenomenon of single event upset.

Currently, there are many ways to reinforce SEU. An Error Correction Codes (ECC) is a common system-level reinforcement method, and the most representative is a Hamming Code. The improved Hamming code can achieve the effects of Correcting 1bit errors and Detecting 2 bit errors (Single Error Correcting, Double Error Detecting, SECDED), and is widely applied to actual circuits due to the fact that the number of check bits (redundant bits) is small and coding and decoding logics are simple. In addition, there are some more complicated ECC encoding schemes such as DECTED (Double Error Correcting, Triple Error Detecting), OLSC, etc., but these methods also bring extra area overhead while increasing reliability, i.e. more redundant bits are needed.

In practical application scenarios, various different scenario requirements may be faced, such as scenarios requiring high reliability, or scenarios pursuing performance without requiring higher reliability, etc. However, the current CPU is often a fixed ECC scheme, and cannot dynamically adjust the ECC scheme, so that the current CPU does not have good flexibility and cannot be applied to different application scenarios.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a dynamic ECC-based single event upset resistance reinforcing method and system. The technical problem to be solved by the invention is realized by the following technical scheme:

in one aspect, the invention provides a single event upset resistance reinforcing method based on dynamic ECC, which comprises the following steps:

setting the system state as an ECC closed state or an ECC open state; the ECC starting state comprises a plurality of different ECC protection modes;

when the system needs to store data:

if the system is in an ECC closed state, writing original CPU data into a first memory;

if the system is in an ECC (error correction code) opening state, writing original CPU data into a first memory, and simultaneously writing a check code generated for the original CPU data according to a current ECC protection mode into a corresponding storage unit in a second memory;

when the system needs to read data:

if the system is in an ECC closed state, directly reading original CPU data in the first memory;

and if the system is in an ECC (error correction code) opening state, respectively reading the original CPU data in the first memory and the check code in the second memory, processing the original CPU data by using the check code, and outputting the processed CPU data.

In one embodiment of the present invention, the ECC protection mode includes at least two of a parity protection mode, a SECDED protection mode, and a DECTED protection mode.

In an embodiment of the present invention, after setting the system state as an ECC off state or an ECC on state, the method further includes:

and generating a gating signal according to the current system mode to control the opening and closing of the clock of the corresponding storage unit in the second memory. In an embodiment of the present invention, processing the CPU data by using the check code, and outputting the processed CPU data includes:

utilizing a check code to judge the correctness of the original CPU data and outputting error position information;

under different ECC protection modes, selectively correcting the detected errors according to the error position information;

and outputting the CPU data processed by the current ECC protection mode.

In another aspect, the present invention provides a single event upset resistance reinforcement system based on dynamic ECC, including:

a first memory for storing original CPU data;

the coding module comprises a plurality of coders which are respectively used for coding the original CPU data to obtain different check codes;

the second memory comprises a plurality of memory units, and the memory units are respectively connected with the encoders correspondingly and used for storing the check codes generated by different encoders;

the control module is used for setting the system state to be an ECC (error correction code) closed state or an ECC open state so as to realize the selection of the system mode;

the decoding module comprises a plurality of decoders which are respectively correspondingly connected with the plurality of storage units and are respectively connected with the first memory, and is used for judging the correctness of the original CPU data according to the check code and processing the detected error to obtain the processed CPU data;

and the output module is connected with the first memory, the decoders and the control module and used for selectively outputting original CPU data or processed CPU data according to the current system mode.

In one embodiment of the invention, the encoding module comprises a parity encoder, a SECDED encoder and a DECTED encoder; accordingly, the method can be used for solving the problems that,

the second memory comprises a parity memory unit, an SECDED memory unit and a DECTED memory unit;

the decoding module comprises a parity decoder, a SECDED decoder and a DECTED decoder.

In one embodiment of the present invention, a D flip-flop is further connected between the DECTED decoder and the output block.

In an embodiment of the present invention, the control module includes a CSR register, and the CSR register is configured to output a mode selection signal to the output module to control the output module to output data in a corresponding system mode.

In an embodiment of the invention, the control module further includes a gating clock, configured to generate a gating signal to the second memory according to the mode selection signal, so as to control the on and off of the clock of the corresponding memory cell in the second memory.

In one embodiment of the invention, the output module comprises a one-out-of-multiple data selector.

The invention has the beneficial effects that:

1. the single event upset resistance reinforcing method based on the dynamic ECC can be switched among various ECC modes, and is more flexible when a system faces different application scenes; in addition, the structure that the data bit and the check bit are separated is adopted, so that the time delay for reading the SRAM is smaller;

2. the invention adopts the design of the gate control clock for each storage unit for storing the ECC check bit, so that the system only starts one corresponding storage unit and closes other storage units under a certain protection mode, thereby greatly saving the power consumption of the system.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic flowchart of a single event upset resistance reinforcing method based on dynamic ECC according to an embodiment of the present invention;

fig. 2 is a structural block diagram of a single event upset resistance reinforcement system based on dynamic ECC according to an embodiment of the present invention;

fig. 3 is a circuit structure diagram of a single event upset resistance ruggedized system based on dynamic ECC according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic flow chart of a dynamic ECC-based single event upset (sfec) -resistant reinforcement method according to an embodiment of the present invention, which includes:

setting the system state as an ECC closed state or an ECC open state; the ECC on state comprises a plurality of different ECC protection modes.

When the system needs to store data:

if the system is in an ECC (error correction code) opening state, writing original CPU data into a first memory, and simultaneously writing a check code generated for the original CPU data according to a current ECC protection mode into a corresponding memory cell in a second memory;

when the system needs to read data:

and if the system is in an ECC (error correction code) opening state, reading the original CPU data in the first memory and the check code in the second memory respectively, processing the original CPU data by using the check codes, and outputting the processed CPU data.

Specifically, in the present embodiment, the ECC protection mode may include at least two of a parity protection mode (parity mode), an SECDED protection mode (referred to as "2 detection correction mode" in the present embodiment), and a DECTED protection mode (referred to as "2 detection correction 3 mode" in the present embodiment). In addition, other protection modes can be added according to actual requirements so as to adapt to requirements of different system performances and reliability.

Preferably, the embodiment adopts three ECC protection modes, namely a parity protection mode, an SECDED protection mode and a DECTED protection mode, and the reliability of the ECC protection modes is sequentially increased, and meanwhile, the required redundancy bits are also sequentially increased. The CPU may select between using and not using ECC protection, and when ECC is not used, data is not protected, where CPU performance is best and power consumption is lowest. When the ECC protection is selected, it can be selected from the above 3 ECC coding schemes according to the reliability requirement of the application scenario at that time, and higher reliability means more redundant bits and more complex coding and decoding logic, resulting in lower performance and higher power consumption.

In this embodiment, the configuration of the system mode can be realized by selecting to output different data by the mode selection signal ecc _ sel. Specifically, different bit values are assigned to the mode selection signal to represent different system modes, for example, the system mode configuration may be performed according to the following table:

ecc_sel(2-bit)	corresponding system mode
		2’b00	Turning off ECC protection
2’b01	Open ECC protection and use parity protection
		2’b10	Starting ECC protection and using SECDED protection
2’b11	Starting ECC protection and using TECDED protection

And setting the current state of the system according to the bit value of the current mode selection signal ecc _ sel so as to output corresponding output data in the current state.

In addition, after the system state is set to be the ECC off state or the ECC on state, the method further includes:

and generating a gating signal according to the current system mode to control the opening and closing of the clock of the corresponding storage unit in the second memory.

Specifically, the second memory has 3 memory cells (SRAM or Register File) storing check bits (i.e., check codes) corresponding to the first memory storing the original CPU data, and when ECC protection is not turned on, clocks of the 3 memory cells storing the check bits are all turned off by gating the clocks. When the ECC protection is turned on, the clocks of the remaining 2 memory cells are also turned off except for the ECC memory cell used.

For example, a 3-bit gating signal cg (clock gating) may be set, and when the system is in different modes, that is, when the mode selection signal ecc _ sel has different bit values, the bit values of the corresponding gating signal cg are as follows:

ecc_sel(2-bit)	cg(3-bit)	corresponding mode
			2’b00	3’b000	Turning off ECC protection
2’b01	3’b001	Using parity protection
			2’b10	3’b010	Using SECDED protection
2’b11	3’b100	Protection using TECDED

Specifically, when ECC _ sel is 00 and cg is 000, ECC protection is turned off, and at this time, clocks of all memory cells storing check bits are turned off; when ecc _ sel is 01 and cg is 001, the parity protection mode is turned on, at this time, only the clock of the parity memory cell is turned on, and the clocks of the rest memory cells are turned off; when ecc _ sel is 10 and cg is 010, the SECDED protection mode is turned on, and at this time, only the clock of the SECDED memory cell is turned on; when ecc _ sel is 11 and cg is 100, the DECTED protection mode is turned on, and only the clock of the DECDED memory cell is turned on at this time.

In the embodiment, by adopting the design of the gate control clock for each storage unit for storing the ECC check bits, the system only starts one corresponding storage unit and closes other storage units in a certain protection mode, thereby greatly saving the power consumption of the system. The method for reinforcing the single event upset resistance when the system is in the parity protection mode, the SECDED protection mode and the DECTED protection mode in the ECC off state and the ECC on state is described in detail below.

1) ECC protection shutdown

Specifically, when Data is to be stored in the Data Cache, the corresponding Data is directly written into the first memory (Data RAM), and at this time, the clocks of the three memory cells in the second memory are all in an off state, so that the check bits generated by the encoder are not written into the corresponding memory cells.

When Data is read later, Data is also read out directly from the Data RAM.

2) ECC protection open

In this embodiment, when Data is to be stored in the Data Cache, a check code is generated and written into the corresponding storage unit in the current mode while the Data RAM is written, and at this time, clocks of the other 2 storage units should be in a closed state. The writing of data needs to be accompanied by the writing of the corresponding check bits.

When Data is read later, the Data RAM is read, and the check bit in the corresponding check bit storage unit is also read out simultaneously. Then, the CPU data is processed by utilizing the check bit, and the processed CPU data is output, wherein the check bit comprises the following components:

the method comprises the steps of utilizing a check code to judge the correctness of original CPU data and outputting error position information;

and outputting the CPU data processed by the current ECC protection mode.

The following describes the process of determining and processing the original CPU data by different check codes in the three protection modes in sequence.

2.1) parity protection mode

Specifically, the parity protection mode generates a parity check code for the original CPU data, which can only detect odd bit (1bit,3-bit,5-bit …) errors, but cannot directly correct the errors. When an error is found, the error position information is directly output, and the currently read data cannot be used.

2.2) SECDED protection mode

SECDED can correct single bit errors and detect double bit errors.

If single bit error is found, the data is corrected by itself, correct data which can be used after correction is output, and error position information is output at the same time. At a later appropriate time, the corresponding data bits are corrected using the error location information while the corresponding check code is modified to prevent accumulation of errors.

If a double bit Error is found, Error information is directly output and the currently read data cannot be used.

2.3) DECTED protected mode

DECTED can correct single bit and double bit errors and detect three bit errors.

Similar to SECDED, if a single-bit or double-bit error occurs, the data is corrected by itself and error location information is output to prevent accumulation of errors.

If a three-bit Error occurs, Error information is directly output, and the currently read data cannot be used.

And finally, reading corresponding data in a certain system mode according to the system mode.

Specifically, the present embodiment may implement the selection of the output data through a one-out-of-multiple selector. When the selector receives the corresponding mode selection signal ecc _ sel, the corresponding data is selected as output.

The single event upset resistance reinforcing method based on the dynamic ECC can be switched among various ECC modes, and is more flexible when a system faces different application scenes; in addition, the structure that the data bit and the check bit are separated is adopted in the embodiment, so that the time delay for reading the SRAM is smaller.

Example two

On the basis of the first embodiment, the present embodiment provides a single event upset resistance reinforcement system based on dynamic ECC, which can be used to implement the single event upset resistance reinforcement method based on dynamic ECC provided in the first embodiment.

Specifically, referring to fig. 2, fig. 2 is a block diagram of a single event upset (sfet) resisting reinforcement system based on dynamic ECC according to an embodiment of the present invention, which includes:

a first memory 1 for storing original CPU data;

the coding module 2 comprises a plurality of coders which are respectively used for coding the original CPU data to obtain different check codes;

the second memory 3 comprises a plurality of memory units, the memory units are respectively correspondingly connected with the encoders and used for storing the check codes generated by different encoders;

the control module 4 is used for setting the system state to be an ECC closed state or an ECC open state so as to realize the selection of the system mode;

the decoding module 5 comprises a plurality of decoders which are respectively correspondingly connected with the plurality of storage units and are all connected with the first memory 1, and is used for judging the correctness of the original CPU data according to the check code and processing the detected errors to obtain the processed CPU data;

and the output module 6 is connected with the first memory 1, the decoders and the control module 4 and is used for selectively outputting original CPU data or processed CPU data according to the current system mode.

Specifically, in this embodiment, for example, three ECC protection modes are implemented, the encoding module includes three encoders, the second memory correspondingly includes three storage units, and the decoding module correspondingly includes three decoders.

More specifically, referring to fig. 3, fig. 3 is a circuit structure diagram of a single event upset (sfg) resisting reinforcement system based on dynamic ECC according to an embodiment of the present invention. The first memory 1 is implemented by a Data RAM.

The three protection modes adopted by the implementation are a parity protection mode, an SECDED protection mode and a DECTED protection mode respectively, and then

The encoding module 2 includes a Parity Encoder (Parity Encoder), a SECDED Encoder (SECDED Encoder), and a DECTED Encoder (DECTED Encoder).

Accordingly, the second memory 3 includes a parity memory cell, a SECDED memory cell (SECDED RAM), and a DECTED memory cell (DECTED RAM);

because the Parity check code has only 1bit, the storage unit storing the Parity check code uses a Register File (Register File), such as the Parity Register File in fig. 3, compared with the SRAM, the area is not much larger, and the timing sequence and reliability of the Register are better, and the SECDED storage unit and the DECTED storage unit are implemented by the conventional SRAM.

Accordingly, the decoding block 5 includes a Parity Decoder (Parity Decoder), a SECDED Decoder (SECDED Decoder), and a DECTED Decoder (DECTED Decoder).

Further, a D flip-flop 7 is connected between the DECTED decoder and the output block 6.

In particular, since the DECTED decoder consumes much more logic than SECDED, a D flip-flop (DFF) is added to the path to meet the timing requirements, so that the overall pipeline frequency is not affected.

In this embodiment, the control module 4 includes a CSR (control and Status register) register, and the CSR register outputs a mode selection signal ecc _ sel to the output module 6 to control the output module 6 to output data corresponding to the system mode.

For example, when the bit value of the CSR register output mode selection signal ECC _ sel is 00, the system turns off the ECC protection mode, so that the output module 6 directly outputs the Data in the Data RAM. When the bit value of the mode selection signal ECC _ sel output by the CSR register is 01, 10, or 11, the system is in the ECC protection open mode and corresponds to the parity protection mode, the SECDED protection mode, and the DECTED protection mode, respectively, and the output selection module selects and outputs data in the corresponding mode.

It should be noted that the mode switching is controlled by an extended register in the CSR, and the read/write permission to the CSR can be provided only in the privileged mode, so the mode switching needs to be completed by the operating system.

In addition, the control module 4 further includes a clock gating (clock gating in fig. 3) for generating a gating signal to the second memory according to the mode selection signal to control the on/off of the clock of the corresponding memory cell in the second memory.

Specifically, referring to the first embodiment, when the mode selection signal ecc _ sel is 00, 01, 10, 11, the gated clock output gating signal cg corresponds to 000, 001, 010, 100, so as to control the clock switches of different memory cells in the second memory.

In addition, the single event upset resistance reinforcement system based on dynamic ECC provided in this embodiment is further externally connected to an Error Handling Module 8, that is, an Error Handling Module in fig. 3, for Handling detected errors. When the system is in any one protection mode under the ECC protection state, after the ECC code is adopted to detect the original CPU data, error position information is sent to the module so as to selectively correct the corresponding data bit at a proper time, and meanwhile, the corresponding check code is modified so as to prevent the accumulation of errors.

In this embodiment, the output module 6 includes a one-out-of-multiple data selector (MUX). Specifically, since the system provided by the present embodiment has the system mode of ECC off and three ECC on, the present embodiment adopts a 4-to-1 selector to select the output data.

More specifically, the 1-out-of-4 selector is connected to a CSR register, which outputs a 2-bit mode selection signal ecc _ sel to the selector to implement scene selection.

And the 4-to-1 selector selects corresponding data as corrected data to be output according to the corresponding system mode.

The following describes in detail the working process of the dynamic ECC-based single event upset resistant reinforcement system according to this embodiment.

First, the operating system controls the CSR to output the mode selection signal ecc _ sel to implement mode selection, and the gated clock outputs a corresponding value of the gating signal cg according to the value of the mode selection signal ecc _ sel to implement control of each memory cell in the second memory.

Specifically, when the mode selection signal ECC _ sel output from the CSR to the one-out-of-four selector is 00, the system is in the ECC off mode, and the gated clock outputs a 3-bit cg signal 000 to control the clock off of each memory cell in the second memory.

When the mode selection signal ECC _ sel output by the CSR to the one-out-of-four selector is 01, 10 or 11, the system is in the ECC-on mode, and the gated clock outputs a 3-bit cg signal 001, 010 or 100 to the corresponding memory cell in the second memory, so as to turn on the clock of the cell and keep the clocks of the remaining memory cells off.

Then, data storage is performed.

When the CPU needs to store Data, the Data can be directly written into the Data RAM when the ECC is closed. When ECC is started, Data can be written into the Data RAM, and meanwhile, the check code in the current mode is stored into the corresponding storage unit.

Finally, data reading is performed.

When the CPU needs to read Data, the original Data stored in the Data RAM is directly read when the ECC is closed. When the ECC is turned on, the decoding module 5 reads the original Data stored in the Data RAM and the check code in the corresponding storage unit, processes the Data by using the check code, and reports the detected error information position to the error processing module 8, so as to selectively correct the Data by using the information in the following period, thereby obtaining the corresponding output Data.

In this embodiment, for the process of processing data by using check codes in different modes, reference is made to the first embodiment described above, and details of this embodiment are not described herein.

The single event upset resistant reinforcement system based on the dynamic ECC provided by the embodiment can be switched among a plurality of ECC modes, and is more flexible when the system faces different application scenes.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A single event upset resistance reinforcing method based on dynamic ECC is characterized by comprising the following steps:

when the system needs to store data:

when the system needs to read data:

2. The dynamic ECC-based single event upset resistant reinforcement method of claim 1, wherein the ECC protection mode comprises at least two of parity protection mode, SECDED protection mode and DECTED protection mode.

3. The dynamic ECC-based single event upset resistant reinforcement method of claim 1, wherein after setting the system state as an ECC off state or an ECC on state, the method further comprises:

4. The single event upset resistance reinforcing method based on the dynamic ECC of claim 1, wherein the processing the CPU data by using the check code and outputting the processed CPU data comprises:

and outputting the CPU data processed by the current ECC protection mode.

5. A single event upset resistance reinforcement system based on dynamic ECC is characterized by comprising:

a first memory (1) for storing raw CPU data;

the coding module (2) comprises a plurality of coders which are respectively used for coding the original CPU data to obtain different check codes;

the second memory (3) comprises a plurality of memory units, and the memory units are respectively correspondingly connected with the encoders and used for storing check codes generated by different encoders;

the control module (4) is used for setting the system state to be an ECC (error correction code) closed state or an ECC open state so as to realize the selection of the system mode;

the decoding module (5) comprises a plurality of decoders which are respectively correspondingly connected with the plurality of storage units and are respectively connected with the first memory (1), and is used for judging the correctness of the original CPU data according to the check code and processing the detected error to obtain the processed CPU data;

and the output module (6) is connected with the first memory (1), the decoders and the control module (4) and is used for selectively outputting original CPU data or processed CPU data according to the current system mode.

6. The single event upset resistant reinforcement system based on dynamic ECC of claim 5, wherein the encoding module (2) comprises a parity encoder, an SECDED encoder and a DECTED encoder; accordingly, the method can be used for solving the problems that,

the second memory (3) comprises a parity memory unit, an SECDED memory unit and a DECTED memory unit;

the decoding module (5) comprises a parity decoder, a SECDED decoder and a DECTED decoder.

7. The single event upset immunity system based on dynamic ECC of claim 5, wherein a D flip-flop (7) is further connected between the DECTED decoder and the output module (6).

8. The dynamic ECC-based single event upset resistant reinforcement system of claim 5, wherein the control module (4) comprises a CSR register for outputting a mode selection signal to the output module (6) to control the output module (6) to output data in a corresponding system mode.

9. The dynamic ECC-based single event upset mitigation system according to claim 8, wherein the control module (4) further comprises a clock gating unit for generating a gating signal to the second memory according to the mode selection signal to control the clock gating unit to turn on and off corresponding memory cells in the second memory.

10. The dynamic ECC-based single event upset immunity reinforcement system of claim 5, wherein the output module (6) comprises a one-out-of-many data selector.