CN110309014B - Data read-write structure and data read-write method of full-line coding and decoding SRAM encoder - Google Patents
Data read-write structure and data read-write method of full-line coding and decoding SRAM encoder Download PDFInfo
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
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Abstract
The invention discloses a data read-write structure of an SRAM encoder with full-line encoding and decoding and a data read-write method, which utilizes a register to temporarily store full-line data of the SRAM encoder and EDAC module data, so that a plurality of address data in one line are uniformly encoded and stored, thereby reducing the storage capacity of EDAC codes, simultaneously reducing the total capacity of a memory greatly, reducing the area of the memory, and preventing the accumulated effect of time on memory errors by reading out the internal data of the SRAM encoder one by one, checking and correcting and then writing in the internal data one by one, thus refreshing the memory content only by accessing one address in one line of data, realizing the refreshing of the whole line, improving the refreshing efficiency and reducing the refreshing time. The EDAC module is adopted to carry out error correction and detection, and when the storage has storage data dislocation, the error correction and detection is carried out automatically, so that the requirement of data reinforcement at a system level is saved in the use of a user, and the complexity of system design is reduced.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a data read-write structure and a data read-write method of a full-line coding and decoding SRAM encoder.
Background
In existing SRAM designs, the corresponding memory space is typically found by row decoding and column decoding the access address, and then the data stored in the memory space is read or written. In order to implement fault-tolerant design of on-chip data, it is generally adopted to perform EDAC (error detection and correction) coding reinforcement on single address data, i.e. to configure 1 group of EDAC codes for n-bit (8-bit, 16-bit, 32-bit or more) data of each address, when writing in a memory, the data are stored separately after EDAC coding, when reading out the memory, the EDAC codes are read out and decoded at the same time, and compared with the read-out data, so as to find and correct possible error bits in the data.
The basic idea of EDAC coding is to append check bits to the transmitted or stored information, and to establish a check relation between the two, which can be found and corrected when the check relation is destroyed by transmission errors or other disturbances. This error correction capability and error detection capability is traded for by increasing the redundancy of the data. By constructing the proper generator matrix and monitor matrix, when an error occurs in a certain bit in the code word, a unique non-zero syndrome S vector is obtained, and the vector is only related to the pattern of the error position of the code word and is irrelevant to the code word, so that the correction of single error in data can be realized through redundant monitor bits. Currently, the common EDAC codes mainly comprise Hamming codes, BCH codes, RS codes and the like, and the error detection codes mainly comprise parity check codes, CRC codes, checksums and the like. In general, the stronger the error correction and detection capability, the more check meta-information it needs to additionally store, the more complex the decoding process will be, which will eventually bring about a heavy storage burden on the system and may reduce the overall performance of the system.
In addition, error correction coding is used as a subject, different codes have different correction characteristics, different coding efficiency and implementation complexity, and the same code also has different structural modes and decoding implementation modes, so according to the characteristics of a memory, the EDAC technology of the memory under different process conditions is researched, and the selection of a proper EDAC implementation mode is important for the data fault tolerance reinforcement and the read-write speed of the memory.
The current SRAM fault-tolerant design technology based on EDAC circuits has become the mainstream data fault-tolerant reinforcement technology of large-capacity memories in the industry. The column selection circuit of the large-capacity memory is 8, 1 and above, so that the one-bit error correction and detection mode becomes the optimized selection of the 32-bit large-capacity SRAM chip above the 150nm process, and the added check bit data area occupies 20% of the whole area. And after the process enters the ultra-deep submicron process, the probability of multi-bit errors of the IO port is greatly increased, the radiation-resistant reinforcement performance requirement cannot be met by a one-bit error correction and detection mode, the two-bit error correction and detection mode gradually becomes the main trend of the ultra-deep submicron process and SRAM radiation-resistant reinforcement research below, and the area cost is larger and larger.
To be generally based on error controlHamming codes in the code are used as an example to illustrate the method of device resistance to memory data bit errors. Hamming codes are linear block (n, k) codes that can only correct a single error, and are ineffective when 2 or more errors occur in a codeword, and are likely to produce errors due to superposition of 2 (or more) errors, which are considered to be another error. The Hamming code is expanded by adding one more check element, so that the Hamming distance d is increased by 1, namely d=4, and 1 check 2 (according to theorem 2) is achieved, namely all two errors can be checked, and the error code cannot be caused. The number of information elements and check elements of the Hamming code needs to satisfy: 2 r Not less than k+r+1; where r is the number of check elements. The check element of the extended Hamming code needs to be added one more, namely, the following conditions are satisfied:
2 r ≥k+r (1)
the Hamming code decoding method determines that it can only correct 1 error. But is widely used because of its simplicity of decoding. As described above, in order to realize the function of 1-bit data correction 2, according to expression (1), in order to obtain an extended Hamming code, a 32-bit information element, 7-bit check elements, that is, hamming codes of (39, 32), are required.
In the prior SRAM memory architecture adopting EDAC technology for fault tolerance reinforcement, EDAC coding is generally carried out on single address data. In this structure, after the common bit line of each column of memory cells is connected to YMUX (multiple select one gate), each YMUX corresponds to a set of read/write circuits, and EDAC encodes data of each address separately and stores the encoded data in the EDAC code storage area. The working principle is shown in fig. 1, and four modules of an EDAC code storage area, an EDAC coding logic, an EDAC decoding logic, a comparator and a data strobe logic are mainly added on the basis of the original data storage area in order to realize fault tolerance reinforcement of storage data. If the data width of the SRAM is 32 bits, if the EDAC Hamming code technology is adopted to realize the 1 correction and 2 detection functions, each address needs to be added with 7 bits of storage area as EDAC code storage space. The working process of the SRAM memory is as follows:
and (one) a read operation: when the SRAM memory is read, (1) corresponding data of the data storage area and corresponding EDAC codes of the EDAC code storage area are selected according to the read address, and then output through the read-write circuit after being selected by the column circuit YMUX, (2) the read EDAC codes are decoded and compared with the read data, (3) the read data are directly output to the memory IO port if the result is correct, and (4) the data are output to the memory IO port after being corrected if the result is incorrect, and meanwhile, the correct data are written back to the data storage area.
(II) write operation: when writing operation is performed on the SRAM memory, (1) 32-bit data to be written is selectively written to the corresponding address of the data storage area through the read-write circuit and YMUX, (2) the 32-bit write data is EDAC-encoded at the same time and the encoding is written to the corresponding address of the EDAC storage area.
But the total storage capacity occupied by the EDAC code required by the existing full line coding is large, and the area consumption of the memory is large. SRAM with fault tolerance reinforcement by EDAC technology generally needs to refresh contents at regular time, i.e. when the memory is idle, internal data is read out one by one, checked and corrected, and then written in, so as to prevent cumulative effect of time on memory errors, and thus, the memory contents need to be refreshed. The original technology for encoding single address data generally adopts single address data refreshing, and has low efficiency.
Disclosure of Invention
The invention aims to provide a data read-write structure and a data read-write method of a full-line coding-decoding SRAM encoder, which overcome the defects of the prior art.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the data read-write structure of the full-line coding and decoding SRAM encoder comprises an EDAC module, a register, a comparison error correction logic module and YMUX units;
the EDAC module is connected with the SRAM encoder;
the EDAC module is used for performing EDAC encoding on the data stored in the SRAM encoder and storing the EDAC code;
the register is used for reading the data in the SRAM encoder and the corresponding EDAC code in the EDAC module,
the comparison error correction logic module is used for acquiring EDAC codes from the register, decoding the EDAC codes to obtain decoded data, and then performing error detection and correction on the decoded data and the data in the read SRAM encoder; outputting the detection result through YMUX units or writing the corrected result back to the SRAM encoder;
the YMUX cell is used for address selection and outputting data.
Further, the comparison error correction logic module comprises an error correction and detection module and a write-back circuit.
Further, the YMUX unit is a one-out-of-many gate.
Further, each column of memory cells in the SRAM memory corresponds to a bit line and a set of read and write circuits.
A data reading method of a full-line coding and decoding SRAM encoder data read-write structure comprises the following steps:
step 1), according to the row decoding result of the read address, all the storage data in the SRAM encoder of the row corresponding to the read address and the EDAC code data in the EDAC module are read out;
step 2), decoding the read EDAC code data, comparing the decoded data result with the stored data in the SRAM encoder, if the stored data in the SRAM encoder corresponds to the decoded data result, sending the read stored data into YMUX units for reading address selection, finally reading the required data, if the stored data in the SRAM encoder is inconsistent with the decoded data result, correcting the wrong stored data, then writing the corrected stored data back to the corresponding row in the data storage area, and simultaneously sending the corrected stored data to the YMUX units for reading address selection, thereby finishing data reading.
Further, the data read from the SRAM encoder and the EDAC module is temporarily stored through a register.
A data writing method of a full-line coding and decoding SRAM encoder data reading and writing structure comprises the following steps: when the SRAM memory performs writing operation, firstly reading out full-line data in an SRAM encoder corresponding to a writing operation address and EDAC codes in an EDAC module, correcting error detection of the read full-line data, when the full-line data corresponds to the EDAC code decoded data correctly, replacing corresponding bits in the read full-line data with written data according to the writing address to obtain written full-line data, temporarily storing the written full-line data into a register, then performing EDAC coding on the written full-line data to obtain written EDAC codes, and writing the written full-line data and the written EDAC codes back to corresponding lines in the SRAM encoder and the EDAC module;
when the contrast of the full line data and the EDAC code decoded data is different, correcting error bits in the read full line data, replacing bit data corresponding to a writing address in the corrected full line data with writing data to obtain writing full line data, temporarily storing the writing full line data into a register, performing EDAC coding on the writing full line data to obtain writing EDAC code, and writing the writing full line data and the writing EDAC code back to corresponding lines in an SRAM coder and an EDAC module; and finishing the data writing of the SRAM error correction and detection.
Further, after the read EDAC code data is decoded, error correction and detection correction are carried out on the read full-line data.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention relates to a data read-write structure of an SRAM encoder and a data read-write method, which utilize a register to temporarily store the data of the whole line of the SRAM encoder and the data of an EDAC module, so that a plurality of address data in one line are uniformly encoded and stored, and for a memory with a certain capacity, the total storage capacity of EDAC codes required by the method is much less than that of the original single address data encoding, so that the storage capacity of the EDAC codes is reduced, and the total capacity of the memory is reduced, and the area of the memory is greatly reduced. The EDAC module is adopted to carry out error correction and detection, and when the storage data dislocation occurs in the storage, the error correction and detection is carried out automatically without user intervention, so that the requirement of data reinforcement at a system level is saved in the use of a user, and the complexity of system design is reduced.
Drawings
FIG. 1 is a schematic diagram of the working principle of an SRAM memory using the single address error correction and detection technique.
FIG. 2 is a flow chart of SRAM memory read operations employing full row code error correction and detection techniques.
FIG. 3 is a flow chart of a write operation of an SRAM memory using full row code error correction and detection techniques.
Detailed Description
The invention is described in further detail below with reference to the attached drawing figures:
the data read-write structure of the full-line coding and decoding SRAM encoder comprises an EDAC module, a register, a comparison error correction logic module and YMUX units;
the EDAC module is connected with the SRAM encoder;
the EDAC module is used for performing EDAC encoding on the data stored in the SRAM encoder and storing the EDAC code;
the register is used for reading the data in the SRAM encoder and the corresponding EDAC code in the EDAC module,
the comparison error correction logic module is used for acquiring EDAC codes from the register, decoding the EDAC codes to obtain decoded data, and then performing error detection and correction on the decoded data and the data in the read SRAM encoder; outputting the detection result through YMUX units or writing the corrected result back to the SRAM encoder;
the YMUX cell is used for address selection and outputting data.
The comparison and error correction logic module comprises an error correction and detection module and a write-back circuit;
the YMUX unit is a multi-selection gating device;
each column of memory cells in the SRAM corresponds to a bit line and a set of read-out circuit and write-in circuit;
a data reading method of a full-line coding and decoding SRAM encoder data read-write structure comprises the following steps:
step 1), according to the row decoding result of the read address, firstly, all the storage data in the SRAM encoder of the row corresponding to the read address and the EDAC code data in the EDAC module are read out; temporarily storing the read data through a register;
step 2), decoding the read EDAC code data, comparing the decoded data result with the stored data in the SRAM encoder, if the stored data in the SRAM encoder corresponds to the decoded data result, sending the read stored data into YMUX units for reading address selection, finally reading the required data, if the stored data in the SRAM encoder is inconsistent with the decoded data result, correcting the wrong stored data, then writing the corrected stored data back to the corresponding row in the data storage area, simultaneously sending the corrected stored data to the YMUX units for reading address selection, and finally reading the required data.
A data writing method of a full-line coding and decoding SRAM encoder data reading and writing structure comprises the following steps: when the SRAM memory performs writing operation, firstly reading out full-line data in an SRAM encoder corresponding to a writing operation address and EDAC codes in an EDAC module, correcting error detection of the read full-line data, when the full-line data corresponds to the EDAC code decoded data correctly, replacing corresponding bits in the read full-line data with written data according to the writing address to obtain written full-line data, temporarily storing the written full-line data into a register, then performing EDAC coding on the written full-line data to obtain written EDAC codes, and writing the written full-line data and the written EDAC codes back to corresponding lines in the SRAM encoder and the EDAC module;
when the contrast of the full line data and the EDAC code decoded data is different, correcting error bits in the read full line data, replacing bit data corresponding to a writing address in the corrected full line data with writing data to obtain writing full line data, temporarily storing the writing full line data into a register, performing EDAC coding on the writing full line data to obtain writing EDAC code, and writing the writing full line data and the writing EDAC code back to corresponding lines in an SRAM coder and an EDAC module; and finishing the data writing of the SRAM error correction and detection.
Decoding the read EDAC code data, and then carrying out error correction and detection correction on the read full-line data;
the structural principles and steps of the present invention will be further described with reference to the accompanying drawings, in which:
examples
The description of the data read-write structure of the SRAM encoder adopting full-line encoding and decoding is as follows:
taking an SRAM memory with 32 bits of data bit width and 1024 columns of memory array as an example, the corresponding full-row encoding and decoding EDAC module array is 12 bits, so the total column number of the memory array of the register is 1036; wherein each column of memory cells corresponds to a bit line and a set of Sense (SA) and write circuits. The working process is as follows:
and (one) a read operation: when the SRAM memory is read, (1) according to the row decoding result of the read address, firstly, all the data of the 1024-bit data storage area and the 12-bit EDAC code storage area of the row corresponding to the read address are read out at one time, the read 12-bit EDAC code is decoded, (2) the decoded data result is compared with 1024-bit data read out from the data area, if the comparison result is correct, all 1024-bit data are sent to the YMUX module, and (3) the YMUX module reads out the data required by 32 bits after selecting according to the read address; (4) If the comparison result is wrong, correcting the wrong 1024-bit data, (5) then writing all the corrected 1024-bit data back to the corresponding row in the data storage area, (6) simultaneously sending the corrected 1024-bit data to the YMUX module, and sending the data required by 32 bits to the memory IO for reading after selecting according to the read address. As shown in fig. 2.
(II) write operation: when writing the SRAM, the method comprises the steps of (1) sending 32-bit data to be written to an IO port, (2) simultaneously, in 1024-bit data and EDAC code storage areas in a row corresponding to an address to be written, completely reading out 12-bit EDAC codes, temporarily storing the 12-bit EDAC codes in a register, decoding the EDAC codes, (3) comparing a decoding result with the read 1024-bit data, if the comparison result is correct, replacing corresponding bits in the read 1024-bit data with the data written in the IO port according to the written address to obtain the 1024-bit data, temporarily storing the 1024-bit data in the register, and (4) carrying out EDAC coding on the 1024-bit data to obtain the written EDAC codes, and writing the written 1024-bit data and the written EDAC codes back to the corresponding rows in the SRAM encoder and the EDAC module; (5) If the comparison result is wrong (i.e. when the difference exists), correcting 1024-bit error data firstly, (6) replacing corresponding bits in the read 1024-bit data by using write data written at an IO port to obtain written 1024-bit data, temporarily storing the written 1024-bit data into a register, (7) performing EDAC coding on the written 1024-bit data to obtain written EDAC codes, and writing the written 1024-bit data and the written EDAC codes back to corresponding rows in the SRAM encoder and the EDAC module. As shown in fig. 3.
Since the wider the data bit width to be encoded and decoded is in the EDAC module encoding and decoding, the higher the error correction code bit efficiency is required, that is, the fewer the number of encoding bits required for a unit data bit is. For example, for 1024 data in each row, if the memory data bit width is 32 bits, the total number of EDAC codes required for each row is 7 (1024/32) =224, and if full row coding is used, the number of EDAC code bits required for each row is 12, and the corresponding area is reduced by 18.67 times. If for 2048 data per line, if the memory data bit width is 32 bits, the total number of EDAC codes required per line is 7 (2048/32) =448, and if full line coding is used, the number of EDAC code bits required per line is 13, the corresponding area is reduced by 34.46 times. For EDAC codes of four types, the area advantage of the invention is more obvious, and the comparison result is shown in Table 1.
Table 1 comparison of effects with full-row codec and with single address codec
The SRAM memory with EDAC fault-tolerant structure adopts a full-row refreshing mode. The full-line refreshing is equivalent to the simultaneous data refreshing of a plurality of addresses, and compared with the address-by-address refreshing adopted by the traditional EDAC fault-tolerant SRAM memory, the full-line refreshing improves the refreshing efficiency and reduces the total refreshing time. For example, for 1024 bits of data per row, if the single address data is 32 bits, each row includes 1024/32=32 single address data, so the SRAM memory refresh time with full row encoding is 1/32 of the SRAM memory refresh time with single address encoding.
Claims (8)
1. The data read-write structure of the full-line coding and decoding SRAM encoder is characterized by comprising an EDAC module, a register, a comparison error correction logic module and YMUX units;
the EDAC module is connected with the SRAM encoder;
the EDAC module is used for performing EDAC encoding on the data stored in the SRAM encoder and storing the EDAC code;
the register is used for reading the data in the SRAM encoder and the corresponding EDAC code in the EDAC module,
the comparison error correction logic module is used for acquiring EDAC codes from the register, decoding the EDAC codes to obtain decoded data, and then performing error detection and correction on the decoded data and the data in the read SRAM encoder; outputting the detection result through YMUX units or writing the corrected result back to the SRAM encoder;
the YMUX unit is used for selecting addresses and outputting data; and temporarily storing the full-line data of the SRAM encoder and the EDAC module data by using a register, so that a plurality of address data in one line are uniformly encoded and stored.
2. The full row codec SRAM encoder data read/write architecture of claim 1, wherein the compare error correction logic comprises an error correction module and a write back circuit.
3. The data read-write structure of full row codec SRAM encoder of claim 1, wherein the YMUX cell is a one-to-one strobe.
4. The data read-write structure of a full-row codec SRAM encoder according to claim 1, wherein each column of memory cells in the SRAM memory corresponds to a bit line and a set of read-out circuit and write-in circuit.
5. A data reading method based on the full-line codec SRAM encoder data read-write structure of claim 1, comprising the steps of:
step 1), according to the row decoding result of the read address, all the storage data in the SRAM encoder of the row corresponding to the read address and the EDAC code data in the EDAC module are read out;
step 2), decoding the read EDAC code data, comparing the decoded data result with the stored data in the SRAM encoder, if the stored data in the SRAM encoder corresponds to the decoded data result, sending the read stored data into YMUX units for reading address selection, finally reading the required data, if the stored data in the SRAM encoder is inconsistent with the decoded data result, correcting the wrong stored data, then writing the corrected stored data back to the corresponding row in the data storage area, and simultaneously sending the corrected stored data to the YMUX units for reading address selection, thereby finishing data reading.
6. The method for reading data from and writing to a full-line codec SRAM encoder of claim 5, wherein the data read from the SRAM encoder and EDAC module is buffered by a register.
7. A data writing method based on the full-line coding SRAM encoder data read-write structure of claim 1, comprising the steps of: when the SRAM memory performs writing operation, firstly reading out full-line data in an SRAM encoder corresponding to a writing operation address and EDAC codes in an EDAC module, correcting error detection of the read full-line data, when the full-line data corresponds to the EDAC code decoded data correctly, replacing corresponding bits in the read full-line data with written data according to the writing address to obtain written full-line data, temporarily storing the written full-line data into a register, then performing EDAC coding on the written full-line data to obtain written EDAC codes, and writing the written full-line data and the written EDAC codes back to corresponding lines in the SRAM encoder and the EDAC module;
when the contrast of the full line data and the EDAC code decoded data is different, correcting error bits in the read full line data, replacing bit data corresponding to a writing address in the corrected full line data with writing data to obtain writing full line data, temporarily storing the writing full line data into a register, performing EDAC coding on the writing full line data to obtain writing EDAC code, and writing the writing full line data and the writing EDAC code back to corresponding lines in an SRAM coder and an EDAC module; and finishing the data writing of the SRAM error correction and detection.
8. The data writing method of the full-line codec SRAM encoder data read-write structure according to claim 7, wherein the read-out EDAC code data is decoded and then error correction and detection correction are performed on the read full-line data.
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