CN111078590A

CN111078590A - Efficient access address bit overturning statistical device

Info

Publication number: CN111078590A
Application number: CN201911396493.4A
Authority: CN
Inventors: 王耀华; 刘胜; 唐冬灯; 郭阳; 鲁建壮; 陈小文; 陈海燕; 刘仲; 雷元武; 刘畅; 张洋; 张显; 金志成
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-04-28

Abstract

The invention discloses a high-efficiency memory access address bit turning statistical device, which comprises: the bit flipping monitoring array is used for triggering the access quantity counting of the corresponding storage channel according to each effective access of the storage channels; the bitwise accumulator array is used for recording the access quantity count of each storage channel; a control section for enabling and resetting and providing a read operation; the memory controller comprises a memory body and the statistical device. The invention directly counts the actual memory access address bit turnover rate, avoids the problem of inaccuracy and incompleteness of the traditional method, has the advantages of simple realization, convenient operation and capability of accurately and comprehensively counting the address bit turnover information when the application accesses the memory, and thus can effectively guide the optimization of the memory address mapping.

Description

Efficient access address bit overturning statistical device

Technical Field

The invention relates to the field of processors, in particular to an efficient memory access address bit turning statistical device.

Background

With the continuous development of processors, the limitation of memory efficiency on the overall performance of the processor becomes more and more obvious. The address mapping mode is one of the key factors influencing the exertion of the storage efficiency. The efficient address mapping mode can effectively reduce the storage delay, thereby greatly improving the storage efficiency, and therefore, how to optimize the address mapping mode plays an important role in the overall performance of the processor. The turn-over rate of the address bit is important information for guiding address mapping optimization, and a typical current address mapping optimization mode is to obtain address change information through offline simulation of a program and perform corresponding mapping optimization according to the information. However, due to the influence of factors such as dynamic task scheduling of an operating system, address transformation, simulator implementation precision and the like, the real transformation situation of the access and memory addresses of the application program cannot be completely and accurately counted by an off-line simulation mode, so that the optimization of the access and memory efficiency is limited, and the problem of limited application scenes exists.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: the invention directly counts the actual memory access address bit turnover rate, avoids the problems of inaccuracy and incompleteness of the traditional method, has the advantages of simple realization, convenient operation and capability of accurately and comprehensively counting the address bit turnover information when the application accesses the memory, and thus can effectively guide the optimization of the address mapping of the memory.

In order to solve the technical problems, the invention adopts the technical scheme that:

a memory access address bit flipping statistical device is characterized by comprising:

the bit flipping monitoring array is mounted on a storage bus of the high-bandwidth memory and used for triggering the access quantity counting of the corresponding storage channel according to each effective access of the storage channel;

the bitwise accumulator array is used for recording the access quantity count of each storage channel;

and the control component is used for enabling and resetting the memory channel access counting module and providing an external access counting reading operation.

Optionally, the bit flipping monitoring array includes N monitoring units, the monitoring units are in one-to-one correspondence with the accumulator and the storage channel, each monitoring unit is configured to trigger a counting operation of the storage channel according to each valid access of the corresponding storage channel, where N is a memory access address bit width.

Optionally, the bitwise accumulator array includes N accumulators, each one-to-one corresponding to a memory channel, the accumulators only need to support an add-1 operation, cancel subsequent accumulations when the accumulation value reaches a maximum value, and hold the maximum value until the accumulators are reset.

In addition, the invention also provides a memory controller which comprises a memory body, wherein the memory body is integrated with or hung with the memory access address bit overturning statistical device.

In addition, the invention also provides a memory, which comprises a memory body with a memory controller, wherein the memory controller is the memory controller.

In addition, the invention also provides a microprocessor, which comprises a processor body with a memory, wherein the memory is the memory.

In addition, the invention also provides a computer device, which comprises a computer device body with a microprocessor, wherein the microprocessor is the microprocessor.

Compared with the prior art, the invention has the following advantages:

1. the invention is independent of the operating system actually operated by the processor, and the statistical precision is not influenced by the address mapping of the operating system and the task scheduling.

2. The invention does not depend on the realization precision and the simulation speed of a simulator, and can accurately and completely count the address turnover information of the target application.

3. The device has simple structure and high operation efficiency.

4. The invention directly counts the actual memory access address bit turnover rate, avoids the problem of inaccuracy and incompleteness of the traditional method, has the advantages of simple realization, convenient operation and capability of accurately and comprehensively counting the address bit turnover information when the application accesses the memory, and thus can effectively guide the optimization of the memory address mapping.

Drawings

FIG. 1 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a bit flipping monitor array structure of an apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram of a bit-wise accumulator array according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a control component of the apparatus according to the embodiment of the present invention.

Detailed Description

As shown in fig. 1, the memory access address bit flipping statistic apparatus of this embodiment includes:

As can be seen from fig. 1, the memory access address bit flipping statistical apparatus of this embodiment is composed of a bitwise accumulator array, a bit flipping monitoring array, and a control unit. The bit overturning monitoring array is directly connected with the access address bus and used for monitoring whether each bit address is overturned or not, and the monitoring result is used for controlling the accumulation operation of the bitwise accumulator array. The control unit is used for enabling and resetting the access address bit flip statistic device and providing read operation for the bitwise accumulator array. During the design process of the processor, the memory access address bit flipping statistic device of the embodiment can be integrated in the memory controller or hung on an address bus of the memory controller as a separate component. As a general matter, each register in the bitwise accumulator array may be treated as a read-only configuration register.

As shown in fig. 2, the bit flipping monitoring array includes N monitoring units, the monitoring units are in one-to-one correspondence with the accumulator and the memory channel, each monitoring unit is configured to trigger a counting operation of the memory channel according to each valid access of the corresponding memory channel, where N is a memory access address bit width. As a general embodiment, the monitoring unit comprises an exclusive-OR circuit and a register for storing the last address bit; the two inputs to the exclusive or circuit are the register and the current address bit, respectively.

As shown in fig. 3, the bitwise accumulator array includes N accumulators, each one-to-one corresponding to a memory channel, the accumulators only need to support an add-1 operation, cancel subsequent accumulations when the accumulation value reaches a maximum value, and hold the maximum value until the accumulators are reset. As a general embodiment, the bit width of the accumulator is 40 bits, and the bit width of the accumulator can be expanded or reduced according to an actual system. As a particular illustration, when the accumulation value reaches a maximum value, subsequent accumulations are cancelled, and the maximum value is maintained until the accumulator is reset. Referring to fig. 2, each monitoring unit is in one-to-one correspondence with an accumulator. The monitoring unit is used for judging whether the current effective address bit is overturned compared with the last effective address bit, and if the current effective address bit is overturned, the corresponding accumulator is added with 1.

As shown in fig. 4, the control unit is mainly used for enabling, resetting and reading control operations of the access address bit flipping statistic device. Where the enable operation is used to turn on the statistics of address bit flips. After the application is executed, the value of the bitwise accumulator array is read through a read operation, and as a general embodiment, the read function is divided into two read modes: 1) batch reading, namely sequentially reading accumulated values of all accumulators; 2) a specific read, i.e. a specific accumulator value specified by the accumulator sequence number is read out independently. After the reading of the accumulated information is completed, the reset operation clears the accumulated value of the accumulator and sets the last address bit value in the bit flipping monitoring unit to be invalid.

In addition, the embodiment further provides a memory controller, which includes a memory body, and the memory body is integrated with or mounted with the above memory access address bit flipping statistical device.

In addition, the embodiment further provides a memory, which includes a memory body with a memory controller, where the memory controller is the aforementioned memory controller.

In addition, the present embodiment further provides a microprocessor, which includes a processor body with a memory, where the memory is the aforementioned memory.

In addition, the embodiment further provides a computer device, which includes a computer device body with a microprocessor, where the microprocessor is the aforementioned microprocessor.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments to equivalent variations, without departing from the scope of the invention, using the teachings disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims

1. A memory access address bit flipping statistical device is characterized by comprising:

2. The memory access address bit flipping statistic device according to claim 1, wherein the bit flipping monitoring array comprises N monitoring units, the monitoring units are in one-to-one correspondence with the accumulator and the memory channel, each monitoring unit is configured to trigger a counting operation of the memory channel according to each valid access of the corresponding memory channel, where N is a memory access address bit width.

3. The memory access address bit flipping statistic device of claim 1, wherein said bit-wise accumulator array comprises N accumulators, each accumulator is in one-to-one correspondence with a memory channel, the accumulator only needs to support an add-1 operation, when the accumulated value reaches a maximum value, the subsequent accumulation is cancelled, and the maximum value is maintained until the accumulator is reset.

4. A memory controller comprises a memory body, and is characterized in that the memory body is integrated with or hung with the memory access address bit reversal statistical device as claimed in any one of claims 1-3.

5. A memory comprising a memory body with a memory controller, wherein the memory controller is the memory controller of claim 4.

6. A microprocessor comprising a processor body with a memory, wherein the memory is the memory of claim 5.

7. A computer device comprising a computer device body having a microprocessor, wherein the microprocessor is the microprocessor of claim 6.