CN115297071A - Fault-tolerant design method for ARINC664 switch engine to SEU and MBU - Google Patents
Fault-tolerant design method for ARINC664 switch engine to SEU and MBU Download PDFInfo
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- H—ELECTRICITY
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- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H04L1/0061—Error detection codes
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Abstract
The invention belongs to the technical field of ARINC664 switches, and discloses a fault-tolerant design method of an ARINC664 switch engine on SEU and MBU, S1, attaching CRC32 check codes in a configuration table, and detecting the integrity of a configuration table file according to the CRC32 check codes; s2, adding an ECC check code for the configuration table parameter of each virtual link written into an SRAM in an ASIC chip of the switching engine, and detecting SEU errors and 2-bit MBU errors of the configuration table according to the ECC check code, so that the switch can correct the SEU errors of the configuration table data and detect the MBU errors of the configuration table data; s3, the SRAM adopts a 4-bit staggered design, and the probability of UE problems caused by SEU errors and MBU errors in the switching function is reduced to a negligible level.
Description
Technical Field
The invention belongs to the technical field of ARINC664 switches, and particularly relates to a SEU and MBU fault-tolerant design method for an ARINC664 switch engine.
Background
Civil airliners have high requirements for the security of avionic systems. Avionics has been developed to date, and IMA (Integrated Modular avinics) based Avionics systems have been implemented on today's mainstream large airliners, such as the model boeing 787 in the united states, the model C919 in chinese business flight, and so on. The IMA system uses ARINC664 (avionics full duplex switched Ethernet) network for data transmission, and ARINC664 switch is a main component of the ARINC664 network, so the IMA system puts higher safety requirements on the ARINC664 switch. One of the safety indexes is an integrity index, and the requirement that the integrity index is less than or equal to 1.0E-6 per hour is provided for the switch, namely the probability that the switch cannot detect the functional failure is less than or equal to 1.0E-6 per hour.
The switching function of the switch assumes the task of data transmission in the avionics system, which performs filtering, policing and forwarding of ARINC664 data frames according to the configuration table. The configuration table contains information of all Virtual Links (VL), each VL includes information of VL ID, input port number, output port number, bandwidth Allocation Gap (BAG), maximum allowable jitter, credit, maximum frame length, minimum frame length, priority, port rate, port buffer depth, port maximum delay, and the like, and approximately 50 bytes are required to store the information. The configuration table is generally stored in a non-volatile memory, such as Flash, to ensure that the configuration table is not lost when power is lost. And reading out the configuration table from the Flash when the switch is powered on, and loading the configuration table into the RAM for the use of the switching function. According to the requirements of the ARINC 664P 7 protocol, a switch supports at least 4096 VLs, and thus the size of a configuration table of a switch is 50 × 4096 (bytes) =1638400 (bits), i.e., the switch needs a RAM space of 1638400 bits to store the configuration table.
The calculation formula of the occurrence probability of SEE according to IEC/TS 62396-1 is as follows:
SEE probability =6000 (n/cm) 2 Hour). Times SEE cross section (cm) 2 Device).
6000 in the formula is the atmospheric neutron flux for the aircraft at 40000 feet and at 45 degrees latitude. For SEU errors, SEE cross-sections are 1E-13cm 2 Perbit, SEE cross section 2E-15cm for MBU error 2 /bit
Therefore, the probability of occurrence of SEU is 6000X 1E-13=6.0E-10 bit-hr, and the probability of occurrence of MBU is 6000X 2E-15=1.2E-11 bit-hr.
The RAM is a single event effect sensitive device, when the RAM is impacted by radiation particles (mainly neutrons for an airplane), an SEU error or an MBU error occurs in the RAM storing the configuration table, and when the switching function continues to use the configuration table with errors to filter, regulate and forward the ARINC664 data frame, the UE problems that the data frame is mistakenly discarded and mistakenly forwarded and the like occur.
The UE probability due to SEU error is: 1638400 × 6.0E-10=9.83e-4 per hour; the probability of a UE due to an MBU error is 1638400 × 1.2E-11=1.97E-4 per hour. Therefore, the switch has a probability of 9.83E-4+1.97E-4=1.18E-3 per hour due to the single event effect, and it can be seen that the probability of the switch exceeds the integrity index of the switch by far 1.0E-6 per hour, and the requirement of the IMA system on the integrity of the switch cannot be met.
Disclosure of Invention
The technical scheme of the invention provides a method for designing the SEU and MBU fault tolerance of an ARINC664 switch engine aiming at the problems in the background technology, so that the switch can correct the SEU error of configuration table data and detect the MBU error of the configuration table data, the probability of UE problems caused by the SEU error and the MBU error in the switching function is reduced to the negligible step, the problem that the switching engine cannot detect errors (undetected error, called UE for short) caused by the SEU error and the MBU error is ensured, and the integrity index of the switch is improved.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme.
A method for designing the fault tolerance of an ARINC664 switch engine to SEU and MBU, wherein a configuration table file of the switch is stored in a Flash memory of the switch, and the method comprises the following steps:
s1, attaching a CRC32 check code to a configuration table, and detecting the integrity of a configuration table file according to the CRC32 check code;
and S2, adding an ECC check code to the configuration table parameters of each virtual link written into the SRAM in the ASIC chip of the switching engine, and detecting SEU errors and 2-bit MBU errors of the configuration table according to the ECC check code.
The technical scheme of the invention has the characteristics and further improvements that:
(1) S1 specifically comprises the following steps:
s11, the configuration table file comprises configuration table parameters and CRC (cyclic redundancy check) codes of the configuration table parameters, and the configuration table files are marked as CRC32 check codes 1;
s12, after the switch is powered on, the management function module reads the CRC32 check code 1 and the configuration table parameters from the configuration table file and writes the configuration table parameters into an SRAM of the switching engine ASIC chip;
s13, recalculating CRC32 check codes for the received configuration table parameters by the switching engine ASIC chip, and recording as CRC32 check codes 2;
and S14, the management function module reads the CRC32 check code 2 from the ASIC chip of the switching engine, and detects the integrity of the configuration table file according to whether the CRC32 check code 1 is equal to the CRC32 check code 2.
(2) In S14, detecting the integrity of the configuration table file according to whether CRC32 check code 1 and CRC32 check code 2 are equal, specifically:
if the configuration table parameters are not equal, the transmission process of the configuration table parameters from the configuration table file to the ASIC chip of the switching engine is wrong, and the switch cannot continue to operate; if the configuration table parameters are not mistakenly transferred from the configuration table file to the ASIC chip of the switching engine, the switch can continue to operate.
(3) The switching engine comprises a switching module and an ECC module; s2 specifically comprises the following steps:
s21, after receiving an ARINC664 data frame, the exchange module firstly reads a VL ID number from the data frame, and then uses the VL ID number to search a corresponding virtual link configuration table parameter in an SRAM of an ASIC chip of the exchange engine;
and S22, reading the configuration table parameters and the corresponding ECC check codes, then checking the read configuration table parameters by the ECC module, correcting single-bit errors, and detecting 2-bit errors.
(4) When the configuration table parameter has a single bit error, the exchange module uses the corrected configuration table parameter to filter, regulate and forward the data frame;
when the configuration table parameter has a 2-bit error, the switching module cannot continue to operate by using the configuration table parameter, and attempts to restart the switch to solve the 2-bit MBU error.
(5) The method further comprises the following steps:
and S3, adding a 4-bit staggered structure for the SRAM in the ASIC chip of the switching engine to store the parameters of the configuration table.
(6) Addresses 0 to 3 in the SRAM correspond to memory cells of four data Q _ A0[0] to Q _ A3[0], and the data of the four memory cells are not arranged continuously, but arranged in an interleaving manner according to the following rule:
Q_A0[0]、Q_A1[0]、Q_A2[0]、Q_A3[0]、
Q_A0[1]、Q_A1[1]、Q_A2[1]、Q_A3[1]、
…
Q_A0[18]、Q_A1[18]、Q_A2[18]、Q_A3[18])。
(7) Assuming that a neutron strikes an adjacent 4-bit memory cell, only 1 bit of each data is affected, thereby correcting data errors according to the step in S2.
According to the technical scheme, the exchange engine can tolerate SEU and MBU errors by CRC checking, ECC checking and adding a 4-bit staggered structure to the SRAM, the problem of the exchanger UE (reduced from 1.18E-3 to 0 per hour) caused by the SEU and MBU errors is solved, and the integrity index of the exchanger is greatly improved.
Drawings
FIG. 1 is a diagram illustrating the transmission of configuration table parameters according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an SRAM storage configuration table parameter and an ECC check code according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the operation of the switch mode according to the embodiment of the present invention;
fig. 4 is a schematic diagram of a MAC layer format of an ARINC664 data frame according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a MAC destination address format according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of SRAM bit interleaved data storage according to an embodiment of the present invention;
fig. 7 is a schematic diagram of an MBU occurrence probability distribution situation according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention aims to provide an SEU and MBU fault-tolerant design method for an ARINC664 switch, so that the switch can correct SEU errors of configuration table data and detect MBU errors of the configuration table data, and the probability of UE problems caused by the SEU errors and the MBU errors in the switching function is reduced to a negligible level.
The first step is as follows: and adding a CRC32 check code (marked as CRC32 check code 1) in the configuration table file, loading the configuration table file into the switching engine by the switch management function, recalculating the CRC32 check code (marked as CRC32 check code 2) of the configuration table file by the switching engine, comparing whether the CRC32 check code 1 and the CRC32 check code 2 are equal or not by the management function, and indicating that the configuration table loaded into the switching engine SRAM is not damaged if the CRC32 check code 1 and the CRC32 check code 2 are equal. This step ensures the initial integrity of the configuration table loaded from Flash to the switching engine ASIC chip.
The exchange function of the exchanger is realized by an exchange engine ASIC chip, and the management function is realized by software. The filtering, policing and forwarding functions within the switching engine operate according to configuration table parameters in the configuration table. The process of passing configuration table parameters from the configuration table file to the switching engine is shown in FIG. 1:
the configuration table file is stored in Flash and includes configuration table parameters and a CRC check code for the configuration table parameters (referred to as CRC32 check code 1). After the switch is powered on, the management function reads the CRC32 check code 1 and the configuration table parameters from the configuration table file and writes the configuration table parameters into the SRAM of the switching engine ASIC chip. The switching engine ASIC chip recalculates the CRC32 check code (referred to as CRC32 check code 2) for the received configuration table parameters. The management function reads the CRC32 check code 2 from the switching engine ASIC chip and compares whether the CRC32 check code 1 and the CRC32 check code 2 are equal. If the configuration table parameters are not equal, the transmission process of the configuration table parameters from the configuration table file to the ASIC chip of the switching engine is wrong, and the switch cannot continue to operate; if the configuration table parameters are not mistakenly transferred from the configuration table file to the ASIC chip of the switching engine, the switch can continue to operate. This step ensures the initial integrity of the configuration table parameters within the switching engine after the switch is powered up.
The second step is that: and adding an ECC check code for the configuration table parameter of each VL written into the SRAM of the switching engine, and performing ECC check when the switching engine reads the configuration table parameter of a certain VL from the SRAM, so that the SEU error of the VL configuration table parameter can be automatically corrected and the 2-bit MBU error can be automatically detected. The problems of SEU errors and 2-bit MBU errors of the configuration table which can occur in the high-altitude operation environment of the ASIC chip of the switching engine are solved;
when the configuration table parameters are stored in the SRAM (see technical solution one), the switching engine ASIC chip of the present invention adds an ECC check code to the configuration table parameters of each VL, and writes the configuration table parameters and the ECC check code into the SRAM together, in a storage manner as shown in fig. 2 (VL 0001 to VL4096 in the figure are only VL numbers, but not VL ID numbers):
after the switching engine receives the ARINC664 data frame, the switching module filters, regulates and forwards the ARINC664 data frame. Fig. 3 is a schematic diagram of the operation of the switching module:
the MAC layer format of ARINC664 data frames is shown in fig. 4: the ARINC664 data frame includes a MAC destination address including a VL ID number, in the specific format shown in fig. 4.
After receiving an ARINC664 data frame, the switching module in fig. 3 reads the VL ID number from the data frame, then uses the VL ID number to look up the corresponding VL configuration table parameter in the SRAM, reads the configuration table parameter and the corresponding ECC check code after finding, and then the ECC module checks the read configuration table parameter. ECC can correct one to two, i.e. can correct single bit errors, detect 2 bit errors:
if the SRAM storing the configuration table parameters is impacted by neutrons and an SEU error occurs, the switching module can detect and automatically correct the single-bit error, and then the switching module uses the corrected configuration table parameters to filter, regulate and forward data frames;
if the SRAM storing the configuration table parameters is impacted by neutrons and a 2-bit MBU error occurs, the switching module can detect the 2-bit MBU error but cannot correct the 2-bit MBU error, the switching module cannot continue to operate by using the configuration table parameters, and the switch is tried to be restarted to solve the 2-bit MBU error;
the fault-tolerant processing method for the SEU error and the 2-bit MBU error of the SRAM in the ASIC chip of the switching engine can ensure that the SEU error and the 2-bit MBU error of the configuration table can not cause the problem of the switch UE. For MBU errors of 3 bits and above, the MBU errors are solved through a third step.
The third step: and adding a 4-bit staggered structure to the SRAM in the ASIC chip of the switching engine for storing the configuration table parameters. This step resolves MBU errors of configuration table 3 bits and above that may occur in a high-altitude operating environment of the switching engine ASIC chip.
The invention designs a 4-bit staggered structure for SRAM in an ASIC chip of a switching engine to store configuration table parameters.
FIG. 5 is a schematic diagram of one of the memory arrays: addresses 0 (A0) to 3 (A3) correspond to memory cells of four data (Q _ A0[0] 18 to Q _ A3[0] 18) which are not arranged in series (Q _ A0[0], Q _ A0[1], Q _ A0[2], …, Q _ A0[18], Q _ A1[0], Q _ A2[1], …, Q _ A3[17], Q _ A3[18 ]), but are arranged in an interleaved manner as (Q _ A0[0], Q _ A1[0], Q _ A2[0], Q _ A3[0], Q _ A0[1], Q _ A1[1], …, Q _ A0[18], Q _ A1[18], Q _ A2[18], Q _ A3[18 ]). The memory locations of the remaining addresses are analogized in turn.
A neutron may only affect a few bits that are physically adjacent, which may cause physical MBU errors. Assuming that a neutron strikes an adjacent 4 bits, memory cells 0_1, 1_1, 4_1, 5_1 in fig. 5 are struck.
The correspondence relationship of the four storage units is as follows:
0_1→Q_A0[1]；
1_1→Q_A1[1]；
4_1→Q_A4[1]；
5_1→Q_A5[1]；
actually, only 1 bit of each data (Q _ A0, Q _ A1, Q _ A4, Q _ A5) is impacted, that is, a physical MBU with 4 bits only causes SEU error of the data, and the data can be automatically corrected by ECC in the second design scheme, so that the problem of the switch UE is not caused.
Similarly, if a neutron hits 4+1=5 bits in at least one row and turns over, it is only possible to cause a 2-bit data MBU error, which can be detected by the ECC in design two, and will not cause a switch UE problem.
Similarly, a neutron needs to hit at least 4+1=9 bits in one row and flip, which may cause a data MBU error of 3 bits. According to the reference of Investigation of Multi-Bit updates in a 150nm Technology SRAM Device published by IEEE TRANSACTIONS NUCLEAR SCIENCE, VOL.52, NO.6, DECEMBER 2005, the proportion of bits that are hit to flip is shown in FIG. 7 for a physical 2,3,4:
as can be seen from fig. 7, the proportion of the case where 9 bits are hit and flipped is very low and can be ignored completely. Therefore, after the SRAM in the ASIC chip of the switching engine adopts 4-bit staggered design, the MBU error of 3 bits or more of the configuration table parameters of a certain VL in the SRAM can be ignored.
Through the three steps of the invention, the switching engine can tolerate the SEU and MBU errors, the problem of the switch UE (reduced from 1.18E-3 to 0 per hour) caused by the SEU and MBU errors is eliminated, and the integrity index of the switch is greatly improved.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (8)
1. A method for designing SEU and MBU fault tolerance of ARINC664 switch exchange engine, which is characterized in that a configuration table file of a switch is stored in a Flash memory of the switch, and the method comprises the following steps:
s1, attaching a CRC32 check code to a configuration table, and detecting the integrity of a configuration table file according to the CRC32 check code;
and S2, adding an ECC check code to the configuration table parameters of each virtual link written into the SRAM in the ASIC chip of the switching engine, and detecting SEU errors and 2-bit MBU errors of the configuration table according to the ECC check code.
2. The method for fault tolerance design of the ARINC664 switch engine on SEU and MBU according to claim 1, wherein S1 is specifically:
s11, the configuration table file comprises configuration table parameters and CRC (cyclic redundancy check) codes of the configuration table parameters, and the configuration table files are marked as CRC32 check codes 1;
s12, after the switch is powered on, the management function module reads the CRC32 check code 1 and the configuration table parameters from the configuration table file, and writes the configuration table parameters into an SRAM of an ASIC chip of the switching engine;
s13, recalculating CRC32 check codes for the received configuration table parameters by the switching engine ASIC chip, and recording as CRC32 check codes 2;
and S14, the management function module reads the CRC32 check code 2 from the ASIC chip of the switching engine, and detects the integrity of the configuration table file according to whether the CRC32 check code 1 is equal to the CRC32 check code 2.
3. The method according to claim 2, wherein in S14, the integrity of the configuration table file is detected according to whether CRC32 check code 1 and CRC32 check code 2 are equal, specifically:
if the configuration table parameters are not equal, the transmission process of the configuration table parameters from the configuration table file to the ASIC chip of the switching engine is wrong, and the switch cannot continue to operate; if the configuration table parameters are not mistakenly transferred from the configuration table file to the ASIC chip of the switching engine, the switch can continue to operate.
4. The method of claim 1, wherein the ARINC664 switch engine is designed to be fault tolerant to SEU and MBU, and comprises a switch module and an ECC module; s2 specifically comprises the following steps:
s21, after receiving an ARINC664 data frame, the exchange module firstly reads a VL ID number from the data frame, and then uses the VL ID number to search a corresponding virtual link configuration table parameter in an SRAM of an ASIC chip of the exchange engine;
and S22, reading the configuration table parameters and the corresponding ECC check codes, then checking the read configuration table parameters by the ECC module, correcting single-bit errors, and detecting 2-bit errors.
5. The ARINC664 switch engine SEU and MBU fault tolerant design method of claim 4,
when the configuration table parameter has a single bit error, the exchange module uses the corrected configuration table parameter to filter, regulate and forward the data frame;
when the configuration table parameter has a 2-bit error, the switching module cannot continue to operate by using the configuration table parameter, and attempts to restart the switch to solve the 2-bit MBU error.
6. The method of claim 1, wherein the ARINC664 switch engine design for SEU and MBU fault tolerance further comprises:
and S3, adding a 4-bit staggered structure for the SRAM in the ASIC chip of the switching engine to store the parameters of the configuration table.
7. The method for designing the ARINC664 switch exchange engine for SEU and MBU fault tolerance according to claim 6, wherein the addresses 0 to 3 in the SRAM correspond to the storage units of four data Q _ A0[0] to Q _ A3[18], and the data of the four storage units are not arranged continuously, but are arranged in an interleaving way according to the following rule:
Q_A0[0]、Q_A1[0]、Q_A2[0]、Q_A3[0]、
Q_A0[1]、Q_A1[1]、Q_A2[1]、Q_A3[1]、
…
Q_A0[18]、Q_A1[18]、Q_A2[18]、Q_A3[18])。
8. the method of claim 7, wherein if a neutron strikes an adjacent 4-bit storage unit, each data has only 1 bit affected, thereby correcting data errors according to the steps in S2;
assuming that a neutron strikes a row of 9 bits in the SRAM to cause a 3-bit data MBU error, the probability of the 9 bits being hit is negligible, and thus the 3-bit and above data MBU errors are negligible.
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