CN114065692A - Memory bitmap analysis method and system based on single event effect - Google Patents

Memory bitmap analysis method and system based on single event effect Download PDF

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CN114065692A
CN114065692A CN202111322447.7A CN202111322447A CN114065692A CN 114065692 A CN114065692 A CN 114065692A CN 202111322447 A CN202111322447 A CN 202111322447A CN 114065692 A CN114065692 A CN 114065692A
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sub
byte
single event
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郭金龙
杜广华
毛光博
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Institute of Modern Physics of CAS
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    • G06F30/30—Circuit design
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    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
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Abstract

The invention relates to a single event effect-based memory bitmap analysis method and a single event effect-based memory bitmap analysis system, which are characterized by comprising the following steps of: acquiring single event effect multi-bit upset data of a memory chip to be analyzed; judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data; the invention can obtain the memory interleaving type with high reliability at lower cost, and can be widely applied to the field of integrated circuits.

Description

Memory bitmap analysis method and system based on single event effect
Technical Field
The invention relates to the field of integrated circuits, in particular to a memory bitmap analysis method and system based on a single event effect.
Background
In the earth's near-earth space and universe, there is a harsh ion radiation environment, and the incidence of such energetic ions to the integrated circuit of a satellite or spacecraft may induce a Single Event Effect (SEE) to occur to the device, and cause the malfunction of the logic circuit and even the burning of the device. The memory is an indispensable composition structure of the integrated circuit, but the devices are susceptible to a single event effect, namely Single Event Upset (SEU), and the single event upset occurring in the memory can cause logic disorder of the integrated circuit system, thereby affecting the functional realization of the integrated circuit.
The design of the bit interleaving structure can efficiently detect and correct the single event upset effect (SEU) of the memory with the aid of an error correction algorithm (ECC), thereby greatly improving the stability of the integrated circuit system. Because the selection and design of the bit interleaving structure are not mature standards, the bit interleaving structure of a mature commercial device is analyzed and researched, and the research and development of a high-performance device and the construction of a high-reliability system are facilitated. The hardware reverse and microbeam error injection attack is a key means for analyzing the current memory bit interleaving technology, but the manpower and material resource investment is quite large, and great difficulty exists in actual implementation.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a method and a system for analyzing a memory bitmap based on a single event effect, which can economically and efficiently extract interleaving structure information of a memory device.
In order to achieve the purpose, the invention adopts the following technical scheme: in a first aspect, a single event effect-based memory bitmap parsing method is provided, including:
acquiring single event effect multi-bit upset data of a memory chip to be analyzed;
judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data;
and judging the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes.
Further, the acquiring single event effect multi-bit upset data of the memory chip to be analyzed includes:
writing a preset data structure into a memory chip to be analyzed;
carrying out irradiation attack on a memory chip to be analyzed;
reading single event effect multi-bit upset data stored in a memory chip to be analyzed according to the logic address;
and repeating the steps until the single event effect multi-bit upset data with the preset number in each written data state is obtained.
Further, the determining the structure of the sub-byte according to the acquired single event effect multi-bit upset data includes:
judging the boundary of the sub-byte according to the acquired single event effect multi-bit upset data;
and judging the length of the sub-byte according to the acquired single event effect multi-bit upset data and the judged boundary of the sub-byte.
Further, the determining the boundary of the sub-byte according to the acquired single event effect multi-bit upset data includes:
screening single-event-effect multi-bit upset data MCU (microprogrammed control Unit) which is induced in a memory chip to be analyzed by single ions and only comprises two bits and belongs to different logic words according to the acquired single-event-effect multi-bit upset data;
determining all MCUs comprising specified number bits, wherein the bits are considered to be adjacent to a specified bit space; calculating the difference value of the word logic addresses of two bits in the MCU as the MCU interval;
counting the number of all MCU intervals of the designated number bits;
and if the MCU interval number is more than 1, judging that the bit of the specified number is at the boundary position of the sub-byte.
Further, the determining the length of the sub-byte according to the acquired single event effect multi-bit upset data and the determined boundary of the sub-byte includes:
screening single-event-effect multi-bit upset data MBU (minimum byte count) induced by a single ion in a memory chip to be analyzed, wherein the single-event-effect multi-bit upset data MBU only comprises two bits which belong to the same logic word;
determining all MBUs including the bits of the specified number;
counting all bits belonging to the same MBU event as the designated bit, wherein the bits are regarded as adjacent to the designated bit space;
sequentially connecting any two boundary bits in series into a column or a row through the adjacent relation obtained by the MBU event to form a sub-byte, wherein the length of the sub-byte is the number of the bits included in the sub-byte; or, according to the condition that the adjacent bit found out for a boundary bit comes from 8 different logic words, the bit is directly determined to be an independent sub-byte with the length of 1.
Further, the determining the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes includes:
if the length of the sub-byte is equal to the length of the logic word of the memory chip to be analyzed, the bitmap of the memory chip to be analyzed is in a non-staggered structure;
if the length of the sub-byte is smaller than the length of the logic word of the memory chip to be analyzed, the bitmap of the memory chip to be analyzed is in a staggered structure.
Further, the determining the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes further includes:
if the length of the sub-byte is larger than 1, the bitmap of the memory chip to be analyzed is a bit interleaving structure;
if the length of the sub-byte is equal to 1, the bitmap of the memory chip to be analyzed is a bit-interleaved structure.
In a second aspect, a single event effect-based memory bitmap parsing system is provided, including:
the data acquisition module is used for acquiring single event effect multi-bit upset data of the memory chip to be analyzed;
the sub-byte length judging module is used for judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data;
and the interleaving type judging module is used for judging the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes.
In a third aspect, a processing device is provided, which includes computer program instructions, where the computer program instructions, when executed by the processing device, are configured to implement the steps corresponding to the above memory bitmap parsing method based on the single event effect.
In a fourth aspect, a computer-readable storage medium is provided, where computer program instructions are stored on the computer-readable storage medium, and when the computer program instructions are executed by a processor, the computer program instructions are used to implement the steps corresponding to the above memory bitmap analysis method based on the single event effect.
Due to the adoption of the technical scheme, the invention has the following advantages: the traditional hardware reverse technology generally needs to peel off a metal wiring layer and a semiconductor doping sensitive layer of a chip layer by layer and extract an optical image, and then obtains a design structure in a device through positioning analysis of metal wiring and a storage unit position, the common research period is from several months to several years, and the input research cost is high. The high-resolution microbeam error injection attack technology needs to completely depend on an accelerator microbeam device and is limited by self-space resolution precision and accelerator time. Compared with the traditional research means, the method does not need to depend on a large-scale experimental device, has great experimental flexibility and economic applicability, can ensure the accuracy and credibility of results, and can be widely applied to the field of integrated circuits.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Like reference numerals refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart of a method provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of an analysis model of a memory structure according to an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless specifically identified as an order of performance. It should also be understood that additional or alternative steps may be used.
The core of the memory bitmap analysis method and system based on the single event effect provided by the embodiment of the invention is to determine the length of the memory chip sub-byte and compare the length with the length of the memory chip logic word so as to judge whether the bitmap of the memory chip adopts the staggered structure layout or the type of the staggered layout, so that the memory staggered type with high reliability can be obtained at a low cost, the memory bitmap analysis method and system can be further used for providing important parameters such as the staggered interval, the distribution of address blocks and the like, and an economic and applicable research means can be provided for the research and technical development of the memory staggered structure.
Example 1
As shown in fig. 1, the present embodiment provides a method for analyzing a memory bitmap based on a single event effect, which includes the following steps:
1) acquiring single event effect multi-bit upset data of a memory chip to be analyzed, specifically:
1.1) writing a preset data structure into a memory chip to be analyzed.
Specifically, the data structure is, for example: all storage bits are written with the same data (0 or 1), or adjacent bits are written with different data (logical adjacent bits are written with 0\1 or 1\ 0).
1.2) carrying out irradiation attack on the memory chip to be analyzed by adopting an ion radiation device.
Specifically, the ion irradiation device may employ a radiation source, an accelerator ion, a laser, or the like.
1.3) reading single event effect multi-bit upset data stored in a memory chip to be analyzed according to the logic address to be used as stream disk recording.
1.4) entering the step 1.1) until a preset number of single event effect multi-bit upset data in each written data state are obtained.
2) Judging the structure of a sub-byte according to the acquired single event effect multi-bit upset data, wherein the sub-byte refers to a minimum structure unit formed by continuous and adjacent bits in the same word, and the method specifically comprises the following steps:
2.1) judging the boundary of the sub-byte according to the acquired single event effect multi-bit upset data:
2.1.1) screening single-event-effect multi-bit upset data (MCU) which are induced in a memory chip to be analyzed by single ions and only comprise two bits and belong to different logic words according to the obtained single-event-effect multi-bit upset data.
2.1.2) determines that all bits include the specified number (e.g.: and the MCU of the bit 1) calculates the difference value of the word logic addresses of the two bits in the MCU as the MCU interval.
2.1.3) count the number of all MCU slots for the specified number bits.
2.1.4) if the MCU interval number is more than 1, judging that the bit of the specified number is at the boundary position of the sub-byte.
Specifically, all numbered bits within the logical word length of the memory chip to be resolved need to perform the operation of step 2.1) above.
2.2) judging the length of the sub-byte according to the acquired single event effect multi-bit upset data and the judged boundary of the sub-byte:
2.2.1) according to the obtained single event effect multi-bit upset data, screening single event effect multi-bit upset data (MBU) which only comprises two bits and belongs to one logic word and is induced in a memory chip to be analyzed by a single ion.
2.2.2) determines that all bits including the specified number (e.g.: bit 1).
2.2.3) count all bits belonging to the same MBU event as the specified bit.
2.2.4) sequentially connecting adjacent bit relations of any two boundary bits obtained by MBU events in series into a column or a row to form a sub-byte, wherein the length of the sub-byte is the number of the bits included in the sub-byte; or, according to the condition that the adjacent bit found out for a boundary bit comes from 8 different logic words, the bit is directly determined to be an independent sub-byte with the length of 1.
It should be noted that two bits in the MCU and the MBU events excited by the same ion are adjacent in physical layout.
As shown in fig. 2, which is an analytic model of a memory structure, wherein each box represents a single bit, the same group of bits represents a sub-byte, biIs the middle bit of the sub-byte (adjacent to the upper and lower sub-bytes and the number of MCU spaces is equal to 1), bbIs the boundary bit of the sub-byte (adjacent to at least 5 sub-bytes, the number of MCU slots is more than 1).
3) According to the structure of the sub-bytes, judging the interleaving type of the memory chip to be analyzed, specifically:
3.1) if the length of the sub-byte is equal to the length of the logic word of the memory chip to be analyzed, the bitmap of the memory chip to be analyzed is in a non-staggered structure.
3.2) if the length of the sub-byte is less than the length of the logic word of the memory chip to be analyzed, the bitmap of the memory chip to be analyzed is in a staggered structure.
Specifically, if the length of the sub-byte is greater than 1, the bitmap of the memory chip to be analyzed is a bit interleaving structure; if the length of the sub-byte is equal to 1, the bitmap of the memory chip to be analyzed is a bit-interleaved structure.
The memory bitmap analysis method based on the single event effect is explained in detail by the following specific embodiments:
s1, acquiring single event effect multi-bit upset data of the memory chip to be analyzed:
firstly, a development board with the model number of DE2-115 FPGA is used as an upper computer, hexadecimal data 00, FF, 55 and AA are written into all addresses of a memory chip to be analyzed according to groups, and the addresses are stored to be analyzedThe length of a single logic word of the memory chip is 8 bits, and the total length is 215A word address.
② adopt252The Cf radiation source irradiates and attacks the unsealed memory chip.
Reading out single event effect multi-bit upset data stored in the memory chip to be analyzed according to the logic address, and transmitting the data to the personal computer for stream disk recording.
And fourthly, entering the step one until the single event effect multi-bit upset data under the state of writing the data with the preset number are obtained.
S2, judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data:
determining the boundary point of the sub-byte according to the acquired single event effect multi-bit upset data: and the statistical data show that the MCU interval numbers of eight bits (bit 0 to bit 7) of the memory chip are all larger than 1, and the bit 0 to the bit 7 are all the boundaries of the sub-bytes.
Judging the length of the sub-byte according to the acquired single event effect multi-bit upset data: statistical data indicate that MBUs exist only between bits 0/1, 2/3, 4/5, and 6/7, bits 0/1, 2/3, 4/5, and 6/7 are determined to be adjacent, respectively.
Meanwhile, bit 0 and bit 1 are boundary bits of a sub-byte and can be concatenated using the adjacent relationship obtained by the MBU, so that bit 0/1 is obtained to form a sub-byte, and the length of the sub-byte is 2. In addition, bits 2/3, 4/5, and 6/7 constitute the other three bytes, respectively, which are also 2 in length.
S3, judging the interleaving type of the memory chip to be analyzed according to the length of the sub-bytes:
length (2 bit) of sub byte is smaller than length (8 bit) of logic word of memory chip to be analyzed, then bit map of memory chip to be analyzed is staggered structure; meanwhile, if the length of the sub-byte is larger than 1 bit, the bitmap of the memory chip is determined to be a bit interleaving structure with 2 bits of the sub-byte.
Example 2
The embodiment provides a memory bitmap analysis system based on a single event effect, which comprises:
and the data acquisition module is used for acquiring single event effect multi-bit upset data of the memory chip to be analyzed.
And the sub-byte length judging module is used for judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data.
And the interleaving type judging module is used for judging the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes.
Example 3
This embodiment provides a processing device corresponding to the single event effect-based memory bitmap parsing method provided in embodiment 1, where the processing device may be a processing device for a client, such as a mobile phone, a notebook computer, a tablet computer, a desktop computer, and the like, to execute the method of embodiment 1.
The processing equipment comprises a processor, a memory, a communication interface and a bus, wherein the processor, the memory and the communication interface are connected through the bus so as to complete mutual communication. The memory stores a computer program that can be run on the processing device, and the processing device executes the method for analyzing the memory bitmap based on the single event effect provided in this embodiment 1 when running the computer program.
In some implementations, the Memory may be a high-speed Random Access Memory (RAM), and may also include a non-volatile Memory, such as at least one disk Memory.
In other implementations, the processor may be various general-purpose processors such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), and the like, and is not limited herein.
Example 4
The present embodiment provides a computer program product corresponding to the single event effect-based memory bitmap analysis method provided in this embodiment 1, and the computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing the single event effect-based memory bitmap analysis method described in this embodiment 1 are loaded.
The computer readable storage medium may be a tangible device that retains and stores instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any combination of the foregoing.
The above embodiments are only used for illustrating the present invention, and the structure, connection mode, manufacturing process, etc. of the components may be changed, and all equivalent changes and modifications performed on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.

Claims (10)

1. A memory bitmap analysis method based on a single event effect is characterized by comprising the following steps:
acquiring single event effect multi-bit upset data of a memory chip to be analyzed;
judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data;
and judging the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes.
2. The single event effect-based memory bitmap analysis method according to claim 1, wherein the obtaining of the single event effect multi-bit upset data of the memory chip to be analyzed comprises:
writing a preset data structure into a memory chip to be analyzed;
carrying out irradiation attack on a memory chip to be analyzed;
reading single event effect multi-bit upset data stored in a memory chip to be analyzed according to the logic address;
and repeating the steps until the single event effect multi-bit upset data with the preset number in each written data state is obtained.
3. The single event effect-based memory bitmap analysis method according to claim 1, wherein the determining the structure of the sub-byte according to the acquired single event effect multi-bit upset data comprises:
judging the boundary of the sub-byte according to the acquired single event effect multi-bit upset data;
and judging the length of the sub-byte according to the acquired single event effect multi-bit upset data and the judged boundary of the sub-byte.
4. The single event effect-based memory bitmap analysis method according to claim 3, wherein the determining the boundary of the sub-byte according to the acquired single event effect multi-bit upset data comprises:
screening single-event-effect multi-bit upset data MCU (microprogrammed control Unit) which is induced in a memory chip to be analyzed by single ions and only comprises two bits and belongs to different logic words according to the acquired single-event-effect multi-bit upset data;
determining all MCUs including the specified number bits, and calculating the difference value of the word logic addresses of the two bits in the MCUs to serve as the MCU interval;
counting the number of all MCU intervals of the designated number bits;
and if the MCU interval number is more than 1, judging that the bit of the specified number is at the boundary position of the sub-byte.
5. The single event effect-based memory bitmap analysis method according to claim 4, wherein the determining the length of the sub-byte according to the acquired single event effect multi-bit upset data and the determined boundary of the sub-byte comprises:
screening single-event-effect multi-bit upset data MBU (minimum byte count) induced by a single ion in a memory chip to be analyzed, wherein the single-event-effect multi-bit upset data MBU only comprises two bits which belong to the same logic word;
determining all MBUs including the bits of the specified number;
counting all bits belonging to the same MBU event with the designated bit;
sequentially connecting any two boundary bits in series into a column or a row through the adjacent relation obtained by the MBU event to form a sub-byte, wherein the length of the sub-byte is the number of the bits included in the sub-byte; or, according to the condition that the adjacent bit found out for a boundary bit comes from different logic words, the bit is directly determined to be an independent sub-byte with the length of 1.
6. The method for analyzing the memory bitmap based on the single event effect according to claim 1, wherein the determining the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes comprises:
if the length of the sub-byte is equal to the length of the logic word of the memory chip to be analyzed, the bitmap of the memory chip to be analyzed is in a non-staggered structure;
if the length of the sub-byte is smaller than the length of the logic word of the memory chip to be analyzed, the bitmap of the memory chip to be analyzed is in a staggered structure.
7. The single event effect-based memory bitmap analysis method of claim 6, wherein the determining the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes further comprises:
if the length of the sub-byte is larger than 1, the bitmap of the memory chip to be analyzed is a bit interleaving structure;
if the length of the sub-byte is equal to 1, the bitmap of the memory chip to be analyzed is a bit-interleaved structure.
8. A single event effect-based memory bitmap parsing system, comprising:
the data acquisition module is used for acquiring single event effect multi-bit upset data of the memory chip to be analyzed;
the sub-byte length judging module is used for judging the structure of the sub-byte according to the acquired single event effect multi-bit upset data;
and the interleaving type judging module is used for judging the interleaving type of the memory chip to be analyzed according to the structure of the sub-bytes.
9. A processing device comprising computer program instructions, wherein said computer program instructions, when executed by a processing device, are adapted to implement the corresponding steps of the single event effect based memory bitmap parsing method according to any one of claims 1-7.
10. A computer readable storage medium, having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, are configured to implement the corresponding steps of the single event effect based memory bitmap parsing method according to any one of claims 1-7.
CN202111322447.7A 2021-11-09 2021-11-09 Memory bitmap analysis method and system based on single event effect Pending CN114065692A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115297071A (en) * 2022-07-15 2022-11-04 中国航空无线电电子研究所 Fault-tolerant design method for ARINC664 switch engine to SEU and MBU

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115297071A (en) * 2022-07-15 2022-11-04 中国航空无线电电子研究所 Fault-tolerant design method for ARINC664 switch engine to SEU and MBU
CN115297071B (en) * 2022-07-15 2023-10-27 中国航空无线电电子研究所 Fault-tolerant design method for SEU and MBU by switch engine of ARINC664 switch

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