CN113254252A

CN113254252A - Satellite load FPGA with BRAM and use method thereof

Info

Publication number: CN113254252A
Application number: CN202110739414.6A
Authority: CN
Inventors: 孙鹏跃; 黄仰博; 刘旭辉; 毛二坤; 楼生强; 张书政; 周欢; 唐小妹
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2021-08-13
Anticipated expiration: 2041-07-01
Also published as: CN113254252B

Abstract

The invention provides a satellite load FPGA with BRAM and a using method thereof, wherein the satellite load FPGA comprises: the input of the internal algorithm module is correct output data after passing through the three-module voting module, and the internal algorithm module is used for processing the satellite load FPGA configuration item; the three-module voting module acquires data output by the three-module BRAM and carries out three-module redundancy voting; and the BRAM and self-refresh module is used for storing the on-track parameters and controlling the self-refresh of the on-track parameters. According to the satellite load FPGA, the self-refreshing function of the BRAM can be completed without intervention of an external processor, and the problems that the traditional BRAM irradiation-resistant reinforcing method consumes more resources, and the processor access conflict risk is high can be solved. The problem that the BRAM causes errors of satellite load FPGA data due to accumulation of single event upset is solved.

Description

Satellite load FPGA with BRAM and use method thereof

Technical Field

The invention relates to the field of FPGA space reliability, in particular to a satellite load FPGA with BRAM and a use method thereof.

Background

The SRAM type FPGA contains rich BRAM storage resources, is the most common IP core in a satellite-borne FPGA configuration item, is widely applied to data caching, parameter storage and the like, and can realize functions of a single-port memory, a double-port memory, FIFO and the like. The BRAM is the highest probability of single particle occurrence in the user logic of the satellite-borne FPGA, and accounts for 2.9%. However, since the data stored in the BRAM is always in dynamic application, it is difficult to implement a timing refresh design of similar configuration data, and therefore, the single event upset accumulated in the BRAM is difficult to eliminate.

The spatial single event effect of SRAM type FPGAs can be mainly classified into three categories: configuration memory roll-over, user logic roll-over, and control unit roll-over. The configuration memory turnover accounts for more than 90% of single event turnover events in all spaces, has great influence on load configuration items, is the key point of load irradiation-resistant design, and forms a series of irradiation-resistant design methods. For a user logic part, the probability of single event upset is high, the part is closely related to user design, a systematic anti-irradiation reinforcement design method is difficult to form, and the part gradually becomes a bottleneck of space load anti-irradiation design at present. Particularly, the BRAM memory is difficult to eliminate accumulation of space single event upset through traditional refresh operation because the stored data of the BRAM memory is always in dynamic application, and is one of the main reasons for the current SRAM type FPGA space single event upset events.

For a data cache class BRAM, although BRAM data is an intermediate result and can be automatically repaired by an algorithm after a certain time, the BRAM data error period has an influence on the subsequent data flow of the algorithm. For the parameter storage BRAM, a user requires that data in the BRAM are kept unchanged, but under the condition of space irradiation, even if the parameter storage BRAM is subjected to triple modular redundancy, data errors caused by single particle accumulation cannot be solved. Therefore, in the strengthening of the on-board configuration item BRAM, a corresponding single-particle accumulation elimination method must be designed to ensure the correctness of data.

The traditional single event effect elimination method mainly comprises two types of refreshing and error correction coding. For refresh, a common architecture is shown in fig. 1, and it can be seen that, in the conventional refresh architecture, refreshing of data in the BRAM is mainly completed by an external processor, this scheme needs to occupy one port of a dual-port BRAM separately, which is equivalent to that BRAM resource consumption is increased by 1 time, and there is a possibility that external processor refresh conflicts with internal algorithm access. In the prior art, CN112015584A belongs to a conventional refresh architecture, which mainly completes the refresh of data in a BRAM through an external processor, and needs to occupy one port of a dual-port BRAM separately, which is equivalent to that the BRAM resource consumption is increased by 1 time, and there is a possibility that the refresh of the external processor conflicts with the access of an internal algorithm. The error correction coding method is to code the data written in the BRAM and decode the data when reading. For example, a commonly used BRAM reinforcement method based on EDAC coding does not occupy a BRAM port independently, so that resource waste of the BRAM is reduced, but single event upset of data in the BRAM is not corrected fundamentally, only 2-bit errors can be detected and 1-bit errors can be corrected when the BRAM data are used, and along with time accumulation, when the data in the BRAM have multi-bit errors, the error correction coding method fails.

The error correction coding method is to encode the data written in the BRAM and decode the data when reading. A commonly used BRAM data error correction architecture based on EDAC coding is shown in fig. 2. The error correction coding method does not occupy the BRAM port independently and can not cause the waste of BRAM resources, but the error correction coding method does not fundamentally correct the single event upset of the data in the BRAM, only can detect 2-bit errors and correct 1-bit errors when the BRAM data is used, but along with the accumulation of time, when the data in the BRAM has multi-bit errors, the error correction coding method fails.

The simplest fault-tolerant design of the BRAM memory is to directly carry out triple modular redundancy and finally output the triple modular redundancy through a majority voter, but the capacity of the BRAM memory is increased by 3 times along with the increase of the number of the BRAM memory and the improvement of the reading rate, and the complexity of the control sequence of the BRAM memory is also increased. Another method is error detection and correction coding (EDAC) technology such as Hamming codes and RS codes, which is suitable for correcting and detecting bit flipping in memories by adding redundant bits to solve the radiation resistance of data, for example, (13, 8) Hamming codes can effectively correct one to two errors, RM (2, 5) codes can correct 3-bit random errors and detect 4-bit errors. However, because the EDAC module does not have the radiation resistance, the encoding and decoding circuits may generate single event upset, which causes errors of encoded or decoded data, and therefore, the design of triple modular redundancy reinforcement for the EDAC module can also be considered. However, in the current satellite-borne key electronic equipment, the contradiction of balancing the system reliability and the performance resource becomes a new requirement of the radiation-resistant design of the satellite-borne FPGA.

Disclosure of Invention

In order to solve the technical problems, the invention provides a satellite load FPGA with a BRAM and a use method thereof, which are used for solving the problem that the BRAM used for data storage and parameter storage in the prior art is difficult to eliminate due to the accumulation of single event upset, so that the data of the satellite load FPGA is wrong.

According to a first aspect of the invention, there is provided a satellite payload FPGA with a BRAM, the FPGA comprising:

the system comprises an internal algorithm module, a three-module voting module, a BRAM and a self-refreshing module, wherein:

the input of the internal algorithm module is correct output data after passing through the triple-module voting module, namely, the BRAM data subjected to triple-module redundancy voting is obtained by performing read-write operation on the data stored in the BRAM and is used for processing and calculating the satellite load FPGA configuration item;

the three-module voting module acquires data with the same content output by the three-module BRAM, votes the data by a majority decision device, and can shield the error of the fault module and ensure correct output as long as two same errors do not occur at the same position of the three BRAM modules at the same time;

the BRAM and self-refresh module is used for storing the on-track parameters and controlling the self-refresh of the on-track parameters;

the BRAM and self-refresh module comprises an algorithm monitoring module, a self-refresh control module, a BRAM storage module and a time division multiplexing module;

the algorithm monitoring module is used for monitoring a satellite load FPGA functional algorithm accessing the BRAM and identifying an idle state accessed by the BRAM;

the self-refresh control module is used for realizing the state switching of the BRAM between the self-refresh operation and the internal algorithm access and controlling the traversal self-refresh of the whole BRAM;

the BRAM storage module is used for storing on-track parameters and read-write access;

the time division multiplexing module is used for realizing time division multiplexing control of the BRAM on two branches of self-refreshing operation and internal algorithm access according to the monitoring result of the algorithm monitoring module, and when the internal algorithm accesses the BRAM, namely the internal algorithm module is in a busy state, the internal algorithm access branch is used for realizing read-write access of the BRAM; when the internal algorithm module is in an idle state, the self-refresh of the BRAM is realized through the self-refresh control branch circuit, so that the on-track single event upset accumulation is eliminated.

According to a second aspect of the invention, a method for using a satellite payload FPGA with a BRAM is provided, the method comprising the following steps:

step S401: the internal algorithm module configures configuration items of the satellite load FPGA;

step S402: the internal algorithm generates control signals for reading the BRAM, votes the read data of the three BRAMs through the three-mode voting module, and corrects the single event upset accumulated error;

step S403: and the BRAM and self-refreshing module writes back the data after the resolution is passed, and the single event accumulated error stored in the BRAM storage module is eliminated.

According to the scheme of the invention, the algorithm monitoring module and the self-refreshing control module are added in the satellite load FPGA to accurately detect the idle state of the BRAM accessed by the internal algorithm, and the data after triple modular redundancy voting is written back by adopting a time division multiplexing mode, so that the time-sharing refreshing of the BRAM is realized, the problem of data errors caused by the accumulation of single particles of the BRAM in a space irradiation environment is solved, the irradiation resistance reliability of the BRAM can be effectively improved aiming at the reinforcement of the satellite load configuration item BRAM, the irradiation resistance reinforcement design of the satellite load FPGA is more comprehensively completed, the correctness of the data is ensured, and the feasibility and the popularization value are good.

The invention can complete the self-refreshing function of the BRAM without the intervention of an external processor, and can solve the problems of more resource consumption, processor access conflict risk and the like of the traditional BRAM irradiation-resistant reinforcement method. The problem that the BRAM causes the data error of the satellite load FPGA due to the accumulation of single event upset is solved, and a new solution is provided for further perfecting the anti-irradiation reinforcement design of the satellite load FPGA; a BRAM port does not need to be occupied independently, so that resource waste is reduced; the internal algorithm monitoring module ensures that the BRAM refreshing is executed in an idle state, thereby avoiding the BRAM access conflict. Compared with the prior art CN112015584A, the self-refresh in the prior art is stand-alone self-refresh, the stand-alone comprises a DSP and an FPGA, the DSP and the FPGA are matched for refresh, the BRAM in the FPGA is refreshed through the DSP, not only more BRAM resources are occupied, but also the problem of conflict between internal access and DSP access is caused; the self-refresh of the invention is only the self-refresh of the FPGA, the reliability is higher, the resources are saved and the invention is more universal.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of a method for eliminating a single particle accumulation effect by a refresh method in the prior art;

FIG. 2 is a diagram illustrating a method for eliminating single particle accumulation effect by error correction coding in the prior art;

FIG. 3 is a schematic structural diagram of a satellite payload FPGA with a BRAM according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating state transitions of a self-refresh control module according to an embodiment of the present invention;

FIG. 5 is a flow chart illustrating a self-refresh method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

A satellite payload FPGA with BRAMs is first described in conjunction with fig. 3 as one embodiment of the present invention. The satellite load FPGA comprises an internal algorithm module, a three-module voting module, a BRAM and a self-refreshing module, wherein:

and the BRAM and self-refresh module is used for storing the on-track parameters and controlling the self-refresh of the on-track parameters.

The internal algorithm module performs read-write operation on the data stored in the BRAM, and comprises the following steps: when the BRAM writing operation is carried out, a BRAM writing address and a data control signal are generated; when the BRAM reading operation is carried out, a BRAM reading address control signal is generated, and BRAM data subjected to three-mode voting is obtained and used for operation.

The triple-module voting module acquires data output by a triple-module BRAM (Block-based redundancy management) and carries out triple-module redundancy voting, and the triple-module redundancy voting comprises the following steps:

and acquiring the output data of the three-mode BRAM as the input of the three-mode voting module, and taking the output with the same majority as the correct output of the three-mode voting module. In this embodiment, as long as two data errors at the same position do not occur simultaneously in three BRAMs, the error of the fault module can be shielded, and the correct output of the system is ensured.

and the time division multiplexing module is used for realizing the time division multiplexing control of the BRAM on the two branches of self-refresh operation and internal algorithm access according to the monitoring result of the algorithm monitoring module.

When the rising edge of the clock comes and the enabling end of the BRAM memory module is at a high level, the BRAM memory module reads or writes data stored in the BRAM memory module under the action of the read-write control signal.

The time division multiplexing module is used for realizing time division multiplexing control of the BRAM on two branches of self-refresh operation and internal algorithm access according to the monitoring result of the algorithm monitoring module, wherein:

when the internal algorithm accesses the BRAM, namely the internal algorithm module is in a busy state, the read-write access of the BRAM is realized through the internal algorithm access branch; when the internal algorithm module is in an idle state, the self-refresh of the BRAM is realized through the self-refresh control branch circuit, so that the on-track single event upset accumulation is eliminated.

In this embodiment, by setting the algorithm monitoring module, it can be ensured that the BRAM self-refresh is performed when the internal algorithm module is in an idle state, and therefore, a BRAM port does not need to be occupied by a self-refresh operation alone, and a BRAM access conflict is not caused. Through the above architecture design, the satellite load FPGA can autonomously finish BRAM self-refresh reinforcement, BRAM conflict and resource waste are not caused, and the realization can be realized only by adding a small amount of CLB logic resources.

The algorithm monitoring module generally needs to be designed specifically according to different functions of the load FPGA configuration items, and for the self-refresh control module, the algorithm monitoring module can be designed into a Common Building Blocks (CBB) which is suitable for different load FPGA configuration items, so that the development efficiency can be improved.

As shown in FIG. 4, the self-refresh control module implements state switching via a finite state machine having four states S0, S1, S2, S3, each of which is:

s0: when the BRAM memory module is reset or is busy in access, the BRAM memory module is always in an S0 state, and when the BRAM memory module is idle, the BRAM memory module enters an S1 state;

s1: when the BRAM memory module is in a data reading state, the BRAM memory module is in an S1 state, and when the data reading of the BRAM memory module is finished, the BRAM memory module enters an S2 state;

s2: when the BRAM memory module is in a data writing state, the BRAM memory module is in an S2 state, data subjected to three-mode voting is written back, accumulated errors in the BRAM are eliminated, and the BRAM memory module enters an S3 state after writing is completed.

S3: when the BRAM memory module is in the single refresh completion state, the BRAM memory module is in the S3 state, entering the state indicates that the BRAM single address data refresh is completed, controlling the refresh address accumulation, returning to the S0 state, and continuing the next address refresh.

As shown in fig. 5, the self-refresh method performed by the self-refresh control module includes:

step S301: self-refresh and its control system reset;

step S302, monitoring the monitoring result of the algorithm monitoring module, if the BRAM storage module is in the busy state of internal algorithm access, then the step S302 is executed after a preset time interval; if the BRAM storage module is in an internal algorithm access idle state, entering a step S303;

step S303: reading the data in the BRAM storage module, wherein the self-refresh control module sequentially generates data reading addresses from 0 address and reads the BRAM data in the corresponding addresses;

step S304: voting the read data of the three BRAMs through the three-module voting module, and correcting the single event upset accumulated error;

step S305: the self-refresh control module writes the voted data back to the corresponding BRAM module, and eliminates the single event accumulated error stored by the BRAM;

step S306: the self-refresh control module accumulates the refresh address, if the address reaches the maximum value of the BRAM address space, the address is cleared, and the step S302 is entered; otherwise, completing the self-refreshing of the BRAM single address data and ending the method.

An embodiment of the present invention is given below and verified from both the heavy ion irradiation test and the satellite load in-orbit measurement.

The heavy ion irradiation test is a reliability evaluation test carried out before the satellite loading network satellite is launched, a test satellite configuration item and a network satellite configuration item are contrastively tested, and the test process is carried out for 5 times by single-particle function interruption or the total ion injection amount reaches 10⁷Particles per square centimeter (first arrival) is the irradiation stop criterion. The reliability evaluation index of the irradiation test is a single-particle functional interruption section, mainly represents the probability of a single-particle radiation event which causes single-particle functional interruption on a unit area of the device, is a recognized index for representing the sensitivity degree of the device to be tested to a single-particle effect, and is defined as follows:

（1）

wherein N is the number of single particle functional interruptions, and F is the total number of incident particles on the unit cross section of the device.

The results of the irradiation test are shown in table 1.

TABLE 1

It can be seen that the cross section of the single particle functional interruption of the positive sample star is from 5.5X 10 compared with the experimental star^-4cm²Down to 9.92 x 10^-5cm²The reliability is greatly improved by reducing the reliability by about 84 percent. Although the irradiation test cannot directly evaluate the performance of the BRAM improvement section, the positive star-stage reliability design improvement is mainly focused on BRAM reinforcement design compared to the experimental star-stage design, and thus the above results largely demonstrate the effectiveness of the method described herein.

And finally, verifying the effectiveness of the reinforcing method through the on-orbit operation condition of the load. The satellite loading test satellite phase counts 3 satellites, because the BRAM reinforcement design of the test satellite phase is insufficient, multiple single event upset abnormalities occur on the orbit, during the period from 8 months to 9 months in 2017 in 2015, the 3 satellites count 7 times of in-orbit abnormalities, and the analysis results of the 7 times of in-orbit single event upset abnormalities are summarized as shown in Table 2 after the abnormity zeroing analysis.

TABLE 2

It can be seen that, in all 7 on-track single-event anomalies, the BRAM parameter single-event accumulation anomaly accounts for 42.8%, which is the main cause of the on-track anomaly of the type of engineering. In the stage of the normal sample star, the BRAM anti-irradiation reinforcing method based on time-sharing refreshing and position constraint is adopted, irradiation tests show that the anti-irradiation reliability of the BRAM anti-irradiation reinforcing method is about 5 times that of the design of a test star, and at present, 30 normal sample stars do not have one-time single event upset abnormality in-orbit operation, so that the effectiveness of the satellite load FPGA with the BRAM is fully proved.

The embodiment of the invention further provides a use method of the satellite load FPGA with the BRAM, which comprises the following steps:

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a physical machine Server, or a network cloud Server, etc., and needs to install a Windows or Windows Server operating system) to perform some steps of the method according to various embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent change and modification made to the above embodiment according to the technical spirit of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. The utility model provides a satellite load FPGA with BRAM, characterized in that, satellite load FPGA includes inside algorithm module, three modulus voting module, BRAM and self-refresh module, wherein:

2. The satellite payload FPGA with BRAM of claim 1, wherein said internal algorithm module, performing read and write operations on data stored in BRAM, comprises: when the BRAM writing operation is carried out, a BRAM writing address and a data control signal are generated; when the BRAM reading operation is carried out, a BRAM reading address control signal is generated, and BRAM data subjected to three-mode voting is obtained and used for operation.

3. The satellite payload FPGA with BRAM of claim 2, wherein the tri-mode voting module takes the output data of the tri-mode BRAM as an input to the tri-mode voting module, with the majority of the same output as the correct output of the tri-mode voting module.

4. The satellite-borne FPGA with BRAM of claim 3, wherein when the rising edge of the clock comes and the enable terminal of the BRAM memory module is at a high level, the BRAM memory module reads or writes data stored in the BRAM memory module under the action of the read-write control signal.

5. The satellite payload FPGA with BRAM of claim 4, wherein the self-refresh control module implements state switching through a finite state machine having four states S0, S1, S2, S3, each state being:

s2: when the BRAM storage module is in a data writing state, the BRAM storage module is in an S2 state, data subjected to three-module voting is written back, accumulated errors in the BRAM are eliminated, and the BRAM storage module enters an S3 state after writing is completed;

6. The satellite payload FPGA with BRAM of claim 5, wherein the self-refresh control module performs self-refresh by:

step S301: self-refresh and its control system reset;

7. Use of a satellite payload FPGA with BRAM according to any of claims 1-6, comprising the steps of: