CN114492273B - Satellite load BRAM anti-radiation design method based on position constraint - Google Patents
Satellite load BRAM anti-radiation design method based on position constraint Download PDFInfo
- Publication number
- CN114492273B CN114492273B CN202210052202.5A CN202210052202A CN114492273B CN 114492273 B CN114492273 B CN 114492273B CN 202210052202 A CN202210052202 A CN 202210052202A CN 114492273 B CN114492273 B CN 114492273B
- Authority
- CN
- China
- Prior art keywords
- bram
- layout
- key
- wiring
- constraint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/04—Constraint-based CAD
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Details Of Aerials (AREA)
Abstract
The invention provides a satellite load BRAM anti-radiation design method based on position constraint. The method fundamentally reduces the probability that the plurality of functional modules in the triple modular redundancy design of the key functional module of the BRAM make mistakes simultaneously due to single event upset, improves the reliability of the satellite load in the space irradiation environment, and provides reference and reference for more comprehensively perfecting the anti-irradiation reinforcement design of the satellite-borne FPGA.
Description
Technical Field
The invention belongs to the technical field of FPGA (field programmable gate array) reliability, and relates to a satellite load BRAM (brake beam management) anti-radiation design method based on position constraint.
Background
The SRAM type FPGA has the advantages of high running speed and flexible design, and has great advantages compared with the traditional aerospace level device, but the SRAM type FPGA is very easy to generate single event effect under the space irradiation environment, the space single event effect is a bottleneck for preventing the SRAM type FPGA from being widely applied to space tasks, and the protection and reinforcement design of the SRAM type FPGA is very necessary. Particularly, the BRAM memory is difficult to eliminate the accumulation of space Single Event Upset (SEU) through the traditional refreshing operation because the stored data of the BRAM memory is always in dynamic application, and is one of the main reasons for the space single event of the SRAM type FPGA at present.
The flipping of a single configuration bit of the FPGA may cause multiple functional modules in the redundant design of the critical functional module to be simultaneously erroneous, thereby causing all the critical logic to fail. The traditional reinforcement design method for resisting the single event effect, such as the reinforcement design methods of Triple Modular Redundancy (TMR), error detection and correction coding (EDAC) technology, read-back refreshing and the like, cannot fundamentally solve the problem, and a strategy for improving the single event upset resistance of the traditional design still needs to be further researched to improve the fault tolerance of FPGA wiring resources to the single event effect fault, so that the reliable operation of key function modules in the electronic device under the space irradiation environment is ensured.
Disclosure of Invention
In order to solve the technical problem, the invention provides a satellite load BRAM anti-radiation design method based on position constraint, which comprises the following steps:
step 2, aiming at the resource condition after EDA software layout and wiring, executing layout position results, static timing sequence results and layout and wiring result analysis of a key BRAM, and determining the layout position of the BRAM after triple modular redundancy;
step 3, according to the analysis conclusion of the step 2, confirming whether the positions of the key BRAM and the key peripheral SLICE after the triple modular redundancy meet the preset requirement, if not, modifying the constraint condition of the layout and the wiring of the EDA software, and executing the step 4; if the preset requirement is met, executing the step 5;
step 4, repeating the steps 1-3, and executing the steps of synthesis, layout, wiring and analysis of the satellite-borne FPGA design again;
step 5, analyzing the layout and layout result after increasing the position constraint and the result of static timing sequence,
if the analysis result meets the preset requirement, jumping to step 7, and if the preset requirement is not met, executing step 6;
and 7, finishing the layout iteration and outputting a layout and wiring result.
Further, before automatically executing the design of the satellite-borne FPGA by using the EDA software in step 1, constraint conditions are set for the layout and routing functions of the EDA software, where the constraint conditions include: the geometric wiring interval between the functional modules, the key functional modules must be distributed in different wiring areas.
Further, step 3 comprises the sub-steps of:
checking the positions of the key BRAM and the key peripheral SLICE after the triple modular redundancy, and confirming whether the key BRAM of the triple modular redundancy is positioned in different rows or different columns; determining whether the critical peripheral SLICE of the triple modular redundancy is located in a different row or a different column;
step 3.2, if the position of the key BRAM or the key peripheral SLICE does not meet the condition: the position of the key BRAM is positioned in different rows or different columns; and, the location of the critical peripheral SLICE is in a different row or a different column; the location constraint limits for critical BRAMs and critical peripheral SLICE are added to the EDA software place-and-route function constraint file.
Further, the position constraint limits include: the geometric distance between the three modes of the same BRAM or SLICE is increased.
Further, step 5 comprises the sub-steps of:
step 5.1, if the BRAM and the key SLICE are positioned in different rows and different columns after the analysis result meets the triple modular redundancy, and the static timing analysis result meets the timing requirement, executing step 7;
and 5.2, if the EDA software cannot complete layout and wiring or the static timing analysis result does not meet the timing requirement, executing the step 6.
Further, step 6 comprises the sub-steps of, performed separately or simultaneously:
step 6.1, reducing the number of critical BRAM or SLICE constraints,
and 6.2, or reducing the layout geometric distance between the three modes.
Further, step 4 and step 6 are repeated and iterated for multiple times until the requirements in step 5.1 are met: after the analysis result meets the triple modular redundancy, the BRAM and the key SLICE are positioned in different rows or different columns, and the static timing sequence analysis result meets the timing sequence requirement.
By adopting the method, firstly, the BRAM position constraint script is added during layout and wiring, the EDA software is controlled to lay the BRAM at the appointed position, the wiring area of each redundant module after the BRAM triple-modular redundancy is geometrically divided, the condition that any two BRAMs share one interconnection matrix and the programmable interconnection line are adjacent is avoided, the probability that the multimode design has abnormal functions simultaneously due to single event upset is fundamentally reduced, the reliability of the satellite load working in the space irradiation environment is improved, and the method has good feasibility and popularization value.
Drawings
Fig. 1 is a schematic diagram of a BRAM wiring resource provided by the present invention undergoing a single event upset;
fig. 2 is a schematic diagram of a BRAM layout improvement provided by the present invention;
fig. 3 is a schematic diagram of a routing strategy based on region constraint according to the present invention.
Fig. 4 is a diagram of implementation steps of a BRAM radiation-resistant design method for satellite loads based on position constraints, provided by the invention.
Detailed Description
The invention aims to provide a satellite load BRAM anti-irradiation design method based on position constraint, which fixes the positions of 3 BRAMs after the BRAM triple modular redundancy through the position constraint, greatly reduces the probability of simultaneous errors of a plurality of modules of the BRAM for data storage and parameter storage caused by single event upset of a configuration memory due to FPGA (field programmable gate array) layout and wiring, can effectively improve the anti-irradiation reliability of the BRAM, further more comprehensively improves the satellite load FPGA anti-irradiation reinforcement design, and is a feasible, economic and efficient method.
According to the method, the layout and wiring areas of the redundancy modules after the BRAM triple-modular redundancy are geometrically divided, the situation that any two BRAMs share one interconnection matrix and the programmable interconnection lines are adjacent is avoided, and the probability of the simultaneous occurrence of the abnormal functions of the multi-mode design caused by single-event upset is fundamentally reduced.
The SRAM type FPGA adopts a specially designed switch matrix to improve the area utilization rate and the signal transmission quality. The BRAM resource also has corresponding switch matrix and BRAM interconnection configuration resource, if the resource is subjected to single event upset, as shown in figure 1, the left figure is a wiring implementation of the switch matrix in the functional module, wherein the switch matrix A and the switch matrix B belong to two functional modules, and if SEU occurs in the wiring resource configuration bit, the configuration state of the switch matrix is failed (as the connection shown by the dotted line in the right figure), the switch matrix A and the switch matrix B can be failed. If A and B are two independent repeated modules in the TMR structure, most judgers in the TMR structure output wrong results, so that the corresponding module functions are in failure, and the stable operation of the system is influenced. The root cause of the problems is that the position distribution of two BRAMs exceeds a safe geometric wiring interval, so that the single event upset can affect the simultaneous abnormality of the functions of two adjacent BRAMs.
In the implementation process of the satellite-borne FPGA configuration item, a user generally cannot control the layout and wiring process, the circuit layout after the BRAM is in the three-mode is automatically configured by EDA software, the situation that more than 2 BRAM layouts are in the same row or the same column after the three modules is caused, and the probability that the design after the three modules is abnormal in function due to single event upset is greatly improved.
In order to solve the technical problem, firstly, the invention adds a BRAM position constraint script and controls EDA software to lay out the BRAM at a specified position. The BRAM position constraint schematic diagram corresponding to the invention is shown in fig. 2, for the convenience of analysis, the structure of the BRAM module is simplified, the left diagram shows an original layout strategy, it can be seen that the geometric wiring intervals among three important modules are not enough, a phenomenon of sharing a switch matrix exists, and programmable interconnection lines of the three important modules can be adjacent, if an SEU occurs in a wiring resource configuration bit, a plurality of modules can be failed probably. After the BRAM position constraint script is added, three important function modules can be distributed at three corners respectively, the key function modules are distributed in different wiring areas by increasing the geometric wiring interval between the modules, and the probability of the multimode design having abnormal functions caused by single event upset can be greatly reduced.
In addition, besides the BRAM position constraint, aiming at the peripheral key function modules of the BRAM, such as read-write control and the like, the method for increasing the area constraint is adopted, any two key function modules related to the BRAM are prevented from being distributed in the same wiring area, and the probability of functional abnormality of the BRAM multimode design caused by SEU is fundamentally reduced. The corresponding routing strategy based on the area constraint of the invention is shown in fig. 3, wherein a, B and C are schematic diagrams of programmable routing resource layout areas of three redundant modules, and different key function modules are distributed in mutually independent areas by geometrically dividing the routing areas of each element. However, the area constraint method also reduces the utilization rate of the area of the FPGA for wiring, and increases the difficulty of wiring, so the method also has a risk of failure of wiring, and may need to iterate multiple rounds to realize the layout and wiring in a scenario with a high resource occupancy rate. The BRAM position constraint and key function module region constraint design method can also be applied to other types of user resources of satellite-borne FPGA, so that the reliability of on-orbit single event upset resistance is further improved.
According to the design, the implementation steps of the method for designing the radiation resistance of the BRAM based on the satellite load based on the position constraint are further described, and the flow chart is shown in fig. 4:
the method comprises the following steps: automatically executing the synthesis and layout wiring of the satellite-borne FPGA design through EDA software;
step two: analyzing the resource condition after automatic layout and wiring, the static timing sequence result and the layout and wiring result of the key BRAM, and confirming the layout position of the BRAM after triple modular redundancy;
step three: according to the analysis result of the second step, adding position constraints of the key BRAM and the peripheral SLICE in the constraint file, enabling the BRAM and the key SLICE to be positioned in different rows and different columns after triple modular redundancy, and increasing the geometric distance between the same BRAM or the same SLICE;
step four: performing the integration and layout wiring of the satellite-borne FPGA design again through EDA software;
step five: analyzing the layout and wiring result and the static timing sequence analysis result after the position constraint is added, if the BRAM and the key SLICE are positioned in different rows and different columns after the triple modular redundancy and the static timing sequence analysis result meets the timing sequence requirement, executing a seventh step, and if the EDA software cannot complete the layout and wiring or the static timing sequence analysis result does not meet the timing sequence requirement, executing a sixth step;
step six: adjusting the position constraints of the BRAM and the peripheral key SLCIE in the constraint file, wherein the overall adjustment idea is to reduce the number of the constraint of the key BRAM or SLICE, or reduce the layout geometric distance between the three modules, reduce the layout and wiring difficulty, and execute the step four again;
step seven: and (5) finishing the iteration and outputting a layout and wiring result. Compared with the prior art, the invention has the innovation points that:
(1) the probability that a plurality of functional modules in the triple modular redundancy design of the key functional module make mistakes simultaneously due to single event upset of the BRAM is fundamentally reduced, a common BRAM reinforcement design method is perfected, and the fault tolerance of the BRAM of the satellite load is improved to a certain extent;
(2) under the condition of relatively rich resources, the reliability of the anti-irradiation reinforcement design of the key functional module is greatly improved;
(3) the regional constraint method does not additionally increase FPGA resources and has little influence on the operation speed of the functional module;
the following detailed description of the embodiments of the invention refers to the accompanying drawings.
Fig. 1 is a schematic diagram showing a BRAM wiring resource single event upset provided by the present invention, and the left diagram is a wiring implementation of a switch matrix in a functional module, where the switch matrices a and B belong to two functional modules, and if an SEU occurs in a wiring resource configuration bit, which causes a failure in the configuration state of the switch matrix (as shown by the connection indicated by the dashed line in the right diagram), both the switch matrices a and B may fail. If A and B are two independent repeated modules in the TMR structure, most judgers in the TMR structure output wrong results, so that the corresponding module functions are in failure, and the stable operation of the system is influenced. The root cause of the problems is that the position distribution of two BRAMs exceeds a safe geometric wiring interval, so that the single event upset can affect the simultaneous abnormality of the functions of two adjacent BRAMs.
In the implementation process of the satellite-borne FPGA configuration item, a user generally cannot control the layout and wiring process, the circuit layout after the BRAM is in the three-mode is automatically configured by EDA software, the situation that more than 2 BRAM layouts are in the same row or the same column after the three modules is caused, and the probability that the design after the three modules is abnormal in function due to single event upset is greatly improved.
In order to solve the technical problem, firstly, the BRAM position constraint script is added, and the EDA software is controlled to lay the BRAM at the specified position. The schematic diagram of the BRAM layout corresponding to the invention is shown in fig. 2, for the convenience of analysis, the structure of the BRAM module is simplified, the left diagram shows an original layout strategy, it can be seen that the geometric wiring intervals between three important modules are not enough, a phenomenon of sharing a switch matrix exists, and the programmable interconnection lines of the three important modules can also be adjacent, if an SEU occurs at a wiring resource configuration bit, a plurality of modules can be failed probably. After the BRAM position constraint script is added, three important function modules can be distributed in three corners respectively, and the key function modules are distributed in different wiring areas by increasing the geometric wiring interval between the modules, so that the probability of functional abnormality of the multimode design caused by single event upset can be greatly reduced.
In addition, the invention also adopts a method for increasing the regional constraint, avoids any two key functional modules from being distributed in the same wiring region, and fundamentally reduces the probability of the abnormal function of the multimode design caused by SEU. The corresponding routing strategy based on the area constraint of the invention is shown in fig. 3, wherein a, B and C are schematic diagrams of programmable routing resource layout areas of three redundant modules, and different key function modules are distributed in mutually independent areas by geometrically dividing the routing areas of each element. However, the area constraint method also reduces the utilization rate of the wiring area of the FPGA and increases the wiring difficulty, so the method also has a risk of failure in wiring, and is mainly suitable for a scene with low resource occupancy.
According to the design, the implementation steps of the method for designing the radiation resistance of the BRAM based on the satellite load based on the position constraint are further described, and the flow chart is shown as the following figure 4:
the method comprises the following steps: automatically executing the synthesis and layout wiring of the satellite-borne FPGA design through EDA software;
step two: analyzing the resource condition after automatic layout and wiring, the static timing sequence result and the layout and wiring result of the key BRAM, and confirming the layout position of the BRAM after triple modular redundancy;
step three: according to the analysis result of the second step, adding position constraints of the key BRAM and the peripheral SLICE in the constraint file, enabling the BRAM and the key SLICE to be positioned in different rows and different columns after triple modular redundancy, and adding the geometric distance between the same BRAM or the same SLICE;
step four: performing the integration and layout wiring of the satellite-borne FPGA design again through EDA software;
step five: analyzing the layout and wiring result and the static timing sequence analysis result after the position constraint is added, if the BRAM and the key SLICE are positioned in different rows and different columns after the triple modular redundancy and the static timing sequence analysis result meets the timing sequence requirement, executing a seventh step, and if the EDA software cannot complete the layout and wiring or the static timing sequence analysis result does not meet the timing sequence requirement, executing a sixth step;
step six: adjusting the position constraints of the BRAM and the peripheral key SLCIE in the constraint file, wherein the overall adjustment thought is to reduce the number of the key BRAM or SLCIE constraints or reduce the layout geometric distance between the three modules, reduce the difficulty of layout and wiring, and execute the step four again;
step seven: and (5) finishing the iteration and outputting a layout and wiring result.
Example (b):
in order to verify the effectiveness of the reinforcement method, the ground fault injection test, the heavy ion irradiation test and the satellite load on-orbit actual measurement condition are verified.
At present, a ground fault injection test is mainly to carry out fault injection for SRAM type FPGA configuration data, and fault injection cannot be carried out on a user logic part, such as BRAM storage data, so that the ground fault injection test is difficult to verify the performance of a BRAM self-refresh design, but the fault injection test can realize fault injection on a BRAM interconnection part, and further evaluate the performance of the BRAM position constraint design. The invention utilizes the FPGA configuration data fault injection evaluation index based on the configuration data abnormal Rate (RFCB), which is easier to obtain through a fault injection test and can visually reflect the performance of load FPGA design anti-irradiation design, and the specific definition is as follows:
wherein, b e For the number of bits that cause a malfunction of a configuration item, it is tested by a fault injection test, b T The total number of bits for the configuration data. For the BRAM interconnect concerned by the invention, b T And especially to the total bit number of the BRAM interconnection part.
The abnormal bit rate of the BRAM interconnection part is tested under the condition of different BRAM position constraints by modifying the position of the BRAM used by the three-mode design in the tested unit, and the specific test result is shown in Table 1. The test result shows that when 3 BRAMs with the same function are positioned in the same row or the same column after three modules, the RFCB with abnormal functions caused by single event upset is the highest; when 2 modules are in the same row or column, the FRCB has a certain decline; when the three-mode BRAM is at different rows and different columns, the RFCB is obviously reduced, and is reduced by about 42.6 percent compared with the three-mode same-column case. The above result is only reliability improvement after a single BRAM position constraint, and if more BRAMs are subjected to position constraints, the reliability improvement will be more obvious. Of course, the position constraint reduces the degree of freedom of layout and wiring optimization of EDA software to a certain extent, and may even cause layout and wiring failure, so in an actual application process, the position constraint design needs to be selectively performed on the key BRAM according to the actual design.
The heavy ion irradiation test is a reliability evaluation test carried out before the satellite loading network satellite is launched, a test satellite configuration item and a network satellite configuration item are contrastively tested, and the test process is carried out for 5 times by single-particle function interruption or the total ion injection amount reaches 10 7 Particles per square centimeter (first arrival) is the irradiation stop criterion. The reliability evaluation index of the irradiation test is a single-particle functional interruption section, mainly represents the probability of a single-particle radiation event which causes single-particle functional interruption on a unit area of the device, is a recognized index for representing the sensitivity degree of the device to be tested to a single-particle effect, and is defined as follows:
wherein N is the number of single particle functional interruptions, and F is the total number of incident particles on the unit cross section of the device.
The irradiation test results are shown in Table 2, and it can be seen that the cross section of the single particle functional interruption of the positive sample star is from 5.5 × 10 compared with the experimental star -4 cm 2 Down to 9.92 x 10 -5 cm 2 The reliability is greatly improved by about 84 percent. Although the irradiation test cannot directly evaluate the performance of the BRAM improvement section, the positive star-stage reliability design improvement is mainly focused on BRAM reinforcement design compared to the experimental star-stage design, and thus the above results largely demonstrate the effectiveness of the method described herein.
And finally, verifying the effectiveness of the reinforcing method through the on-orbit operation condition of the load. The satellite loading test satellite phase counts 3 satellites, because the BRAM reinforcement design of the test satellite phase is insufficient, the single event upset abnormality occurs for many times in the orbit, and during the period from 8 months in 2015 to 9 months in 2017, the orbit abnormality occurs for 7 times in total for 3 satellites. The BRAM parameter single particle accumulation abnormity accounts for 42.8%, and is a main reason for the on-orbit abnormity of the engineering. In the stage of the normal sample star, the BRAM anti-radiation reinforcement method based on the position constraint and the like are adopted, the radiation test shows that the anti-radiation reliability is about 5 times of that of the design of a test star, and at present, 30 normal sample stars operate on the orbit without one-time single event upset abnormality, so that the effectiveness of the reinforcement method is fully proved.
Table 1 shows BRAM position constraint fault injection test results provided by the invention
Table 2 shows the results of the irradiation test provided by the present invention
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting, and although the embodiments of the present invention are described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the embodiments of the present invention without departing from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A satellite load BRAM radiation resistance design method based on position constraint is characterized by comprising the following steps:
step 1, executing comprehensive layout of satellite-borne FPGA design and wiring the comprehensive layout by using EDA software;
step 2, aiming at the resource condition after EDA software layout and wiring, executing layout position results, static timing sequence results and layout and wiring result analysis of a key BRAM, and determining the layout position of the BRAM after triple modular redundancy;
step 3, according to the analysis conclusion of the step 2, confirming whether the positions of the key BRAM and the key peripheral SLICE after the triple modular redundancy meet the preset requirement, if not, modifying the constraint condition of the layout and the wiring of the EDA software, and executing the step 4; if the preset requirement is met, executing the step 5;
step 4, repeating the steps 1-3, and executing the steps of synthesizing, laying out, wiring and analyzing the satellite-borne FPGA design again;
step 5, analyzing the layout and layout result after increasing the position constraint and the result of static timing sequence,
if the analysis result meets the preset requirement, jumping to step 7, and if the preset requirement is not met, executing step 6;
step 6, adjusting the position constraints of BRAM and key periphery SLCIE in the constraint conditions, changing the layout constraint conditions, and returning to execute the step 4;
step 7, finishing the layout iteration and outputting a layout and wiring result;
the step 3 comprises the sub-steps of:
step 3.1, checking the positions of the key BRAM and the key peripheral SLICE after the triple modular redundancy, and confirming whether the key BRAM of the triple modular redundancy is positioned in different rows or different columns; determining whether the critical peripheral SLICE of the triple modular redundancy is located in a different row or a different column;
step 3.2, if the position of the key BRAM or key peripheral SLICE does not satisfy the condition: the position of the key BRAM is positioned in different rows or different columns; and, the location of the critical peripheral SLICE is in a different row or a different column; the location constraint limits for critical BRAMs and critical peripheral SLICE are added to the EDA software place-and-route function constraint file.
2. The method of claim 1, wherein before automatically performing the on-board FPGA design using EDA software in step 1, constraints are set on EDA software place and route functions, the constraints comprising: the geometric wiring interval between the functional modules, the key functional modules must be distributed in different wiring areas.
3. The method of claim 1, wherein the location constraint limit comprises: the geometric distance between the three modes of the same BRAM or SLICE is increased.
4. The method of claim 1, wherein step 5 comprises the sub-steps of:
step 5.1, if the BRAM and the key SLICE are positioned in different rows and different columns after the analysis result meets the triple modular redundancy, and the static timing analysis result meets the timing requirement, executing step 7;
and 5.2, if the EDA software cannot complete layout and wiring or the static timing analysis result does not meet the timing requirement, executing the step 6.
5. The method of claim 4, wherein step 6 comprises the sub-steps of, performed separately or simultaneously:
step 6.1, reducing the number of key BRAM or SLICE constraints,
and 6.2, or reducing the layout geometric distance between the three modes.
6. The method of claim 5, wherein steps 4 and 6 are iteratively run for a plurality of times until the requirements in step 5.1 are met: the BRAM and the key SLICE are positioned in different rows or different columns after the analysis result meets the triple modular redundancy, and the static timing sequence analysis result meets the timing sequence requirement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210052202.5A CN114492273B (en) | 2022-01-18 | 2022-01-18 | Satellite load BRAM anti-radiation design method based on position constraint |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210052202.5A CN114492273B (en) | 2022-01-18 | 2022-01-18 | Satellite load BRAM anti-radiation design method based on position constraint |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114492273A CN114492273A (en) | 2022-05-13 |
| CN114492273B true CN114492273B (en) | 2022-09-13 |
Family
ID=81511212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210052202.5A Active CN114492273B (en) | 2022-01-18 | 2022-01-18 | Satellite load BRAM anti-radiation design method based on position constraint |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114492273B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0415107A2 (en) * | 1989-07-31 | 1991-03-06 | Yazaki Corporation | Method of treating gold plating film |
| CN104133655A (en) * | 2014-07-11 | 2014-11-05 | 中国人民解放军信息工程大学 | Design method of anti-radiation multiplier based on satellite-borne MIMO detection |
| CN104281742A (en) * | 2014-09-11 | 2015-01-14 | 上海卫星工程研究所 | SRAM (static random access memory) type large-scale FPGA (field programmable gate array) anti-single-particle device and method |
| CN104331546A (en) * | 2014-10-22 | 2015-02-04 | 中国空间技术研究院 | Digital customized integrated circuit back end layout design evaluation method for space vehicle |
| CN105468798A (en) * | 2014-09-02 | 2016-04-06 | 复旦大学 | Anti-radiation placing and routing method for integrated circuits |
| CN112597728A (en) * | 2020-12-28 | 2021-04-02 | 中国科学院空天信息创新研究院 | Triple modular redundancy method based on molecular-level netlist |
| CN113254252A (en) * | 2021-07-01 | 2021-08-13 | 中国人民解放军国防科技大学 | Satellite load FPGA with BRAM and use method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110083492B (en) * | 2019-04-28 | 2023-03-07 | 北京控制工程研究所 | Circuit key register triple modular redundancy reinforcing method and device |
| CN111338833B (en) * | 2020-02-19 | 2022-02-01 | 北京航空航天大学 | BRAM detection-based dynamic self-adaptive SRAM type FPGA system fault tolerance method |
-
2022
- 2022-01-18 CN CN202210052202.5A patent/CN114492273B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0415107A2 (en) * | 1989-07-31 | 1991-03-06 | Yazaki Corporation | Method of treating gold plating film |
| CN104133655A (en) * | 2014-07-11 | 2014-11-05 | 中国人民解放军信息工程大学 | Design method of anti-radiation multiplier based on satellite-borne MIMO detection |
| CN105468798A (en) * | 2014-09-02 | 2016-04-06 | 复旦大学 | Anti-radiation placing and routing method for integrated circuits |
| CN104281742A (en) * | 2014-09-11 | 2015-01-14 | 上海卫星工程研究所 | SRAM (static random access memory) type large-scale FPGA (field programmable gate array) anti-single-particle device and method |
| CN104331546A (en) * | 2014-10-22 | 2015-02-04 | 中国空间技术研究院 | Digital customized integrated circuit back end layout design evaluation method for space vehicle |
| CN112597728A (en) * | 2020-12-28 | 2021-04-02 | 中国科学院空天信息创新研究院 | Triple modular redundancy method based on molecular-level netlist |
| CN113254252A (en) * | 2021-07-01 | 2021-08-13 | 中国人民解放军国防科技大学 | Satellite load FPGA with BRAM and use method thereof |
Non-Patent Citations (2)
| Title |
|---|
| "FPGA块存储器的多位翻转容错设计";钟敏 等;《计算机测量与控制》;20210302;第29卷(第5期);169-178 * |
| "航天用SRAM型FPGA抗单粒子翻转设计";马寅;《航天器环境工程》;20111215;第28卷(第6期);551-556 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114492273A (en) | 2022-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8117512B2 (en) | Failure detection and mitigation in logic circuits | |
| Dugan et al. | Dynamic fault-tree models for fault-tolerant computer systems | |
| EP2533154B1 (en) | Failure detection and mitigation in logic circuits | |
| Ginosar | Survey of processors for space | |
| US20180046580A1 (en) | Multi-mode radiation hardened multi-core microprocessors | |
| Nazar et al. | Accelerated FPGA repair through shifted scrubbing | |
| CN114492273B (en) | Satellite load BRAM anti-radiation design method based on position constraint | |
| Veljković et al. | Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures | |
| Quinn et al. | A review of Xilinx FPGA architectural reliability concerns from Virtex to Virtex-5 | |
| Niknahad et al. | A study on fine granular fault tolerance methodologies for FPGAs | |
| CN113254252B (en) | Satellite load FPGA with BRAM and use method thereof | |
| US7565586B2 (en) | Method and apparatus for latent fault memory scrub in memory intensive computer hardware | |
| JPH0652697A (en) | Semiconductor memory having error correcting function | |
| Bentoutou | Program memories error detection and correction on-board earth observation satellites | |
| CN107168817B (en) | Data restoration method and device applied to storage array and storage equipment | |
| Gonazlez et al. | Supporting fault tolerance in an industrial environment: the AMATISTA approach | |
| CN113380294A (en) | Single event upset resistant circuit and method for FLASH chip configured by FPGA | |
| Cai et al. | Implementation of a reconfigurable computing system for space applications | |
| Mukherjee et al. | Fault tolerant architecture design using quad‐gate‐transistor redundancy | |
| CN107895090B (en) | Mathematical description method of embryo electronic system | |
| KR101825568B1 (en) | Failure Detection and Mitigation in Logic Circuits | |
| Singh et al. | Ram error detection and correction using HVD implementation | |
| CN112988431B (en) | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) | |
| Cannon et al. | Improving sram fpga radiation reliability through low-level tmr implementation | |
| Gericota et al. | Robust configurable system design with built-in self-healing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |