CN111459712A - SRAM type FPGA single event upset error correction method and single event upset error correction circuit - Google Patents
SRAM type FPGA single event upset error correction method and single event upset error correction circuit Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/102—Error in check bits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The application discloses a single event upset error correction method for an SRAM type FPGA, a single event upset error correction circuit, electronic equipment and a computer storage medium, wherein the method comprises the following steps: s1: starting a single event upset error correction circuit; s2: acquiring a configuration frame address; s3: reading the configuration data frame from a configuration storage unit according to the configuration frame address; s4: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single error data bit is found, the configuration data frame is written back to the configuration storage unit after error correction; s5: judging whether the configuration frame address is the maximum frame address; if yes, go to S2; otherwise, executing S6; s6: a next configuration frame address is generated and S2 is performed. And reading back the data bits of the configuration data frame, and synchronously performing error correction and write-back, so that the error correction process is synchronously completed when the configuration data frame is written back, and the data does not need to be cached, so that additional resources are not needed for storing the read-back configuration storage unit data.
Description
Technical Field
The application relates to the technical field of integrated circuit design, in particular to a single event upset error correction method of an SRAM type FPGA, a single event upset error correction circuit, electronic equipment and a computer storage medium.
Background
A Single Event Upset (SEU) is a bit flip of a memory cell (i.e., the content changes from 0 to 1, or from 1 to 0) due to the space particle radiation. The SEU effect is transient, non-destructive, but it may alter the RAM (Random access memory) configuration of the microelectronic circuit, adversely affecting the functions performed by the programmable electronic hardware.
Modern civil aircraft flight control, avionics and other systems are highly complex, and a large number of RAM-based complex electronic devices, such as microprocessors, Field Programmable Gate Arrays (FPGAs) and the like, are used. In the development process of civil aircraft onboard equipment, chips which are widely used mainly include Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). ASIC chips can achieve high density, small volume and low power consumption, but ASIC production costs and risks are high and lack flexibility. ASICs are also sensitive to SEU, but have relatively good SEU immunity characteristics. With the rapid development of the electronic industry, FPGAs are widely used in digital system design and ASIC prototype front-end design due to their high performance and flexibility.
Compared with the antifuse-based FPGA and the FPGA based on F L ASH, the radiation resistance of the SRAM-type FPGA is insufficient, but the strong performance advantage and the design flexibility of the SRAM-type FPGA still have great attraction to flight control and avionics application.
Because the SRAM type FPGA is sensitive to the SEU effect, in order to reduce the security influence caused by the SEU to the minimum when a civil aircraft system and an apparatus are designed, several common SEU reduction measures of Triple Modular Redundancy (TMR), Error Correction Code (ECC), and Scrubbing (Scrubbing) may be adopted for the device sensitive to the SEU effect. The triple-modular redundancy technology has high error correction speed, but has the defect of more additional hardware resources, and is not suitable for large-scale SRAM type FPGA SEU slowing and reinforcing. Scrubbing does not essentially solve the problem of the SEU effect, but only provides some degree of relief.
Error correction codes are a common mitigation method for SEU, and may use specific encoding and decoding rules to check and correct faults in memory. The basic principle of error correction codes is to add redundant codes to an information-encoded sequence, which are then stored and transmitted, with some definite correlation between these redundant codes and the information encoding. The receiver can find whether the SEU is influenced by checking the association between the redundant code and the information code, and then realize fault isolation or correct the SEU by using a coding algorithm.
The purpose of ECC encoding of FPGAs is to enable errors to be discovered and corrected when the contents of a memory cell are read. Coding methods capable of detecting and correcting errors, such as Cyclic Redundancy Check (CRC), Hamming Code (Hamming Code), etc., are generally used.
The existing FPGA manufacturers realize embedded single-particle upset error correction circuits in partial devices of the FPGA manufacturers for reducing SEU effect, and the defects that read-back configuration storage unit data need to be stored by using Block RAM resources in an FPGA chip, and extra resources are occupied.
Disclosure of Invention
The application aims to provide an SRAM type FPGA single event upset error correction method, an SRAM type FPGA single event upset error correction circuit, electronic equipment and a computer storage medium, overcomes the defects of the prior art, diagnoses, positions and corrects bit errors caused by SEU effect in an SRAM type FPGA storage unit, and does not need extra resources to store read-back configuration storage unit data.
The purpose of the application is realized by adopting the following technical scheme:
in a first aspect, the present application provides a method for correcting single event upset of an SRAM-type FPGA, the method comprising:
s1: starting a single event upset error correction circuit;
s2: acquiring a configuration frame address;
s3: reading the configuration data frame from a configuration storage unit according to the configuration frame address;
s4: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single error data bit is found, the configuration data frame is written back to the configuration storage unit after error correction;
s5: judging whether the configuration frame address is the maximum frame address; if the frame address is the maximum frame address, performing S2; if not, go to S6;
s6: a next configuration frame address is generated and S2 is performed.
And reading back the data bits of the configuration data frame, and synchronously performing error correction and write-back, so that the error correction process is synchronously completed when the configuration data frame is written back, and the data does not need to be cached, so that additional resources are not needed for storing the read-back configuration storage unit data.
Optionally, the S4 includes: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S7 is performed;
the method further comprises the following steps:
s7: judging whether the configuration data frame needs to be checked again; if the re-verification is required, executing S8; if the re-verification is not required, performing S9;
s8: reading back the configuration data frame according to the configuration frame address, and carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S9 is performed;
s9: and writing the configuration data frame after error correction to the configuration storage unit.
In the prior art, when programmable resources in an FPGA device are in a working mode, a data read-back result of a storage unit is possibly abnormal, so that a diagnosis result of a bit error is unreliable.
Optionally, S8 to S9 are repeatedly performed, so that a plurality of checks on the configuration data frame are implemented.
The configurable option is provided, multiple error checks on the configuration data frame can be supported, and the reliability of error positioning can be improved by performing multiple data frame readback and checks under the condition of sacrificing efficiency, so that multiple checks on the bit errors of the data of the storage unit are performed, and the reliability of a diagnosis result is improved.
Optionally, the configuration data frame includes n-bit data bits and m-bit check bits, and the m-bit check bits perform error check and location on the n-bit data bits and the m-bit check bits in the configuration data frame; wherein n and m are positive integers.
One configuration data frame contains n-bit data bits and m-bit check bits, and the m check bits perform error location on the (n + m) -bit data bits, that is: the m-bit check bits not only check the data bits, but also check the check bits themselves.
Optionally, the performing error checking and locating on the configuration data frame includes: performing error check and positioning on the configuration data frame in a pipeline mode according to k data bits each time; wherein k is a positive integer and k is divisible by n;
the writing back the configuration data frame after error correction to the configuration storage unit includes: and writing the configuration data frame after error correction to the configuration storage unit in a pipeline mode according to k data bits each time.
Data are checked and written back in a pipeline mode, data processing is changed from synchronous to asynchronous, a large amount of data are prevented from being processed at the same time, hardware stability and data safety can be improved, and data are processed stably and orderly.
Optionally, the n-bit data bits and the m-bit check bits in the configuration data frame are binary data bits.
The binary data has a value of 0 or 1, the m-bit check bits in the configuration data frame are enhanced hamming code check bits of the n-bit data bits, and the (n + m) -bit binary bits in the configuration data frame are subjected to error check and positioning according to the m-bit check bits.
Optionally, the writing back the configuration data frame after error correction to the configuration storage unit includes: and writing back the error data bit positioned in the configuration data frame to the configuration storage unit after binary inversion.
Since the binary data has only 0 and 1, error correction can be accomplished by binary negation of the erroneous data bits.
In a second aspect, the present application provides a single event upset error correction circuit, where the single event upset error correction circuit includes a configuration storage unit, a read/write controller, a frame address generator, an error locator, an error correction circuit, and an error correction state controller, and the error correction state controller executes:
s1: starting the single event upset error correction circuit;
s2: acquiring a configuration frame address output by the frame address generator;
s3: reading the configuration data frame from the configuration storage unit according to the configuration frame address;
s4: performing error checking and positioning on the configuration data frame through the error positioner; if no error data bit is found, go to S5; if a single error data bit is found, error correction is carried out on the configuration data frame through the error correction circuit, and the configuration data frame after error correction is written back to the configuration storage unit through the read-write controller;
s5: judging whether the configuration frame address output by the frame address generator is the maximum frame address; if the frame address is the maximum frame address, performing S2; if not, go to S6;
s6: the frame address generator is driven to generate the next configuration frame address and S2 is performed.
Optionally, the S4 includes: performing error checking and positioning on the configuration data frame through the error positioner; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S7 is performed;
the error correction state controller further performs:
s7: judging whether the configuration data frame needs to be checked again; if the re-verification is required, executing S8; if the re-verification is not required, performing S9;
s8: reading the configuration data frame from the configuration storage unit according to the configuration frame address, and carrying out error check and positioning on the configuration data frame through the error positioner; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S9 is performed;
s9: and correcting the configuration data frame through the error correction circuit, and writing the configuration data frame after error correction back to the configuration storage unit through the read-write controller.
Optionally, the error correction state controller repeatedly performs S8 to S9, implementing a plurality of checks on the configuration data frame.
Optionally, the configuration data frame includes n-bit data bits and m-bit check bits, and the m-bit check bits perform error check and location on the n-bit data bits and the m-bit check bits in the configuration data frame; wherein n and m are positive integers.
Optionally, the error locator performs error checking and locating on the configuration data frame in a pipelined manner according to k data bits at a time; wherein k is a positive integer and k is divisible by n;
and the read-write controller writes the configuration data frame after error correction back to the configuration storage unit in a pipeline mode according to k data bits at each time.
Optionally, the n-bit data bits and the m-bit check bits in the configuration data frame are binary data bits.
Optionally, the error correction circuit performs binary inversion on the error data bits located in the configuration data frame.
In a third aspect, the present application provides an electronic device, including a processor and a memory, where the processor executes computer instructions stored in the memory, so that the electronic device executes any one of the above SRAM-type FPGA single event upset error correction methods.
In a fourth aspect, the present application provides a computer storage medium comprising computer instructions that, when run on an electronic device, cause the electronic device to perform any one of the above described SRAM-type FPGA single event upset error correction methods.
Compared with the prior art, the technical effects of the application include:
the application discloses a single event upset error correction method of an SRAM type FPGA (field programmable gate array), a single event upset error correction circuit, electronic equipment and a computer storage medium, wherein data bits of a configuration data frame are read back and are subjected to error correction and write back synchronously, so that the error correction process is finished synchronously when the configuration data frame is written back, and no cache data is needed, so that extra resources are not needed for storing the read-back configuration storage unit data.
Drawings
The present application is further described below with reference to the drawings and examples.
FIG. 1 is a flow chart of a single event upset error correction method for an SRAM type FPGA according to a first embodiment;
FIG. 2 is a schematic flow chart of a single event upset error correction method for an SRAM type FPGA according to a first embodiment;
FIG. 3 is a schematic diagram of a configuration data frame;
FIG. 4 is a part of a flowchart of a single event upset error correction method for an SRAM type FPGA according to a second embodiment;
fig. 5 is a block diagram of a single event upset error correction circuit according to a third embodiment.
Detailed Description
The present application is further described with reference to the accompanying drawings and the detailed description, and it should be noted that, in the present application, the embodiments or technical features described below may be arbitrarily combined to form a new embodiment without conflict.
Referring to fig. 1 and 2, a first embodiment provides a single event upset error correction method for an SRAM-type FPGA, which includes steps S1 to S6.
S1: and starting the single event upset error correction circuit.
S2: and acquiring a configuration frame address.
S3: and reading the configuration data frame from a configuration storage unit according to the configuration frame address.
The configuration storage unit may contain a plurality of configuration data frames. Specifically, referring to fig. 3, the configuration data frame 201 may include n-bit data bits 202 and m-bit check bits 203, and the m-bit check bits 203 perform error checking and positioning on the n-bit data bits 202 and the m-bit check bits 203 in the configuration data frame 201; wherein n and m are positive integers. A configuration data frame 201 contains n-bit data bits 202 and m-bit check bits 203, where the m check bits 203 perform error location on the (n + m) -bit data bits 202, i.e.: the m-bit check bits 203 check not only the data bits 202, but also the check bits 203 themselves.
Further preferably, the n-bit data bits and the m-bit check bits in the configuration data frame are binary data bits. The binary data has a value of 0 or 1, the m-bit check bits in the configuration data frame are enhanced hamming code check bits of the n-bit data bits, and the (n + m) -bit binary bits in the configuration data frame are subjected to error check and positioning according to the m-bit check bits.
S4: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; and if a single error data bit is found, correcting the error of the configuration data frame and writing the configuration data frame back to the configuration storage unit.
Wherein the performing error check and positioning on the configuration data frame may include: performing error check and positioning on the configuration data frame in a pipeline mode according to k data bits each time; wherein k is a positive integer and k is divisible by n; the writing back the configuration data frame after error correction to the configuration storage unit may include: and writing the configuration data frame after error correction to the configuration storage unit in a pipeline mode according to k data bits each time. Data are checked and written back in a pipeline mode, data processing is changed from synchronous to asynchronous, a large amount of data are prevented from being processed at the same time, hardware stability and data safety can be improved, and data are processed stably and orderly.
When the n-bit data bits and the m-bit check bits in the configuration data frame are binary data bits, the performing error check and location on the configuration data frame may include: and writing back the error data bit positioned in the configuration data frame to the configuration storage unit after binary inversion. Since the binary data has only 0 and 1, error correction can be accomplished by binary negation of the erroneous data bits.
S5: judging whether the configuration frame address is the maximum frame address; if the frame address is the maximum frame address, performing S2; if not, S6 is executed.
S6: a next configuration frame address is generated and S2 is performed.
And reading back the data bits of the configuration data frame, and synchronously performing error correction and write-back, so that the error correction process is synchronously completed when the configuration data frame is written back, and the data does not need to be cached, so that additional resources are not needed for storing the read-back configuration storage unit data.
Referring to fig. 4, a second embodiment provides a method for correcting single event upset of SRAM-type FPGA, where, on the basis of the first embodiment, the S4 includes: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S7 is performed;
the method further includes steps S7-S9, wherein:
s7: judging whether the configuration data frame needs to be checked again; if the re-verification is required, executing S8; if the re-verification is not required, performing S9;
s8: reading back the configuration data frame according to the configuration frame address, and carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S9 is performed;
s9: and writing the configuration data frame after error correction to the configuration storage unit.
Step S2 may be entered again after step S9.
In the prior art, when programmable resources in an FPGA device are in a working mode, a read-back result of data of a storage unit may be abnormal, which may cause an unreliable diagnosis result of a bit error.
Optionally, S8 to S9 are repeatedly performed, so that a plurality of checks on the configuration data frame are implemented.
The embodiment provides a configurable option, which can support multiple error checks on the configuration data frame, and the reliability of error positioning can be improved by performing multiple data frame readback and checks under the condition of sacrificing efficiency, so that the bit errors of the data of the memory unit can be checked multiple times, and the reliability of a diagnosis result is improved. For example, three checks, four checks, five checks, etc. may be performed on the configuration data frame.
Referring to fig. 2 and 5, a third embodiment provides a single-event-upset error correction circuit, which includes a configuration storage unit 101, a read/write controller 102, a frame address generator 103, an error locator 104, an error correction circuit 105, and an error correction state controller 106, where the read/write controller 102 performs data interaction with the configuration storage unit 101, the frame address generator 103, the error locator 104, the error correction circuit 105, and the error correction state controller 106, respectively, the error locator 104 performs data interaction with the error correction circuit 105, and the error correction state controller 106 performs data interaction with the configuration storage unit 101, the frame address generator 103, the error locator 104, and the error correction circuit 105, respectively.
The configuration storage unit 101 is configured to store FPGA configuration data, and the FPGA configuration data is stored in the configuration storage unit 101 by taking a frame as a unit.
The read/write controller 102 is used to implement the conversion of address/data and other circuit interfaces of the configuration memory unit 101.
The frame address generator 103 is used to generate an access address for the configuration memory unit 101.
The error locator 104 is used for configuring the data ECC decoding of the data in the memory unit 101 and locating the error occurrence and the error data bits. ECC decoding and error location is a tightly coupled process.
The error correction circuit 105 is configured to automatically correct the error data bits in the configuration frame data of the configuration storage unit 101 according to the error data location information input by the error locator 104, and initiate a data write-back action to the configuration storage unit 101.
The error correction state controller 106 is used for overall process control of the read/write controller 102 and the ECC circuit. Fig. 2 depicts the work flow of the single event upset error correction circuit, and the whole work flow is controlled by the error correction state controller 106.
The error correction state controller 106 performs steps S1-S6.
S1: and starting the single event upset error correction circuit.
Enabling ECC is a switching step of the entire error correction circuit. For the SRAM type FPGA, after configuration data is downloaded, the data is stored in the configuration storage unit 101, and at this time, a user can select whether to turn on the single event upset error correction function. When the single event upset error correction circuit is activated, the process proceeds to step S2.
S2: the configuration frame address output by the frame address generator 103 is acquired.
This step resets the frame address generator 103. When the single event upset error correction circuit is activated, the frame address generator 103 will be reset so that the output configuration frame address is set to the start address (typically 0). The enabling of the single event upset error correction circuit is not the only condition for proceeding to step S2, and when the configuration frame error data is corrected and written back (step S9), or the frame address is counted to the maximum frame address, the workflow will also return to step S2.
S3: and reading the configuration data frame from the configuration storage unit 101 according to the configuration frame address.
This step reads the configuration data frame in the configuration storage unit 101, and specifically, reads out one complete configuration data frame from the configuration storage unit 101 according to the configuration frame address information output by the frame address generator 103. Optionally, the configuration data frame includes n-bit data bits and m-bit check bits, and the m-bit check bits perform error check and location on the n-bit data bits and the m-bit check bits in the configuration data frame; wherein n and m are positive integers. Further preferably, the n-bit data bits and the m-bit check bits in the configuration data frame may both be binary data bits.
S4: error checking and locating the configuration data frame by the error locator 104; if no error data bit is found, go to S5; if a single error data bit is found, the configuration data frame is corrected by the error correction circuit 105, and the configuration data frame after error correction is written back to the configuration storage unit 101 by the read/write controller 102.
Specifically, the error locator 104 may perform error checksum locating on the configuration data frame in a pipelined manner by k data bits at a time; wherein k is a positive integer and k is divisible by n; the read/write controller 102 writes the error-corrected configuration data frame back to the configuration storage unit 101 in a pipelined manner according to k data bits at a time.
And recording the error check sum positioning as error positioning A. The readback data from step S3 is fed to the error locator 104 in a pipelined manner, where k can be divided by n every time k data is fed. When n data bits are completely entered, the error locator 104 will determine whether an erroneous data bit has occurred in the configuration data frame. If the number of error data bits is 1, the error locator 104 will indicate the specific position (0-n) of the error data bits in the configuration frame; if the number of error data bits is greater than 1, the error cannot be corrected and can only be resolved by refreshing the FPGA configuration, which is not within the scope of the present disclosure.
If an error A is found, this is a decision step. If no error data bit is found according to the error check result obtained in step S4, go to step S5; if a single erroneous data bit is found, the process proceeds to step S7.
S5: judging whether the configuration frame address output by the frame address generator 103 is the maximum frame address; if the frame address is the maximum frame address, performing S2; if not, S6 is executed.
It is a judgment step whether the currently output configuration frame address of the frame address generator 103 is the maximum frame address. On the premise that no error data bit is found, judging whether the current output frame address of the frame address generator 103 is the maximum frame address, if so, entering the step S2, and resetting the frame address generator 103; if not, the process proceeds to step S7.
S6: the frame address generator 103 is driven to generate the next configuration frame address and S2 is performed.
This step will drive the frame address generator 103 to generate the next configuration frame address. It should be noted that the frame address +1 is not simply an incremental addition, but needs to interact with the read/write controller 102 to obtain the next valid frame address, because the arrangement of the frame addresses is not always in the form of a pure incremental number. After the next configuration frame address is generated, the work flow returns to S2.
Further preferably, the S4 includes: error checking and locating the configuration data frame by the error locator 104; if no error data bit is found, go to S5; if a single erroneous data bit is found, S7 is performed.
The error correction state controller 106 further performs steps S7-S9, in which:
s7: judging whether the configuration data frame needs to be checked again; if the re-verification is required, executing S8; if the re-verification is not required, S9 is performed.
Whether to perform secondary detection is a judgment step. This step judges whether the configuration data frame error detection needs to be carried out for the second time, if need to carry out the second detection, enter step S8; if the secondary detection is not required, the flow proceeds to step S9.
S8: reading back the configuration data frame from the configuration storage unit 101 according to the configuration frame address, and performing error check and positioning on the configuration data frame through the error positioner 104; if no error data bit is found, go to S5; if a single erroneous data bit is found, S9 is performed.
And recording the error check sum positioning as error positioning B. This step will keep the current configuration frame address, re-read the configuration data frame from the configuration storage unit 101, and perform error detection and positioning, and after the detection is completed, the process goes to step S9.
If an error B is found, this is a decision step. If no error data bit is found according to the error check result obtained in step S8, go to step S5; if a single erroneous data bit is found, the process proceeds to step S9. Optionally, the error correction state controller 106 may repeatedly perform S8 to S9, implementing multiple checks on the configuration data frame. Steps S8 to S9 may be repeated a plurality of times, and if it is necessary to detect the error data for a third or more times, steps S8 to S9 may be repeated.
S9: the configuration data frame is corrected by the error correction circuit 105, and the configuration data frame after error correction is written back to the configuration storage unit 101 by the read/write controller 102.
The steps S8-S9 may be subdivided into three operations of read-back, error correction, and write-back, but in logical order, these three steps are closely coupled and may be considered to occur near simultaneously for the read/write controller 102. When both the n-bit data bits and the m-bit check bits in the configuration data frame are binary data bits, the error correction circuit 105 may perform binary inversion on the erroneous data bits located in the configuration data frame. After the binary inversion of the positioned error data bits, the k data bits are written back to the configuration storage unit 101 through the read-write controller 102 in a pipeline manner every time, so that the error correction is completed, and the purpose of reducing the SEU effect is achieved.
A thirteenth embodiment provides an electronic device comprising a processor and a memory, the processor executing computer instructions stored by the memory, causing the electronic device to perform any one of the above described SRAM-type FPGA single event upset error correction methods.
A fourteenth embodiment provides a computer storage medium comprising computer instructions that, when run on an electronic device, cause the electronic device to perform any one of the above described SRAM-type FPGA single event upset error correction methods.
The foregoing description and drawings are only for purposes of illustrating the preferred embodiments of the present application and are not intended to limit the present application, which is, therefore, to the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present application.
Claims (10)
1. A single event upset error correction method for SRAM type FPGA is characterized by comprising the following steps:
s1: starting a single event upset error correction circuit;
s2: acquiring a configuration frame address;
s3: reading the configuration data frame from a configuration storage unit according to the configuration frame address;
s4: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single error data bit is found, the configuration data frame is written back to the configuration storage unit after error correction;
s5: judging whether the configuration frame address is the maximum frame address; if the frame address is the maximum frame address, performing S2; if not, go to S6;
s6: a next configuration frame address is generated and S2 is performed.
2. The SRAM-type FPGA single event upset error correction method of claim 1, wherein the S4 comprises: carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S7 is performed;
the method further comprises the following steps:
s7: judging whether the configuration data frame needs to be checked again; if the re-verification is required, executing S8; if the re-verification is not required, performing S9;
s8: reading back the configuration data frame according to the configuration frame address, and carrying out error check and positioning on the configuration data frame; if no error data bit is found, go to S5; if a single erroneous data bit is found, then S9 is performed;
s9: and writing the configuration data frame after error correction to the configuration storage unit.
3. The SRAM-type FPGA single event upset error correction method of claim 2, wherein S8-S9 are repeatedly executed to realize multiple checks on the configuration data frame.
4. The SRAM-type FPGA single event upset error correction method of claim 1, wherein the configuration data frame comprises n-bit data bits and m-bit check bits, and the m-bit check bits perform error check and positioning on the n-bit data bits and the m-bit check bits in the configuration data frame; wherein n and m are positive integers.
5. The SRAM-type FPGA single event upset error correction method of claim 4, wherein said performing error checking and locating on said configuration data frame comprises: performing error check and positioning on the configuration data frame in a pipeline mode according to k data bits each time; wherein k is a positive integer and k is divisible by n;
the writing back the configuration data frame after error correction to the configuration storage unit includes: and writing the configuration data frame after error correction to the configuration storage unit in a pipeline mode according to k data bits each time.
6. The SRAM-type FPGA single event upset error correction method of claim 4, wherein the n-bit data bits and the m-bit check bits in the configuration data frame are binary data bits.
7. The SRAM-type FPGA single event upset error correction method of claim 6, wherein the writing back the configuration data frame after error correction to the configuration storage unit comprises: and writing back the error data bit positioned in the configuration data frame to the configuration storage unit after binary inversion.
8. A single event upset error correction circuit is characterized by comprising a configuration storage unit, a read-write controller, a frame address generator, an error locator, an error correction circuit and an error correction state controller, wherein the error correction state controller executes:
s1: starting the single event upset error correction circuit;
s2: acquiring a configuration frame address output by the frame address generator;
s3: reading the configuration data frame from the configuration storage unit according to the configuration frame address;
s4: performing error checking and positioning on the configuration data frame through the error positioner; if no error data bit is found, go to S5; if a single error data bit is found, error correction is carried out on the configuration data frame through the error correction circuit, and the configuration data frame after error correction is written back to the configuration storage unit through the read-write controller;
s5: judging whether the configuration frame address output by the frame address generator is the maximum frame address; if the frame address is the maximum frame address, performing S2; if not, go to S6;
s6: the frame address generator is driven to generate the next configuration frame address and S2 is performed.
9. An electronic device comprising a processor and a memory, wherein the processor executes computer instructions stored in the memory, so that the electronic device executes the method for single event upset error correction of an SRAM-type FPGA of any one of claims 1 to 7.
10. A computer storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of SRAM-type FPGA single event upset error correction of any one of claims 1 to 7.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112579342A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Memory error correction method, memory controller and electronic equipment |
| CN115297071A (en) * | 2022-07-15 | 2022-11-04 | 中国航空无线电电子研究所 | Fault-tolerant design method for ARINC664 switch engine to SEU and MBU |
| CN115543683A (en) * | 2022-09-21 | 2022-12-30 | 深圳市紫光同创电子有限公司 | Single event upset error correction method and device, electronic equipment and readable storage medium |
| CN117555721A (en) * | 2024-01-12 | 2024-02-13 | 深圳疆泰科技有限公司 | Bit flipping processing method and device for aircraft FPGA |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632757A (en) * | 2005-01-10 | 2005-06-29 | 中国航天时代电子公司第七七一研究所 | Primary particle inversion resistant memory error correction and detection and automatic write back method for spacial computer |
| CN101281481A (en) * | 2008-05-23 | 2008-10-08 | 北京时代民芯科技有限公司 | Method for error correcting and detecting for memory anti-single particle overturn |
| US20140195733A1 (en) * | 2012-08-17 | 2014-07-10 | Andrew C. Russell | Memory Using Voltage to Improve Reliability for Certain Data Types |
| CN104731666A (en) * | 2013-12-23 | 2015-06-24 | 深圳市国微电子有限公司 | Single event upset prevention self-correction integrated circuit and correction method thereof |
| CN106293991A (en) * | 2016-08-10 | 2017-01-04 | 上海无线电设备研究所 | FPGA anti-single particle based on ECC upset fast refresh circuitry and method |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
-
2020
- 2020-04-16 CN CN202010298915.0A patent/CN111459712B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632757A (en) * | 2005-01-10 | 2005-06-29 | 中国航天时代电子公司第七七一研究所 | Primary particle inversion resistant memory error correction and detection and automatic write back method for spacial computer |
| CN101281481A (en) * | 2008-05-23 | 2008-10-08 | 北京时代民芯科技有限公司 | Method for error correcting and detecting for memory anti-single particle overturn |
| US20140195733A1 (en) * | 2012-08-17 | 2014-07-10 | Andrew C. Russell | Memory Using Voltage to Improve Reliability for Certain Data Types |
| CN104731666A (en) * | 2013-12-23 | 2015-06-24 | 深圳市国微电子有限公司 | Single event upset prevention self-correction integrated circuit and correction method thereof |
| CN106293991A (en) * | 2016-08-10 | 2017-01-04 | 上海无线电设备研究所 | FPGA anti-single particle based on ECC upset fast refresh circuitry and method |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112579342A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Memory error correction method, memory controller and electronic equipment |
| CN112579342B (en) * | 2020-12-07 | 2024-02-13 | 海光信息技术股份有限公司 | Memory error correction method, memory controller and electronic equipment |
| CN115297071A (en) * | 2022-07-15 | 2022-11-04 | 中国航空无线电电子研究所 | Fault-tolerant design method for ARINC664 switch engine to SEU and MBU |
| CN115297071B (en) * | 2022-07-15 | 2023-10-27 | 中国航空无线电电子研究所 | Fault-tolerant design method for SEU and MBU by switch engine of ARINC664 switch |
| CN115543683A (en) * | 2022-09-21 | 2022-12-30 | 深圳市紫光同创电子有限公司 | Single event upset error correction method and device, electronic equipment and readable storage medium |
| CN117555721A (en) * | 2024-01-12 | 2024-02-13 | 深圳疆泰科技有限公司 | Bit flipping processing method and device for aircraft FPGA |
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