CN112000526A - Low-cost minisatellite important data fault-tolerant method - Google Patents

Low-cost minisatellite important data fault-tolerant method Download PDF

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CN112000526A
CN112000526A CN202010879195.7A CN202010879195A CN112000526A CN 112000526 A CN112000526 A CN 112000526A CN 202010879195 A CN202010879195 A CN 202010879195A CN 112000526 A CN112000526 A CN 112000526A
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CN112000526B (en
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吕达
李志刚
李军予
李超
熊浩伦
王啓宁
韩延东
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Aerospace Dongfanghong Satellite Co Ltd
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1637—Error detection by comparing the output of redundant processing systems using additional compare functionality in one or some but not all of the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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Abstract

A low-cost fault-tolerant method for important data of a small satellite is characterized in that each program control command comprises a task number, time and a command code and also comprises an error correction code, and the command and the corresponding error correction code are stored after the satellite host checks the correctness when the program control command is injected. Before the program control command is executed or when the satellite center computer runs a periodic error detection program, error detection and correction are carried out on the program control command through error correction codes. The invention can carry out error correction coding aiming at data with different lengths, and achieve the capability that data with kbit length can detect 2-bit errors and correct 1-bit errors. Compared with hardware EDAC, the method of the invention has good universality, does not need to increase hardware EDAC chips or FPGA, and is very beneficial to the realization of low-cost satellites based on commercial shelf products; compared with the traditional triple-modular redundancy method, the method can save the storage space to a great extent, can refresh periodically, and solves the problem that the triple-modular redundancy method fails due to single event upset accumulation during long-term on-track operation.

Description

Low-cost minisatellite important data fault-tolerant method
Technical Field
The invention relates to a low-cost minisatellite important data error correction method which is used for error detection and correction of minisatellite important data and overcoming the spatial single event effect. Important data includes program control commands, program control data blocks, relative program control commands, thermal control data, load data, and the like.
Background
With the explosive growth of commercial satellite launching, the business requirements of commercial aerospace can not be met according to the traditional large satellite research and development period of 3-5 years. Aerospace-grade devices widely applied in spacecrafts are often prohibited to be transported, long in supply period, several times higher in price than COTS devices with the same functions, and 2-3 generations behind performance, so that a commercial current goods (COTS) product is adopted to replace an aerospace-grade product, and the aerospace-grade device becomes a main direction of commercial aerospace development. When commercial off-the-shelf products are applied to small satellites, the problem of Single Event Upset (SEU) caused by space radiation is generally encountered, and important satellite data such as program control instructions, program control data blocks, relative program control instructions and stored load data need to be stored for a long time, so that the SEU resistance design is required. Currently, anti-SEU designs widely employ error detection and correction (EDAC) or Triple Modular Redundancy (TMR) techniques. The traditional EDAC technology is realized by a special hardware circuit or an FPGA chip, but the small satellite is developed based on a commercial goods shelf product system due to the requirements of small volume, light weight, low power consumption, low development cost and short period, industrial-grade components and even whole machine spot products are applied, and the method for realizing hardware EDAC by modifying the circuit and increasing the EDAC chip or the FPGA is not applicable. The TMR technology can resist SEU, but occupies 3 times of storage space of data to be protected, is often unacceptable when the data volume is large, and the 3-out-of-2 method fails due to the possible single event upset accumulation along with long-term on-track operation.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method overcomes the defects of the prior art and provides an important data fault-tolerant method suitable for a low-cost satellite based on a commercial shelf system. And performing extended Hamming coding on the length of each piece of important data, such as 9 bytes of a program control command, 6 bytes of a relative program control command and 15 bytes of a program control data block, wherein each command contains a corresponding error correcting code. And each instruction contains a corresponding error correction code during initialization or program control uploading, and the house service center computer stores each program control instruction and the corresponding error correction code respectively. Before each program control instruction is executed or when the error is detected periodically, error detection and correction are executed on each instruction.
The technical solution of the invention is as follows:
a low-cost fault tolerance method for important data of a small satellite comprises the following steps:
1) determining the number r of bits of an instruction data parity bit
Carrying out extended Hamming code coding, wherein r bit supervision bits are correspondingly generated by k bit instruction data, and the data length n of each group of coded relative program control instructions is k + r, wherein the information bits of the instruction data comprise: d1～DkThe supervision position comprises: p1～PrDefinition of PrIs a global supervisory bit;
2) distributing the address of information bit and the address of monitor bit to obtain n r bit binary codes
21) Assigning the jth parity bit PjAddress of is corresponding to 2j-1(ii) a Information bit DiSequentially distributing n addresses [1, n ] from small to large according to the number i]Addresses not occupied by the supervisor bits; acquiring k addresses of information bits and r addresses of supervision bits; i is an e [1, k ]]，j∈[1，r](ii) a i and j are positive integers;
22) increase all n address values by 2r-1Then converting into r-bit binary code; numbering the elements in each binary code from low order to high order by j;
3) determining the values of r supervision bits according to binary coding; the jth supervisory bit PjThe method for determining the value of (1) specifically comprises the following steps:
obtaining the XOR sum value of the information bit data corresponding to all binary codes with j-th bit element being 1 in the k binary codes as the supervision bit PjA value of (d);
4) repeating the steps 1) -3), coding the plurality of pieces of instruction data to obtain coded instruction data and performing group detection and annotation; each upper note frame comprises a synchronous word, a frame length, a CRC value, a plurality of instruction data and a supervision bit corresponding to each instruction data;
5) the house keeping center computer receives the upper note frame in the step 4), and stores a plurality of pieces of instruction data in the upper note frame and the corresponding supervision bits of each piece of instruction data after judging that the synchronization word, the frame length and the CRC of the upper note frame are correct;
6) before a star service center computer starts to operate each piece of instruction data, the values of r syndromes of the instruction data are calculated in real time, and whether single event upset occurs or not is judged according to the values of the r syndromes, which specifically comprises the following steps:
if the values of the r syndromes are equal to 0, judging that single event upset does not occur;
if the values of the r syndromes are not all equal to 0, and syndrome SrIf the value of (1) is equal to 1, judging that a 1-bit error occurs, and entering step 7);
if the values of the r syndromes are not all equal to 0, and syndrome SrIf the value of (1) is equal to 0, it is determined that an even bit error has occurred;
7) and back checking to determine the error code occurrence position.
Step 1), r and k satisfy the following relational expression:
2r-1-1≥k+r-1。
the house keeping center computer detects the error of the m instructions according to the value of the syndrome according to the task period and judges whether the single event upset happens or not; m is determined according to the processing capacity of the processor, and the original task of the processor is not influenced; wherein m is a positive integer.
Step 6) the method for calculating the values of the r syndromes specifically comprises:
for the jth syndrome SjThe value of (b) is equal to the XOR sum value of the supervision bit data and the information bit data corresponding to all binary codes with j-th bit element being 1 in the n binary codes; srFor the global syndrome, define SrIs equal to the xor-sum of n all supervisory bit data and information bit data.
Step 7) the method for determining the error code occurrence position by reverse checking specifically comprises the following steps:
in the n r-bit binary codes obtained in the step 2), binary codes corresponding to the r syndrome values calculated in the step 6) are searched to obtain corresponding binary codes, and information bits or supervision bits corresponding to the same addresses as the binary codes, namely error code generating positions, are obtained.
And 6) after judging that the even-numbered bit error occurs, setting the count of a double-bit error counter to be increased by 1, and resetting the satellite service center computer after the count of the double-bit error counter is higher than a safety threshold value.
Compared with the prior art, the invention has the beneficial effects that:
1) the invention realizes error detection and correction of important data through software, does not change the original hardware structure, does not need to increase a hardware EDAC chip or FPGA, and is suitable for low-cost satellites adopting commercial goods shelf product systems;
2) compared with the triple modular redundancy method, the method occupies less memory and only needs to allocate the storage space to the supervision bit. If the data length to be protected is N bytes, the storage space occupied by the invention is about 1.16N for the case of selecting (56,48) the extended Hamming code relative to the program control instruction, and the storage space occupied by the invention is about 1.11N for the case of selecting (80,72) the extended Hamming code relative to the program control instruction. The triple modular redundancy method occupies 3N of storage space, and because the satellite service center computer stores thousands of program control instructions, program control data blocks, and relative program control instructions and load important data, the invention can greatly save the storage space and solve the problem of internal memory shortage;
3) the method of the invention can periodically detect the error, and if the method is used in an on-orbit mode for a long time, the accumulation can occur due to the single event turnover, so that the triple modular redundancy method has effective risk. The invention adopts the data error detection task to operate periodically, can finish the error detection and correction of m pieces of important data per period, and avoids the risk of errors occurring in two parts due to the long-term accumulation of triple modular redundancy method by the single event effect.
Drawings
FIG. 1 is a schematic diagram of the present invention for encoding kbit data with extended Hamming codes;
FIG. 2 is a diagram of a plurality of important data framing;
FIG. 3 is a schematic diagram of a plurality of important data stores;
FIG. 4 is a flowchart of the task of error detection and correction of data according to the present invention.
Detailed Description
The invention provides a low-cost satellite important data fault-tolerant method, which is characterized in that when a system is initialized or instructions are injected, program-controlled data are subjected to extended Hamming code encoding, and when the instructions are checked to be correct, a satellite service center computer stores the instructions and an error correcting code together. Before each cycle or each instruction is started, error detection and correction are carried out. The important data comprises program control instructions, program control data blocks, relative program control instructions, thermal control data, load important data and the like.
The invention discloses a low-cost fault tolerance method for important data of a small satellite, which comprises the following steps of:
1) determining the number r of bits of a parity bit required for error correction of instruction data
When each important instruction data is made as a relative program control instruction (kbit), extended Hamming code coding is carried out, r-bit supervision bits are correspondingly generated by k-bit data, and r and k meet the relation (1);
2r-1-1≥k+r-1 (1)
after encoding, the data length n of each group of the relative program control commands is k + r, wherein the information bits of the command data comprise: d1～DkThe supervision position comprises: p1～PrDefinition of PrIs a global supervisory bit.
2) Distributing the address of information bit and the address of monitor bit to obtain n r bit binary codes
21) Assigning the jth parity bit PjAddress of is corresponding to 2j-1(ii) a In the embodiment of the invention, the supervision bits P0-P6 sequentially allocate addresses 1, 2, 4, 8, … and 2r-2. Information bit DiSequentially distributing n addresses [1, n ] from small to large according to the number i]Addresses not occupied by the supervisor bits; i.e., 3, 5, 6, 7, …; acquiring k addresses of information bits and r addresses of supervision bits; i is an e [1, k ]]，j∈[1，r](ii) a i and j are positive integers;
22) increase all n address values by 2r-1After conversion to rBinary encoding of the bits; the elements in each binary are numbered sequentially from low to high j. In the embodiment of the present invention, taking the relative program control command as an example, k is taken as 48, r is taken as 7, and the relationship between the syndrome and the error code position is defined as shown in table 1.
3) Determining r parity bits P from the binary codejIn the embodiment of the present invention, the values of 7 supervision bits { P0-P6 } are defined. The jth supervisory bit PjThe method for determining the value specifically comprises the following steps:
obtaining the XOR sum value of the information bit data corresponding to all binary codes with j-th bit element being 1 in the k binary codes as the supervision bit PjA value of (d); the information bit data of the instruction data adopts binary coding;
in the embodiment of the present invention, when error correction coding is performed, the values of the parity bits P0, …, and P6 are expressed by the following formulas (2) to (8):
S0＝0＝D0+D1+D3+D4+D6+D8+D10+D11+D13+D15+D17+┅P0 (2)
S1＝0＝D0+D2+D3+D5+D6+D9+D10+D12+D13+D16+D17+┅P1 (3)
S2＝0＝D1+D2+D3+D7+D8+D9+D10+D14+D15+D16+D17+┅P2 (4)
S3＝0＝D4+D5+D6+D7+D8+D9+D10+D18+D19+D20+D21+┅P3 (5)
S4＝0＝D11+D12+D13+D14+D15+D16+D17+D18+D19+D20+┅P4 (6)
S5＝0＝D26+D27+D28+D29+D30+D31+D32+D33+D34+D35+┅P5 (7)
S6＝0＝D0+D1+D2+D3+D4+D5+D6+Dk-1+┅+P0+P1+┅+P6 (8)
4) and (3) repeating the steps 1) to 3), and carrying out coding processing on a plurality of pieces of instruction data (such as program control instructions) to obtain coded instruction data and detecting and annotating the coded instruction data in a group, as shown in the format of fig. 2. Each upper note frame comprises a synchronous word, a frame length, a CRC value, a plurality of instruction data and a supervision bit corresponding to each instruction data;
5) the house keeping center computer receives the upper note frame (program control frame) noted in the step 4), and stores a plurality of instruction data (program control instructions) in the upper note frame and the corresponding supervision bits of each instruction data after judging that the synchronization word, the frame length and the CRC of the upper note frame are correct, as shown in fig. 3;
6) before the start of the operation of each instruction data by the satellite service center computer, the values of r syndromes of the instruction data are calculated in real time, and whether single event upset occurs or not is judged according to the values of the r syndromes. The method for calculating the r syndrome values specifically includes:
for the jth syndrome SjThe value of (b) is equal to the XOR sum value of the supervision bit data and the information bit data corresponding to all binary codes with j-th bit element being 1 in the n binary codes; srFor the global syndrome, define SrThe value of (a) is equal to the exclusive or sum value of n all supervisory bit data and information bit data; as shown in table 1, the value of the syndrome S0 in the embodiment of the present invention is equal to the xor sum of the parity bit data and the information bit data corresponding to the binary code whose right 1 st bit (i.e., the lowest bit of the binary code) is 1; the value of S1 is equal to the XOR sum of the supervisory bit data and the information bit data corresponding to the binary code with the 2 nd bit at the right side of the binary code being 1, and so on, S6 is the global syndrome, and the value of S6 is the XOR sum of all the supervisory bit data and the information bit data. The specific formula is as follows:
S0＝D0+D1+D3+D4+D6+D8+D10+D11+D13+D15+D17+…+P0 (9)
S1＝D0+D2+D3+D5+D6+D9+D10+D12+D13+D16+D17+…+P1 (10)
S2＝D1+D2+D3+D7+D8+D9+D10+D14+D15+D16+D17+…+P2 (11)
S3＝D4+D5+D6+D7+D8+D9+D10+D18+D19+D20+D21+…+P3 (12)
S4＝D11+D12+D13+D14+D15+D16+D17+D18+D19+D20+…+P4 (13)
S5＝D26+D27+D28+D29+D30+D31+D32+D33+D34+D35+…+P5 (14)
S6＝D0+D1+D2+D3+D4+D5+D6+D47+…+P0+P1+…+P6 (15)
step 6) the method for judging whether the single event upset happens or not according to the value of the syndrome specifically comprises the following steps:
if the values of r syndromes (namely the values of 7 syndromes { S6-S0 } are equal to 0), judging that single event upset does not occur;
if the value of r syndromes (i.e. 7 syndromes)Values of { S6-S0 } are not all equal to 0, and syndrome SrIf the value of (1) is equal to 1, judging that a 1-bit error occurs, and entering step 7);
if the values of the r syndromes (i.e., the values of the 7 syndromes S6-S0) are not all equal to 0, and S isrIf the value is equal to 0, judging that an even bit error occurs, and entering the step 8);
7) the method for determining the error code occurrence position by reverse checking specifically comprises the following steps:
in the n r-bit binary codes obtained in the step 2), binary codes corresponding to the r syndrome values calculated in the step 6) are searched to obtain corresponding binary codes, and information bits or supervision bits corresponding to the same addresses as the binary codes, namely error code generating positions, are obtained. In the embodiment of the invention, the error code generating position is determined and corrected according to the corresponding relation between the corrector and the error code position in the table 1. If the data of S6-S0 is equal to 1000011, the data of the group D0 is indicated to have errors in position.
8) And setting the count of the double-bit error counter to be increased by 1, and resetting the star service center computer after the count of the double-bit error counter is higher than a safety threshold value.
The house keeping center computer detects the error of the m instructions according to the value of the syndrome according to the task period and judges whether the single event upset happens or not; m is determined according to the processing capacity of the processor, and the original task of the processor is not influenced. Wherein m is a positive integer.
Table 1 syndrome-error position correspondence table (k is 48, r is 7)
Figure BDA0002653590920000071
Figure BDA0002653590920000081
Figure BDA0002653590920000091
The method of the invention is used for testing a small satellite integrated electronic computer. The data targeted by fault injection comprises relative program control instructions, program control data blocks, load data and the like of the small satellites, the program control instruction error correction algorithm adopts expanded Hamming codes (80,72), the relative program control instruction error correction algorithm adopts expanded Hamming codes (56,48), and the program control data blocks adopt codes (128,120). After the data are uploaded, a 1bit error and a 2bit error are generated on the data by a method of modifying the memory of the satellite service host. The fault of each data type is injected 100 times randomly, and the method can effectively detect and correct the error. The test results are shown in table 2.
TABLE 2 test results
Figure BDA0002653590920000092
The above description is only one embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.

Claims (6)

1. A low-cost fault tolerance method for important data of a small satellite is characterized by comprising the following steps:
1) determining the number r of bits of an instruction data parity bit
Carrying out extended Hamming code coding, wherein r bit supervision bits are correspondingly generated by k bit instruction data, and the data length n of each group of coded relative program control instructions is k + r, wherein the information bits of the instruction data comprise: d1～DkThe supervision position comprises: p1～PrDefinition of PrIs a global supervisory bit;
2) distributing the address of information bit and the address of monitor bit to obtain n r bit binary codes
21) Assigning the jth parity bit PjAddress of is corresponding to 2j-1(ii) a Information bit DiFrom small to large according to the number iSub-allocating n addresses [1, n ]]Addresses not occupied by the supervisor bits; acquiring k addresses of information bits and r addresses of supervision bits; i is an e [1, k ]]，j∈[1，r](ii) a i and j are positive integers;
22) increase all n address values by 2r-1Then converting into r-bit binary code; numbering the elements in each binary code from low order to high order by j;
3) determining the values of r supervision bits according to binary coding; the jth supervisory bit PjThe method for determining the value of (1) specifically comprises the following steps:
obtaining the XOR sum value of the information bit data corresponding to all binary codes with j-th bit element being 1 in the k binary codes as the supervision bit PjA value of (d);
4) repeating the steps 1) -3), coding the plurality of pieces of instruction data to obtain coded instruction data and performing group detection and annotation; each upper note frame comprises a synchronous word, a frame length, a CRC value, a plurality of instruction data and a supervision bit corresponding to each instruction data;
5) the house keeping center computer receives the upper note frame in the step 4), and stores a plurality of pieces of instruction data in the upper note frame and the corresponding supervision bits of each piece of instruction data after judging that the synchronization word, the frame length and the CRC of the upper note frame are correct;
6) before a star service center computer starts to operate each piece of instruction data, the values of r syndromes of the instruction data are calculated in real time, and whether single event upset occurs or not is judged according to the values of the r syndromes, which specifically comprises the following steps:
if the values of the r syndromes are equal to 0, judging that single event upset does not occur;
if the values of the r syndromes are not all equal to 0, and syndrome SrIf the value of (1) is equal to 1, judging that a 1-bit error occurs, and entering step 7);
if the values of the r syndromes are not all equal to 0, and syndrome SrIf the value of (1) is equal to 0, it is determined that an even bit error has occurred;
7) and back checking to determine the error code occurrence position.
2. The low-cost small satellite important data fault-tolerant method according to claim 1, wherein r and k in step 1) satisfy the following relation:
2r-1-1≥k+r-1。
3. the low-cost microsatellite important data fault-tolerant method according to claim 1 is characterized in that the housekeeping center computer performs error detection on m instructions according to the value of the syndrome according to the task period, and judges whether single event upset occurs or not; m is determined according to the processing capacity of the processor, and the original task of the processor is not influenced; wherein m is a positive integer.
4. A low-cost small satellite important data fault-tolerant method according to any one of claims 1 to 3, wherein the calculation method of the r syndrome values in step 6) is specifically:
for the jth syndrome SjThe value of (b) is equal to the XOR sum value of the supervision bit data and the information bit data corresponding to all binary codes with j-th bit element being 1 in the n binary codes; srFor the global syndrome, define SrIs equal to the xor-sum of n all supervisory bit data and information bit data.
5. The low-cost fault-tolerant method for essential data of small satellites as claimed in claim 4, wherein the step 7) of back-checking the method for determining the occurrence position of the error code comprises:
in the n r-bit binary codes obtained in the step 2), binary codes corresponding to the r syndrome values calculated in the step 6) are searched to obtain corresponding binary codes, and information bits or supervision bits corresponding to the same addresses as the binary codes, namely error code generating positions, are obtained.
6. The low-cost microsatellite important data fault-tolerant method as recited in claim 4 wherein after judging that an even bit error occurs in step 6), the method further comprises the steps of setting the count of the double bit error counter to be increased by 1, and resetting the satellite service center computer after the count of the double bit error counter is higher than a safety threshold.
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