CN112000526B - Low-cost small satellite important data fault tolerance method - Google Patents
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Abstract
A fault-tolerant method for important data of low-cost small satellite includes such steps as providing each program-controlled instruction with task number, time and instruction code, error correction code, and storing the instruction and error correction code. When the program control instruction is executed or the star service center computer runs the periodic error detection program, the error detection and correction are carried out on the program control instruction through error correction coding. The invention can carry out error correction coding aiming at data with different lengths, thereby achieving the capability of detecting 2bit errors and correcting 1bit errors of kbit length data. Compared with hardware EDAC, the method of the invention has good universality, does not need to add a hardware EDAC chip or FPGA, and is very beneficial to low-cost satellite realization based on commercial goods shelf products; compared with the traditional triple-modular redundancy method, the method has the advantages that the storage space can be saved to a great extent, the periodic refreshing can be realized, and the problem that the triple-modular redundancy method fails due to single event upset accumulation in long-term on-track operation is solved.
Description
Technical Field
The invention relates to a low-cost error correction method for important data of a small satellite, which is used for detecting and correcting errors of the important data of the small satellite and overcoming the effect of space single particles. The important data comprises program control instructions, program control data blocks, relative program control instructions, thermal control data, load data and the like.
Background
With the explosive growth of commercial satellite emission, the large satellite research and development period of 3-5 years is not capable of meeting the business requirements of commercial aerospace. The aerospace-grade device widely applied in the spacecraft is often forbidden to operate, the supply period is long, the price is several times higher than that of the COTS device with the same function, and the performance is 2-3 generations behind, so that the use of commercial off-the-shelf (COTS) products instead of aerospace-grade products becomes a main direction of commercial aerospace development. When commercial spot products are applied to small satellites, the problem of Single Event Upset (SEU) caused by space radiation is generally faced, and on-board important data such as program control instructions, program control data blocks, relative program control instructions and stored load data need to be stored for a long time, so that SEU-resistant design is required. Current anti-SEU designs widely employ error detection and correction (EDAC) or Triple Modular Redundancy (TMR) techniques. The traditional EDAC technology is realized through a special hardware circuit or an FPGA chip, but the small satellite is subjected to the requirements of small volume, light weight, low power consumption, low development cost and short period, is developed based on a commercial goods shelf product system, is applied to industrial-grade components and even complete machine spot products, and is inapplicable to a hardware EDAC method realized by adding the EDAC chip or the FPGA through modifying the circuit. TMR technology can combat SEU, but occupies 3 times the memory space to protect data, is often unacceptable when the data volume is large, and single event upset accumulation may exist with long-term on-track operation, resulting in 3-fetch 2 approach failure.
Disclosure of Invention
The technical solution of the invention is as follows: the fault-tolerant method for the important data of the low-cost satellite based on the commercial goods shelf system is provided for overcoming the defects of the prior art. And performing extended hamming coding on the length of each important data, such as 9 bytes of the program control instruction, 6 bytes of the relative program control instruction and 15 bytes of the program control data block, namely each instruction contains a corresponding error correction code. When the program control is initialized or the program control is uploaded, each instruction comprises a corresponding error correction code, and the star service center computer stores each program control instruction and the corresponding error correction code respectively. Error detection and correction are performed on each program-controlled instruction when error detection is performed before or periodically executed.
The technical scheme of the invention is as follows:
a fault-tolerant method for important data of a low-cost small satellite comprises the following steps:
1) Determining the bit number r of the instruction data supervisor bits
Performing extended hamming code encoding, wherein k-bit instruction data correspondingly generate r-bit supervision bits, and the data length n=k+r of each group of relative program control instructions after encoding, wherein the information bits of the instruction data comprise: d (D) 1 ～D k The supervision bits include: p (P) 1 ～P r Definition of P r Is a global supervision bit;
2) Distributing the address of the information bit and the address of the supervision bit to obtain n r-bit binary codes
21 A) assigning a jth supervisor bit P j The address of (2) corresponds to 2 j-1 The method comprises the steps of carrying out a first treatment on the surface of the Information bit D i N addresses [1, n ] are allocated in sequence from small to large according to the number i]Addresses not occupied by the monitor bits; obtaining k addresses of information bits and r addresses of supervision bits; i epsilon [1, k]，j∈[1，r]The method comprises the steps of carrying out a first treatment on the surface of the i and j are positive integers;
22 Increasing all n address values by 2 r-1 Converting the binary code into r bits; sequentially numbering j from low order to high order elements in each binary code;
3) Determining the values of r supervision bits according to the binary code; the j-th supervision bit P j The method for determining the value of (a) specifically comprises the following steps:
obtaining the exclusive or sum value of the information bit data corresponding to the binary code with the j-th bit element being 1 in the k binary codes as the supervision bit P j Is a value of (2);
4) Repeating the steps 1) to 3), encoding the plurality of instruction data to obtain encoded instruction data and grouping the encoded instruction data for uploading; each uploading frame comprises a synchronous word, a frame length, a CRC value, a plurality of instruction data and a supervision bit corresponding to each instruction data;
5) The star service center computer receives the uploading frame uploaded in the step 4), and stores and processes a plurality of instruction data in the uploading frame and supervision bits corresponding to each instruction data after judging that the synchronization word, the frame length and the CRC of the uploading frame are correct;
6) Before a star service center computer starts to run each piece of instruction data, calculating the values of r syndromes of the instruction data in real time, and judging whether single event upset occurs according to the values of r syndromes, wherein the method specifically comprises the following steps:
if the values of the r syndromes are equal to 0, judging that single event upset does not occur;
if the value of r syndromes is not equal to 0, syndrome S r If the value of (2) is equal to 1, judging that 1bit error occurs, and entering step 7);
if the value of r syndromes is not equal to 0, syndrome S r If the value of (2) is equal to 0, judging that even bit errors occur;
7) And determining the occurrence position of the error code by inverse checking.
Step 1) the r and k satisfy the following relation:
2 r-1 -1≥k+r-1。
the star service center computer detects the error of m instructions according to the value of the syndrome according to the task period and judges whether single event upset occurs or not; m is determined according to the processing capacity of the processor, and the original task of the processor is not affected; wherein m is a positive integer.
Step 6) the calculation method of the r syndrome values specifically comprises the following steps:
for the j-th syndrome S j The value of (2) is equal to the exclusive or sum value of the supervision bit data and the information bit data corresponding to the binary code with the j-th bit element being 1 in the n binary codes; s is S r For global syndromes, define S r The value of (2) is equal to the exclusive or sum of n all the parity bit data and the information bit data.
The method for determining the occurrence position of the error code by inverse checking in the step 7) specifically comprises the following steps:
searching binary codes corresponding to the r syndrome values calculated in the step 6) in the n r-bit binary codes obtained in the step 2), and obtaining corresponding binary codes, wherein information bits or supervision bits corresponding to the same address as the binary codes, namely error code occurrence positions.
And 6) after judging that the even number bit errors occur, the method further comprises the steps of setting a double-bit error counter to count by 1, and resetting the star service center computer after the double-bit error counter counts higher than a safety threshold.
Compared with the prior art, the invention has the beneficial effects that:
1) The invention realizes the error detection and correction of important data through software, does not change the original hardware structure, does not need to increase a hardware EDAC chip or FPGA, and is suitable for low-cost satellite using commercial shelf product system;
2) Compared with the triple-modular redundancy method, the invention occupies less memory and only needs to allocate memory space for the supervision bits. If the data length to be protected is N bytes, the memory space is about 1.16N for the extended Hamming code case selected (56, 48) relative to the program control instruction, and about 1.11N for the extended Hamming code selected (80,72) relative to the program control instruction. The three-mode redundancy method occupies 3N of storage space, and because the star service center computer stores thousands of program control instructions, program control data blocks and relative program control instructions and load important data, the invention can greatly save the storage space and solve the problem of internal memory tension;
3) The method can periodically detect errors, and if the method is used for a long time on orbit, accumulation can occur due to single event upset, and the triple modular redundancy method has effective risk. The invention adopts the data error detection task to run periodically, can finish error detection and correction of m pieces of important data in each period, and avoids the risk of error occurrence of two triple modular redundancy methods accumulated for a long time due to a single event effect.
Drawings
FIG. 1 is a diagram of the extended Hamming code encoding of kbit data according to the present invention;
FIG. 2 is a schematic diagram of a plurality of important data framing;
FIG. 3 is a schematic diagram of a plurality of important data stores;
FIG. 4 is a flow chart of the error detection and correction task of the data according to the present invention.
Detailed Description
The invention provides a fault-tolerant method for important data on a low-cost satellite, which is characterized in that program-controlled data are subjected to extended Hamming code coding when a system is initialized or instructions are injected, and a star service center computer stores instructions and error correction codes together when the correctness is checked. Error detection and correction are performed every cycle or before each instruction is started. The important data comprises program control instructions, program control data blocks, relative program control instructions, thermal control data, load important data and the like.
The invention discloses a fault tolerance method for important data of a low-cost small satellite, which comprises the following steps:
1) Determining the number of bits r of a supervisor bit required for error correction of instruction data
Each important instruction data is subjected to extended Hamming code encoding when a relative program control instruction (kbit) is manufactured, r bit supervision bits are correspondingly generated by k bit data, and r and k meet a relation formula (1);
2 r-1 -1≥k+r-1 (1)
the data length n=k+r of each group of relative program control instructions after encoding, wherein the information bits of the instruction data comprise: d (D) 1 ～D k The supervision bits include: p (P) 1 ～P r Definition of P r Is a global supervision bit.
2) Distributing the address of the information bit and the address of the supervision bit to obtain n r-bit binary codes
21 A) assigning a jth supervisor bit P j The address of (2) corresponds to 2 j-1 The method comprises the steps of carrying out a first treatment on the surface of the In the embodiment of the invention, the supervision bits P0-P6 are sequentially allocated with addresses 1, 2, 4, 8, … and 2 r-2 . Information bit D i N addresses [1, n ] are allocated in sequence from small to large according to the number i]Addresses not occupied by the monitor bits; i.e., 3, 5, 6, 7, …; obtaining k addresses of information bits and r addresses of supervision bits; i epsilon [1, k]，j∈[1，r]The method comprises the steps of carrying out a first treatment on the surface of the i and j are positive integers;
22 Increasing all n address values by 2 r-1 Converting the binary code into r bits; the elements in each binary are numbered j sequentially from low order to high order. In the embodiment of the invention, taking a relative program control instruction as an example, k is 48, r is 7, and the relation between the defined syndrome and the error code position is shown in table 1.
3) Determining r parity bits P based on binary encoding j In the embodiment of the present invention, values of 7 monitor bits { P0 to P6} are defined. The j-th supervision bit P j The value determining method specifically comprises the following steps:
obtaining the exclusive or sum value of the information bit data corresponding to the binary code with the j-th bit element being 1 in the k binary codes as the supervision bit P j Is a value of (2); information bit data acquisition of instruction dataBinary encoding;
in the embodiment of the invention, when error correction coding is performed, the values of the supervision bits P0, … and P6 are shown in the formulas (2) to (8):
S0＝0＝D0+D1+D3+D4+D6+D8+D10+D11+D13+D15+D17+┅P0 (2)
S1＝0＝D0+D2+D3+D5+D6+D9+D10+D12+D13+D16+D17+┅P1 (3)
S2＝0＝D1+D2+D3+D7+D8+D9+D10+D14+D15+D16+D17+┅P2 (4)
S3＝0＝D4+D5+D6+D7+D8+D9+D10+D18+D19+D20+D21+┅P3 (5)
S4＝0＝D11+D12+D13+D14+D15+D16+D17+D18+D19+D20+┅P4 (6)
S5＝0＝D26+D27+D28+D29+D30+D31+D32+D33+D34+D35+┅P5 (7)
S6＝0＝D0+D1+D2+D3+D4+D5+D6+Dk-1+┅+P0+P1+┅+P6 (8)
4) Repeating the steps 1) to 3), encoding a plurality of instruction data (such as program control instructions), obtaining encoded instruction data, and grouping and detecting the upper notes, as shown in the format of fig. 2. Each uploading frame comprises a synchronous word, a frame length, a CRC value, a plurality of instruction data and a supervision bit corresponding to each instruction data;
5) The star service center computer receives the uploading frame (program-controlled frame) uploaded in the step 4), and stores and processes a plurality of instruction data (program-controlled instructions) in the uploading frame and supervision bits corresponding to each instruction data after judging that the synchronization word, the frame length and the CRC of the uploading frame are correct, as shown in figure 3;
6) Before the star service center computer starts to run each piece of instruction data, the values of r syndromes of the instruction data are calculated in real time, and whether single event upset occurs is judged according to the values of r syndromes. The calculation method of the r syndrome values specifically comprises the following steps:
for the j-th syndrome S j The value of (2) is equal to the exclusive or sum value of the supervision bit data and the information bit data corresponding to the binary code with the j-th bit element being 1 in the n binary codes; s is S r For global syndromes, define S r The value of (2) is equal to the exclusive or sum value of all of the n parity bit data and the information bit data; as shown in Table 1, the present invention was practicedIn the example, the value of the syndrome S0 is equal to the exclusive or sum of the supervision bit data and the information bit data corresponding to the binary code with the 1 st bit (namely the lowest bit of the binary code) on the right side being 1; the value of S1 is equal to the exclusive or sum of the information bit data and the supervisory bit data corresponding to the binary code with the 2 nd bit of the binary code being 1, and the like, S6 is a global syndrome, and the value of S6 is the exclusive or sum of all the supervisory bit data and the information bit data. The specific formula is as follows:
S0＝D0+D1+D3+D4+D6+D8+D10+D11+D13+D15+D17+…+P0 (9)
S1＝D0+D2+D3+D5+D6+D9+D10+D12+D13+D16+D17+…+P1 (10)
S2＝D1+D2+D3+D7+D8+D9+D10+D14+D15+D16+D17+…+P2 (11)
S3＝D4+D5+D6+D7+D8+D9+D10+D18+D19+D20+D21+…+P3 (12)
S4＝D11+D12+D13+D14+D15+D16+D17+D18+D19+D20+…+P4 (13)
S5＝D26+D27+D28+D29+D30+D31+D32+D33+D34+D35+…+P5 (14)
S6＝D0+D1+D2+D3+D4+D5+D6+D47+…+P0+P1+…+P6 (15)
step 6) the method for judging whether single event upset occurs according to the value of the syndrome specifically comprises the following steps:
if the values of r syndromes (i.e., the values of 7 syndromes { S6-S0 } are equal to 0), judging that single event upset does not occur;
if the value of r syndromes (i.e., the value of 7 syndromes { S6-S0 } is not all equal to 0), and syndrome S r If the value of (2) is equal to 1, judging that 1bit error occurs, and entering step 7);
if the value of r syndromes (i.e., the value of 7 syndromes { S6-S0 } is not all equal to 0, and S r If the bit is equal to 0, judging that even bit errors occur, and entering the step 8);
7) The reverse checking method determines the occurrence position of the error code, and specifically comprises the following steps:
searching binary codes corresponding to the r syndrome values calculated in the step 6) in the n r-bit binary codes obtained in the step 2), and obtaining corresponding binary codes, wherein information bits or supervision bits corresponding to the same address as the binary codes, namely error code occurrence positions. In the embodiment of the invention, the occurrence position of the error code is determined according to the corresponding relation between the syndrome and the position of the error code in the table 1, and the error is corrected. If S6-S0 equals 1000011, this indicates that the set of data D0 is in error.
8) And setting the count of the double-bit error counter to be increased by 1, and resetting the star service center computer after the count of the double-bit error counter is higher than the safety threshold.
The star service center computer detects the error of m instructions according to the value of the syndrome according to the task period and judges whether single event upset occurs or not; m is determined according to the processing capacity of the processor, and the original task of the processor is not affected. Wherein m is a positive integer.
Table 1 syndrome vs. bit error position table (k=48, r=7)
The method of the invention tests in a comprehensive electronic computer of a small satellite. The data aimed at by fault injection comprises relative program control instructions, program control data blocks, load data and the like of the minisatellite, wherein the program control instruction error correction algorithm selects an extended Hamming code (80,72), the relative program control instruction error correction algorithm selects the extended Hamming code (56, 48), and the program control data blocks select (128,120). After the data is uploaded, the data is generated into 1bit errors and 2bit errors by modifying the memory of the star host. The fault of each data type is randomly injected 100 times, and the method can effectively detect and correct errors. The test results are shown in graph 2.
Table 2 test results
The foregoing is merely one specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present invention should be included in the scope of the present invention.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.
Claims (6)
1. The fault-tolerant method for the important data of the low-cost small satellite is characterized by comprising the following steps of:
1) Determining the bit number r of the instruction data supervisor bits
Performing extended hamming code encoding, wherein k-bit instruction data correspondingly generate r-bit supervision bits, and the data length n=k+r of each group of relative program control instructions after encoding, wherein the information bits of the instruction data comprise: d (D) 1 ～D k The supervision bits include: p (P) 1 ～P r Definition of P r Is a global supervision bit;
2) Distributing the address of the information bit and the address of the supervision bit to obtain n r-bit binary codes
21 A) assigning a jth supervisor bit P j The address of (2) corresponds to 2 j-1 The method comprises the steps of carrying out a first treatment on the surface of the Information bit D i N addresses [1, n ] are allocated in sequence from small to large according to the number i]Addresses not occupied by the monitor bits; obtaining k addresses of information bits and r addresses of supervision bits; i epsilon [1, k]，j∈[1，r]The method comprises the steps of carrying out a first treatment on the surface of the i and j are positive integers;
22 Increasing all n address values by 2 r-1 Converting the binary code into r bits; sequentially numbering j from low order to high order elements in each binary code;
3) Determining the values of r supervision bits according to the binary code; the j-th supervision bit P j The method for determining the value of (a) specifically comprises the following steps:
obtaining exclusive or sum value of information bit data corresponding to binary code with j-th bit element 1 in k binary codesTo supervise bit P j Is a value of (2);
4) Repeating the steps 1) to 3), encoding the plurality of instruction data to obtain encoded instruction data and grouping the encoded instruction data for uploading; each uploading frame comprises a synchronous word, a frame length, a CRC value, a plurality of instruction data and a supervision bit corresponding to each instruction data;
5) The star service center computer receives the uploading frame uploaded in the step 4), and stores and processes a plurality of instruction data in the uploading frame and supervision bits corresponding to each instruction data after judging that the synchronization word, the frame length and the CRC of the uploading frame are correct;
6) Before a star service center computer starts to run each piece of instruction data, calculating the values of r syndromes of the instruction data in real time, and judging whether single event upset occurs according to the values of r syndromes, wherein the method specifically comprises the following steps:
if the values of the r syndromes are equal to 0, judging that single event upset does not occur;
if the value of r syndromes is not equal to 0, syndrome S r If the value of (2) is equal to 1, judging that 1bit error occurs, and entering step 7);
if the value of r syndromes is not equal to 0, syndrome S r If the value of (2) is equal to 0, judging that even bit errors occur;
7) And determining the occurrence position of the error code by inverse checking.
2. The fault tolerance method for low cost small satellite vital data according to claim 1, wherein in step 1) r and k satisfy the following relation:
2 r-1 -1≥k+r-1。
3. the fault tolerance method for low cost small satellite important data according to claim 1, wherein the star service center computer detects the error of m instructions according to the value of the syndrome according to the task period, and judges whether single event upset occurs; m is determined according to the processing capacity of the processor, and the original task of the processor is not affected; wherein m is a positive integer.
4. A low-cost small satellite important data fault-tolerant method according to any one of claims 1 to 3, wherein the calculating method of the r syndrome values in step 6) specifically comprises:
for the j-th syndrome S j The value of (2) is equal to the exclusive or sum value of the supervision bit data and the information bit data corresponding to the binary code with the j-th bit element being 1 in the n binary codes; s is S r For global syndromes, define S r The value of (2) is equal to the exclusive or sum of n all the parity bit data and the information bit data.
5. The fault-tolerant method for low-cost small satellite important data according to claim 4, wherein the method for determining the occurrence position of the error code in step 7) specifically comprises the following steps:
searching binary codes corresponding to the r syndrome values calculated in the step 6) in the n r-bit binary codes obtained in the step 2), and obtaining corresponding binary codes, wherein information bits or supervision bits corresponding to the same address as the binary codes, namely error code occurrence positions.
6. The method for fault tolerance of low cost small satellite important data according to claim 4, wherein after step 6) judges that even number bit error occurs, the method further comprises setting a double bit error counter to count up by 1, and resetting the star service center computer after the double bit error counter counts up by above a safety threshold.
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