CN103279329A - Efficient fetch production line supporting synchronous EDAC inspection - Google Patents
Efficient fetch production line supporting synchronous EDAC inspection Download PDFInfo
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Abstract
The invention discloses an efficient fetch production line supporting synchronous EDAC inspection. The procedure comprises the steps: (1) program address generate (AG), (2) program address send (AS), wherein the AS is used for receiving returned data from a Tag body, conducting hitting judgment, conducting Tag body accompany computation, judging whether errors occur in the Tag body and correcting the first stage errors, the production line is stopped when errors occur in the Tag body information which is received by the AS, the AS corrects the errors, then conducts the hitting judgment and judges whether to read a next stage memorizer or not, (3) program access ready wait (WT), wherein the WT is used for waiting for an instruction packet returned from a data body or the next memorizer, making judgment, conducting data body accompany computation, judging whether errors occur in the data body, correcting the first stage error and writing in the EDAC codes of the Tag body and the data body, and (4) program fetch packet receive (RE). The efficient fetch production line supporting synchronous EDAC inspection has the advantages of being efficient, strong in error correcting capability, little in hardware cost, transparent to a programmer and the like.
Description
Technical field
The present invention is mainly concerned with the design field of processor, refer in particular to a kind of support synchronous EDAC verification efficiently get the finger streamline, the processor that is particularly useful for space field, namely need to the content in the program storage check and the processor proofreaied and correct get the The pipeline design technology that refers to.
Background technology
Along with the mankind to the deepening continuously of space exploration, Space Radiation Effects is constantly aggravated the influence of electronic equipment in the aircraft.Satellite-borne processor (comprising spaceborne CPU and DSP etc.) is the core component of spacecraft electronic equipment, it is carried out radiation hardening acquire a special sense.In satellite-borne processor, instruction Cache(comprises Tag body and data volume) single-particle inversion (the Single Event Upset that caused by space radiation, SEU) will make a certain position of its memory contents be converted into another stable state from a stable state, thereby make a mistake and influence the normal operation of system, thereby generally need carry out error check and correction (Error Detection And Correction, EDAC), adopting Hamming code to detect and correct 1 bit mistake, detect 2 bit mistakes is a kind of the most frequently used ways.In this error correction method, need in storer, additionally increase several accompanying informations.Who or several that accompanying information is used to indicate valid data in the storer make a mistake, and 1 dislocation that produces is corrected.
Getting in the processor refers to that streamline is responsible for instructing the work such as read of generation, instruction bag of packet address, is the maincenter of processor control assembly, get refer to streamline actual be method and the logic of getting finger.How can be a major challenge that the designer faces not influencing the synchronous EDAC verification of basis support of getting finger streamline correctness and high efficiency.Traditional getting of error correction that have refers to that streamline generally adopts the method for multi-mode redundant.This method adopts two covers or extracts the finger logic more, often extracts to refer to whether the instruction bag that logic obtains is identical command reception is finished after, if identical then normally execution; If it is inequality then need error correction even read data again from external memory.Because this method needs to extract the finger logic more, hardware spending is bigger.As shown in Figure 1, refer to the streamline synoptic diagram for getting substantially of no EDAC verification.Substantially get and refer to that streamline is divided into four stacks, be respectively: the program address produces stack (program Address Generate, AG), the program address sends stack (program Address Send, AS), routine access is waited for stack (program access ready Wait, WT) and the program Fetch Packet receive stack (program fetch packet Receive, RE).Wherein the AG stack mainly is responsible for producing the address of current Fetch Packet, and sends read request to the Tag body of one-level instruction Cache.The AS stack mainly receives the data that the Tag body returns and hits judgement, if hit then send read request to data volume; If do not hit then suspend streamline, and single-level memory sends read request downwards.The WT stack is waited for the instruction bag that returns from data volume or next stage storer and is selected.The RE stack carries out boundary alignment and adjustment to the Fetch Packet that receives.
In addition, the Cell unit Irradiation effect Of influence of on-chip memory generally can produce the stable state mistake.This mistake is in case unless error correction is carried out in generation, otherwise very difficult the recovery.And the read/write circuit of on-chip memory mainly is made up of the unlatching logic, and dynamic error takes place easily in the Irradiation effect Of influence, and the beat that this dynamic error takes place is uncertain.If 2 bit mistakes then appear in Cell unit generation stable state mistake in the data that a certain bat is read, and read/write circuit generation dynamic error probably, lead to errors and to recover.The getting of traditional support EDAC refers to that The pipeline design often ignored read/write circuit this phenomenon of dynamic error takes place easily, causes its error correction effect undesirable, the execution efficient step-down of streamline.
Summary of the invention
The technical problem to be solved in the present invention just is: at the technical matters that prior art exists, the invention provides a kind ofly have high efficiency, error correcting capability is strong, hardware spending is little, the programmer is had the transparency the synchronous EDAC verification of support efficiently get the finger streamline.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A kind of support synchronous EDAC verification efficiently get the finger streamline, flow process is:
(1) program address produces stack AG, the address that is used for producing current Fetch Packet, and send read request to the Tag body of one-level instruction Cache;
(2) program address sends stack AS, is used for receiving the data that the Tag body returns and hits judgement, if hit then send read request to data volume; If do not hit then suspend streamline, and single-level memory sends read request downwards; And carry out Tag body syndrome and calculate, judge whether the Tag body exists mistake and 1 bit-errors is corrected; When 1 bit-errors takes place the Tag body information that obtains when the AS stack, need to suspend streamline, it is carried out error correction, hit judgement again, be confirmed to be and read data volume and still read the next stage storer;
(3) routine access is waited for stack WT, is used for waiting for the instruction bag that returns from data volume or next stage storer and selects; And carry out that the data volume syndrome calculates, whether the judgment data body exists mistake, to 1 bit-errors correct, the EDAC coding of Tag body and data volume writes; In case 1 bit-errors takes place, at first suspend streamline, it is carried out error correction, and then carry out subsequent treatment;
(4) the program Fetch Packet receives stack RE, is used for the Fetch Packet that receives is carried out boundary alignment and adjustment.
In above-mentioned streamline, send stack AS and routine access in the program address and wait for that in a single day stack WT finds 2 dislocations, steering logic will read corresponding memory bank again, and when having only continuous two bat access memory banks 2 dislocations all to occur, system just can enter 2 dislocation treatment states.
As a further improvement on the present invention:
Described program address sends the method that stack AS adopts packet transaction, make and judge whether the Tag body exists 1 dislocation logic and judge the Tag body whether carry out synchronously by matching logic, if do not consider 2 dislocations, need whether mate the information of returning with the Tag body according to the Tag position at the AS stack and whether exist 1 dislocation to carry out the processing of following four kinds of situations, wherein exist be designated as a1, do not exist be designated as a2, coupling is designated as b1, not matching is designated as b2:
2.1 for situation a1b1, the Tag that is divided into the road correspondence of coupling does not exist the Tag of the road correspondence of 1 dislocation and coupling to have two kinds of situations of 1 dislocation; For the former, there is not 1 dislocation in the Tag of the road correspondence of coupling, and namely the request of access of current Fetch Packet is hit on a certain road of Tag body, and there is 1 dislocation in the Tag body on other road simultaneously, at first to correct 1 dislocation in the Tag body on other road, and then send the request of read data body; For the latter, there is 1 dislocation in the Tag of the road correspondence of coupling, need carry out error correction earlier, judges again again;
2.2 for situation a2b1, there is not 1 dislocation in the Tag body, and the Tag body mates, and directly sends read request to data volume;
2.3 for situation a1b2, there is 1 dislocation in the Tag body, and the Tag body do not mate, and carries out error correction earlier, judges again again;
2.4 for situation a2b2, do not exist at the Tag body Tag body coupling does not take place under the situation of 1 dislocation, single-level memory sends the read request order downwards.
In described 2.2 situation, Tag position, Fetch Packet address is carried out the EDAC coding and obtained accompanying information, then with Tag position and accompanying information simultaneously and Tag body content and the accompanying information on n road compare, if identical with a certain road then hit this road Cache, can send the request of read data body.
Described routine access waits for that adopting the state machine that comprises five states to control the data of how data volume being returned among the stack WT handles, and the function of each state is as follows:
State ID LE:WT stack is in free time or normal flow water state, and this state calculates the data volume syndrome, judges whether to exist mistake simultaneously;
State ErrorCorrect:WT stack is in the 1 bit-errors state of correction.This state is corrected 1 dislocation of data volume, sends write request to data volume simultaneously;
State ReRead:WT stack is in data volume and reads state again.If there are 2 bit-errors in the data volume that obtains at state ID LE, then system can send the read request order again at state ReRead;
State DataReceive:WT stack has received the data volume content of reading again at this state, can carry out the calculating of body syndrome and judge whether to exist mistake this content;
State Error2bit: all there are 2 bit-errors in the double data volume of reading of this state representation, will carry out special processing to 2 bit-errors according to the configuring condition of system;
Mutual switch condition between the above-mentioned state is as follows:
1. if do not have the Fetch Packet request of access or not have mistake when clapping the data volume that obtains when clapping, then to hold the IDLE state constant for WT stack state organizational security;
2. if there is 1 bit-errors in the data volume that obtains at the IDLE state, then change state ErrorCorrect over to;
3. carry out error correction and send write request in the data volume information of state ErrorCorrect, change state ID LE over to;
4. if there are 2 bit-errors in the data volume that obtains of IDLE state, then change state ReRead over to;
5. after state ReRead sends the order of read data body, change state DataReceive over to;
6. if the data volume data of obtaining at state DataReceive do not have mistake, enter the IDLE state;
7. if there is 1 bit-errors in the data volume data of obtaining at state DataReceive, enter the ErrorCorrect state;
8. if there are 2 bit-errors in the data volume data of obtaining at state DataReceive, enter the Error2bit state.
Described routine access waits for that stack WT and program address send stack AS and all adopted 2 dislocation treatment mechanisms, namely comprises visit Tag body and data volume, and concrete steps are as follows:
6.1 send the read request order to memory bank, change 6.2 over to;
Whether there are 2 dislocations 6.2 judge the data that memory bank returns, if there is no then jump into 6.3, otherwise jump into 6.4;
6.3 current 2 dislocations that do not exist are carried out subsequent treatment;
6.4 send the read request order again to memory bank, change 6.5 over to;
Whether there are 2 dislocations 6.5 judge the data that memory bank returns, if there is no then jump into 6.3, otherwise jump into 6.6;
Exist 6.6 confirm 2 dislocations, carry out 2 dislocation special processings;
6.1 and 6.2 is to send read request to memory bank for the first time in above-mentioned steps, and the data of returning are judged; 6.4 and 6.5 be for the second time to send read request to memory bank, and the data of returning are judged; If all there are 2 dislocations in continuous two bats, system will carry out 2 dislocation special processings.
Compared with prior art, the invention has the advantages that:
1, the present invention has high efficiency.The present invention has adopted packet processing technique and time-delay concealing technology in getting the finger streamline, thereby can send the data volume request of reading earlier, and then can reduce the critical path time-delay of streamline.
2. error correcting capability of the present invention is strong.The present invention has adopted 2 dislocations to read mechanism again, can eliminate the dynamic error in the storer unlatching logic, both can strengthen the error correcting capability of system, can reduce system again from the probability of next stage memory read data.
3, hardware spending of the present invention is little.Owing to do not adopt traditional multi-mode redundant mechanism among the present invention, do not need employing to extract the finger streamline more and work simultaneously, thereby hardware spending be less.In addition, the present invention refers to that logic that the streamline basis increases comprises mainly that syndrome calculates and error correction matrix processing etc. getting substantially, and based on step-by-step and logic and selection logic, hardware spending is little.
4, the present invention has the transparency to the programmer.The synchronous EDAC verification of support that the present invention proposes efficiently get the finger pipelining, adopt pure hardware mechanisms to finish, not needing the programmer to carry out extra configuration can work automatically.
In sum, the present invention refers to the flowing water visit and declares mistake/error correction logic combine by getting, adopt packet processing technique and 2 dislocations to read mechanism again, provide a kind of to the programmer transparent, efficiently, error correcting capability strong, hardware spending is low gets the finger pipelining.The present invention is very suitable for adopting the EDAC technology on-chip command storer to be carried out the processor of radiation hardening.
Description of drawings
Fig. 1 is that getting substantially of no EDAC verification refers to the streamline synoptic diagram.
Fig. 2 is the synoptic diagram of efficiently getting the finger streamline that the present invention supports synchronous EDAC verification.
Fig. 3 is the synoptic diagram that the various what states of AS stack are handled among the present invention.
Fig. 4 is that the AS stack is judged the hit logic synoptic diagram among the present invention.
Fig. 5 is WT stack state machine conversion synoptic diagram among the present invention.
Fig. 6 adopts 2 dislocations to read schematic diagram of mechanism again among the present invention.
Fig. 7 is the processing flow chart of instruction bag read request among the present invention.
Embodiment
Below with reference to Figure of description and specific embodiment the present invention is described in further details.
As shown in Figure 2, be the synoptic diagram of efficiently getting the finger streamline of the synchronous EDAC verification of support of the present invention, efficiently getting among the present invention refers to the actual method for getting finger of streamline.Of the present invention getting refers to that streamline is basic identical with flow process and the logic of getting the finger streamline substantially, also be divided into four stacks, be respectively: the program address produces stack (program Address Generate, AG), the program address sends stack (program Address Send, AS), routine access is waited for stack (program access ready Wait, WT) and the program Fetch Packet receive stack (program fetch packet Receive, RE).Wherein, the AG stack mainly is responsible for producing the address of current Fetch Packet, and sends read request to the Tag body of one-level instruction Cache.The AS stack mainly receives the data that the Tag body returns and hits judgement, if hit then send read request to data volume; If do not hit then suspend streamline, and single-level memory sends read request downwards.The WT stack is waited for the instruction bag that returns from data volume or next stage storer and is selected.The RE stack carries out boundary alignment and adjustment to the Fetch Packet that receives.
The present invention is mainly reflected in AS and WT stack to getting the improvement that refers to streamline substantially.Wherein, having increased Tag body syndrome at the AS stack calculates, judges whether the Tag body exists mistake and 1 bit-errors is corrected logic; Increased at the WT stack that the data volume syndrome calculates, whether the judgment data body exists mistake, 1 bit-errors has been corrected and the EDAC coding of Tag body, data volume writes logic.In a single day find 2 dislocations at AS stack and WT stack, steering logic will read corresponding memory bank again, and when having only continuous two bat access memory banks 2 dislocations all to occur, system just can enter 2 dislocation treatment states.When 1 bit-errors takes place the Tag body information that obtains when the AS stack, need to suspend streamline, it is carried out error correction, hit judgement again, be confirmed to be and read data volume and still read the next stage storer.Mainly adopt state machine that the data volume information of obtaining is judged and error correction at the WT stack, in case 1 bit-errors takes place, at first suspend streamline, it is carried out error correction, and then carry out subsequent treatment.It should be noted that to get substantially to refer to that streamline has only the disappearance read just can suspend flowing water, thereby only can just may produce halt signal at the AS stack.Might need to correct Tag body information or read disappearance at the AS stack among the present invention, might need correction of data body information at the WT stack, thereby all may produce halt signal at AS stack and WT stack.This difference can not influence gets the efficient that the finger streamline is normally carried out (not having disappearance and SEU fault).
As shown in Figure 3, for the present invention when concrete the application, the synoptic diagram that the various what states of AS stack are handled.The main task of AS stack is the Tag body information of obtaining to be carried out syndrome calculate, declare/error correction, and and the Fetch Packet address in the Tag position compare and judge whether to hit.Way can be carried out syndrome calculating to Tag body information earlier and be declared/error correction intuitively, is hitting judgement then, but this way can make the critical path time-delay of streamline increase.The present invention has adopted packet processing technique, makes to judge whether the Tag body exists 1 dislocation logic and judge the Tag body whether carry out synchronously by matching logic, thereby reduces the influence to the critical path time-delay.If do not consider 2 dislocations, need whether mate the information that (coupling is designated as b1, does not match to be designated as b2) and Tag body return according to the Tag position at the AS stack and whether exist 1 dislocation (existence is designated as a1, does not exist to be designated as a2) to carry out the processing of following four kinds of situations.
3.1 for situation a1b1, the Tag that can further be refined as the road correspondence of coupling does not exist the Tag of the road correspondence of 1 dislocation and coupling to have two kinds of situations of 1 dislocation.For the former, there is not 1 dislocation in the Tag of the road correspondence of coupling, and namely the request of access of current Fetch Packet is hit on a certain road of Tag body, and there is 1 dislocation in the Tag body on other road simultaneously.For 1 dislocation in the Tag body that prevents other road is accumulated, at first to correct 1 dislocation in the Tag body on other road, and then send the request of read data body; For the latter, there is 1 dislocation in the Tag of the road correspondence of coupling, and obvious this coupling is false coupling, can not cause final hitting, might there be 1 dislocation in the Tag body on other road simultaneously, might cause hitting after error correction, thereby need carry out error correction earlier in this situation, judge again again.
3.2 for situation a2b1, there is not 1 dislocation in the Tag body, and the Tag body mates, and this means that read request hits to very, can directly send read request to data volume.Because this situation is the critical path of getting when referring to that streamline is normally carried out, the present invention has adopted time-delay more efficiently to hide decision method when concrete realization, sees for details shown in Figure 4.
3.3 for situation a1b2, there is 1 dislocation in the Tag body, and the Tag body do not mate, and this means and might read to hit after error correction, thereby need carry out error correction earlier, judges again again.
3.4 for situation a2b2, do not exist at the Tag body Tag body coupling do not take place under the situation of 1 dislocation, this means that the read request disappearance for true, needs downward single-level memory to send the read request order.
As shown in Figure 4, judge the synoptic diagram of hit logic for AS stack in the concrete application example.It is machine-processed to suppose that one-level instruction Cache adopts n road group to link to each other, and then will receive n road Tag body content and the corresponding accompanying information that returns from the Tag body at the AS stack.Traditional way need generate adjoint matrix (namely carrying out the EDAC decoding) according to accompanying information earlier, and judging does not have 1 dislocation, and then mates with the Tag position of current Fetch Packet address, judges whether to hit.This brings bigger critical path time-delay will for the AS stack, thereby influences the frequency of system.
The present invention is directed to this situation and adopted the time-delay concealing technology, traditional Tag body EDAC decode logic is replaced with the EDAC codimg logic of Tag position, Fetch Packet address.The present invention has kept the accompanying information of Tag body content and correspondence constant, simultaneously Tag position, Fetch Packet address is carried out the EDAC coding and obtains accompanying information.Next, with Tag position and accompanying information simultaneously and Tag body content and the accompanying information on n road compare, if identical with a certain road then hit this road Cache, can send the request of read data body.In said process, the time-delay of Tag position EDAC codimg logic can be hidden in the Tag body and reads in the time-delay in the Fetch Packet address, path delay during the normal flowing water of AS stack with get the time-delay that the path delay that refers to streamline is compared has only increased accompanying information comparison logic substantially, and the figure place of accompanying information is short (when as the employing Hamming code 32 bit data being carried out the EDAC coding, the figure place of accompanying information has only 7), the sequential time-delay expense of its comparison logic is little.
As shown in Figure 5, be the present invention's WT stack state machine conversion synoptic diagram when specifically using.WT stack among the present invention has adopted the state machine that comprises five states to control the data of how data volume being returned and has handled, and the function of each state is as follows:
State ID LE:WT stack is in free time or normal flow water state, and this state calculates the data volume syndrome, judges whether to exist mistake simultaneously.
State ErrorCorrect:WT stack is in the 1 bit-errors state of correction.This state is corrected 1 dislocation of data volume, sends write request to data volume simultaneously.
State ReRead:WT stack is in data volume and reads state again.If there are 2 bit-errors in the data volume that obtains at state ID LE, then system can send the read request order again at state ReRead.
State DataReceive:WT stack has received the data volume content of reading again at this state, can carry out the calculating of body syndrome and judge whether to exist mistake this content.
State Error2bit: all there are 2 bit-errors in the double data volume of reading of this state representation, will carry out special processing to 2 bit-errors according to the configuring condition of system.
Mutual switch condition between the above-mentioned state is as follows:
1. if do not have the Fetch Packet request of access or not have mistake when clapping the data volume that obtains when clapping, then to hold the IDLE state constant for WT stack state organizational security.
2. if there is 1 bit-errors in the data volume that obtains at the IDLE state, then change state ErrorCorrect over to.
3. carry out error correction and send write request in the data volume information of state ErrorCorrect, change state ID LE over to.
4. if there are 2 bit-errors in the data volume that obtains of IDLE state, then change state ReRead over to.
5. after state ReRead sends the order of read data body, change state DataReceive over to.
6. if the data volume data of obtaining at state DataReceive do not have mistake, enter the IDLE state.
7. if there is 1 bit-errors in the data volume data of obtaining at state DataReceive, enter the ErrorCorrect state.
8. if there are 2 bit-errors in the data volume data of obtaining at state DataReceive, enter the Error2bit state.
As shown in Figure 6, for adopting 2 dislocations to read schematic diagram of mechanism again among the present invention.2 dislocation treatment mechanisms (comprising visit Tag body and data volume) have all been adopted at AS stack of the present invention and WT stack, this mechanism is by sending read request to memory bank again, remove the influence of read/write circuit dynamic error in the memory bank, and then can reduce the probability that 2 dislocations take place effectively.Concrete steps are as follows:
6.1 send the read request order to memory bank, change 6.2 over to.
Whether there are 2 dislocations 6.2 judge the data that memory bank returns, if there is no then jump into 6.3, otherwise jump into 6.4.
6.3 current 2 dislocations that do not exist are carried out subsequent treatment.
6.4 send the read request order again to memory bank, change 6.5 over to.
Whether there are 2 dislocations 6.5 judge the data that memory bank returns, if there is no then jump into 6.3, otherwise jump into 6.6.
Exist 6.6 confirm 2 dislocations, carry out 2 dislocation special processings.
6.1 and 6.2 is to send read request to memory bank for the first time in above-mentioned steps, and the data of returning are judged; 6.4 and 6.5 be for the second time to send read request to memory bank, and the data of returning are judged.If all there are 2 dislocations in continuous two bats, system will carry out 2 dislocation special processings.
As shown in Figure 7, wrap the treatment scheme synoptic diagram of read request for instruction among the present invention.For convenience of description, this process flow diagram is illustrated the work for the treatment of unification of different flowing water stacks.An instruction bag read request refers to need to carry out following step in the streamline efficiently the getting of the synchronous EDAC verification of support that the present invention proposes:
7.1 when not instructing the bag read request, whole getting refers to that streamline is in the IDLE state.If a new Fetch Packet read request arrives, then jump into 7.2; Otherwise wait for 7.1.
7.2 send read request to the Tag body, change 7.3 over to.
Whether there are 2 bit-errors 7.3 judge the data of returning from the Tag body.If exist, jump into 7.4; Otherwise jump into 7.5.
7.4 send read request to the Tag body again, jump into 7.6.
Whether there is 1 bit-errors 7.5 judge the data of returning from the Tag body.If exist, then jump into 7.7; Otherwise jump into 7.8.
Whether there are 2 bit-errors 7.6 judge the data of returning from the Tag body.If exist, then jump into 7.9; Otherwise jump into 7.5.
7.7 the data that the Tag body returns are carried out error correction, enter 7.8.
7.8 the data that the Tag position of more current Fetch Packet address and Tag return judge whether the Tag body mates.If coupling is jumped into 7.10, otherwise is jumped into 7.11.
7.9 there are 2 dislocations in the Tag body, carries out 2 dislocation special processings.
7.10 send read request to data volume, jump into 7.15.
7.11 single-level memory sends read request downwards, jumps into 7.12.
Whether returned data 7.12 judge the next stage storer, if return then jump into 7.13, otherwise waited for.
7.13 the data of returning are carried out the EDAC coding and are written to data volume and Tag body, change 7.14 over to.
7.14 return Fetch Packet.
7.15 whether the data that the judgment data body returns exist 2 bit-errors.If exist, then jump into 7.16, otherwise jump into 7.17.
7.16 send read request to data volume, jump into 7.18.
7.17 whether the data that the judgment data body returns exist 1 bit-errors.If exist, then jump into 7.19, otherwise jump into 7.14.
7.18 whether the data that the judgment data body returns exist 2 bit-errors.If exist, then jump into 7.20, otherwise jump into 7.17.
7.19 the mistake to data volume is corrected, and jumps into 7.14.
7.20 there are 2 dislocations in data volume, carries out 2 dislocation special processings.
Below only be preferred implementation of the present invention, protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art the some improvements and modifications not breaking away under the principle of the invention prerequisite should be considered as protection scope of the present invention.
Claims (5)
- One kind support synchronous EDAC verification efficiently get the finger streamline, it is characterized in that flow process is:(1) program address produces stack AG, the address that is used for producing current Fetch Packet, and send read request to the Tag body of one-level instruction Cache;(2) program address sends stack AS, is used for receiving the data that the Tag body returns and hits judgement, if hit then send read request to data volume; If do not hit then suspend streamline, and single-level memory sends read request downwards; And carry out Tag body syndrome and calculate, judge whether the Tag body exists mistake and 1 bit-errors is corrected; When 1 bit-errors takes place the Tag body information that obtains when the AS stack, need to suspend streamline, it is carried out error correction, hit judgement again, be confirmed to be and read data volume and still read the next stage storer;(3) routine access is waited for stack WT, is used for waiting for the instruction bag that returns from data volume or next stage storer and selects; And carry out that the data volume syndrome calculates, whether the judgment data body exists mistake, to 1 bit-errors correct, the EDAC coding of Tag body and data volume writes; In case 1 bit-errors takes place, at first suspend streamline, it is carried out error correction, and then carry out subsequent treatment;(4) the program Fetch Packet receives stack RE, is used for the Fetch Packet that receives is carried out boundary alignment and adjustment;In above-mentioned streamline, send stack AS and routine access in the program address and wait for that in a single day stack WT finds 2 dislocations, steering logic will read corresponding memory bank again, and when having only continuous two bat access memory banks 2 dislocations all to occur, system just can enter 2 dislocation treatment states.
- 2. the synchronous EDAC verification of support according to claim 1 efficiently gets the finger streamline, it is characterized in that, described program address sends the method that stack AS adopts packet transaction, make and judge whether the Tag body exists 1 dislocation logic and judge the Tag body whether carry out synchronously by matching logic, if do not consider 2 dislocations, need whether mate the information of returning with the Tag body according to the Tag position at the AS stack and whether exist 1 dislocation to carry out the processing of following four kinds of situations, wherein exist be designated as a1, do not exist be designated as a2, coupling is designated as b1, not matching is designated as b2:2.1 for situation a1b1, the Tag that is divided into the road correspondence of coupling does not exist the Tag of the road correspondence of 1 dislocation and coupling to have two kinds of situations of 1 dislocation; For the former, there is not 1 dislocation in the Tag of the road correspondence of coupling, and namely the request of access of current Fetch Packet is hit on a certain road of Tag body, and there is 1 dislocation in the Tag body on other road simultaneously, at first to correct 1 dislocation in the Tag body on other road, and then send the request of read data body; For the latter, there is 1 dislocation in the Tag of the road correspondence of coupling, need carry out error correction earlier, judges again again;2.2 for situation a2b1, there is not 1 dislocation in the Tag body, and the Tag body mates, and directly sends read request to data volume;2.3 for situation a1b2, there is 1 dislocation in the Tag body, and the Tag body do not mate, and carries out error correction earlier, judges again again;2.4 for situation a2b2, do not exist at the Tag body Tag body coupling does not take place under the situation of 1 dislocation, single-level memory sends the read request order downwards.
- 3. the synchronous EDAC verification of support according to claim 2 efficiently gets the finger streamline, it is characterized in that, in described 2.2 situation, Tag position, Fetch Packet address is carried out the EDAC coding and obtained accompanying information, Tag body content and accompanying information with Tag position and accompanying information while and n road compares then, if identical with a certain road then hit this road Cache, can send the request of read data body.
- 4. the synchronous EDAC verification of support according to claim 1 efficiently gets the finger streamline, it is characterized in that, described routine access waits for that adopting the state machine that comprises five states to control the data of how data volume being returned among the stack WT handles, and the function of each state is as follows:State ID LE:WT stack is in free time or normal flow water state, and this state calculates the data volume syndrome, judges whether to exist mistake simultaneously;State ErrorCorrect:WT stack is in the 1 bit-errors state of correction; This state is corrected 1 dislocation of data volume, sends write request to data volume simultaneously;State ReRead:WT stack is in data volume and reads state again; If there are 2 bit-errors in the data volume that obtains at state ID LE, then system can send the read request order again at state ReRead;State DataReceive:WT stack has received the data volume content of reading again at this state, can carry out the calculating of body syndrome and judge whether to exist mistake this content;State Error2bit: all there are 2 bit-errors in the double data volume of reading of this state representation, will carry out special processing to 2 bit-errors according to the configuring condition of system;Mutual switch condition between the above-mentioned state is as follows:(1) if. do not have the Fetch Packet request of access or not have mistake when clapping the data volume that obtains when clapping, then to hold the IDLE state constant for WT stack state organizational security;(2) if. there is 1 bit-errors in the data volume that obtains at the IDLE state, then changes state ErrorCorrect over to;(3). carry out error correction and send write request in the data volume information of state ErrorCorrect, change state ID LE over to;(4) if. there are 2 bit-errors in the data volume that the IDLE state obtains, then changes state ReRead over to;(5). after state ReRead sends the order of read data body, change state DataReceive over to;(6) if. the data volume data of obtaining at state DataReceive do not have mistake, enter the IDLE state;(7) if. there is 1 bit-errors in the data volume data of obtaining at state DataReceive, enter the ErrorCorrect state;(8) if. there are 2 bit-errors in the data volume data of obtaining at state DataReceive, enter the Error2bit state.
- 5. efficiently get the finger streamline according to the synchronous EDAC verification of any described support in the claim 1～4, it is characterized in that, described routine access waits for that stack WT and program address send stack AS and all adopted 2 dislocation treatment mechanisms, namely comprises visit Tag body and data volume, and concrete steps are as follows:6.1 send the read request order to memory bank, change 6.2 over to;Whether there are 2 dislocations 6.2 judge the data that memory bank returns, if there is no then jump into 6.3, otherwise jump into 6.4;6.3 current 2 dislocations that do not exist are carried out subsequent treatment;6.4 send the read request order again to memory bank, change 6.5 over to;Whether there are 2 dislocations 6.5 judge the data that memory bank returns, if there is no then jump into 6.3, otherwise jump into 6.6;Exist 6.6 confirm 2 dislocations, carry out 2 dislocation special processings;6.1 and 6.2 is to send read request to memory bank for the first time in above-mentioned steps, and the data of returning are judged; 6.4 and 6.5 be for the second time to send read request to memory bank, and the data of returning are judged; If all there are 2 dislocations in continuous two bats, system will carry out 2 dislocation special processings.
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| CN116991479A (en) * | 2023-09-28 | 2023-11-03 | 中国人民解放军国防科技大学 | Method and device for performing look-ahead execution-bypass error correction on cache tag body of ultra-long instruction word |
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