CN102929743A - First-stage cached data storage method and device with soft error tolerant function - Google Patents
First-stage cached data storage method and device with soft error tolerant function Download PDFInfo
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Abstract
The invention discloses first-stage cached data storage method and device with a soft error tolerant function. The first-stage cached data storage method comprises the following steps of: (1) when a data filling command is received, receiving data to generate an odd-even check code, and carrying out scatter storage by taking data bits as units; and (2) when a data hit command is received, reading data bit combinations to obtain hit data, generating an odd-even check code, comparing the odd-even check code with the stored odd-even check code, if the odd-even check codes are consistent, directly outputting the hit data, and if not, reporting an error message. The first-stage cached data storage device comprises a data storage array, a check array, a decoder, a data writing access and a data reading access, wherein the data storage array contains multiple data items; each data item contains multiple word storage units; each word storage unit contains multiple bit storage modules; each bit storage module contains multiple data bits; and a complete data is formed through the same data bits of the multiple bit storage modules. The first-stage cached data storage method and device disclosed by the invention have the advantages of high soft error tolerant capacity, less hardware overhead and good timing sequence property.
Description
Technical field
The present invention relates to level cache in the microprocessor (one-level cache) design field, be specifically related to a kind of level cache date storage method and device with soft error fault tolerance.
Background technology
Along with the raising of technological level, the characteristic dimension of integrated circuit constantly reduces, and all so that integrated circuit is more and more responsive on the impact of environment, integrity problem becomes increasingly conspicuous for the supply voltage that constantly reduces, the node capacitor that continues to reduce.Particularly under nanoscale technique, the soft error rate of chip sharply increases.
So-called soft error refers to the instantaneous destruction that discharges and recharges the inside circuit state that integrated circuit occurs when being subject to high-energy particle bombardment or noise.Soft error is a kind of transient error, is recoverable, and the time of its generation and position are at random.The probability that soft error occurs is relevant with the source-drain area area with integrated circuit node electric weight.Along with the progress of integrated circuit technology, supply voltage constantly reduces, and the electric charge of storing on the individual node is fewer and feweri, so lower particle or the noise of energy just may cause soft error.But the simultaneously reduction of characteristic dimension also so that the area of responsive source-drain area reduces, causes the probability of single transistor device generation transient fault to reduce.Because characteristic dimension and supply voltage reduce synchronously, so the probability of single transistor device generation soft error will remain unchanged in a lot of years of future.But along with the progress of technique, transistor size integrated on the monolithic is exponential increase, so as a whole, the probability of chip generation soft error also will be exponential increase.There are some researches show that under the nanoscale process conditions, soft error is the main cause that causes chip failure.
In Modern microprocessor, various storage unit (comprising memory bank and register etc. in the sheet) have occupied more than 70% of chip area, are parts the most responsive to high energy particle in the chip.The soft error that storage unit occurs comprises two types of single event upset (it is wrong that upset occurs the storage unit that single high-energy particle bombardment causes) and multidigit upsets (the upset mistake occurs a plurality of consecutive storage units that single high-energy particle bombardment causes).Studies show that the various transient faults that microprocessor occurs, the overwhelming majority comes from storage unit.Therefore present highly reliable microprocessor is protected for various storage unit mostly.
For single event upset, register (Flip-flop) is the same with the probability of memory bank generation in the sheet; But overturn for multidigit, because the on-chip memory circuit realizes that layout is compacter with respect to register, therefore under the live width and the analogous condition of particle size of deep-submicron device, the multidigit that single particle bombardment may cause consecutive storage unit is overturn probability will be far above register.So with respect to other parts of processor, the easier generation soft error of on-chip memory, more need to adopt reinforcement technique to protect, except can protecting single event upset type soft error, the more important thing is also can the protection of effective support multidigit flip type soft error.
The general information redundancy technology that adopts of memory bank appearance soft error design is carried out soft error detection and correction in the sheet, and information redundancy technology commonly used comprises parity code technology and Hamming checking code technology.During these Technology Need write stories data are carried out redundancy encoding, raw data and coding all are stored in the storer, when reading data and check code are carried out verification.For the parity code technology, required redundancy encoding is few, and the area of increase and timing performance expense are little, but have only considered the appearance single event upset, and does not consider to hold the multidigit upset.For the Hamming checking code technology, not only considered the appearance single event upset, also considered the upset of appearance multidigit, but the redundancy encoding that needs is many, causes area change and timing performance expense large.
Level cache (L1 cache) is the bulk storage in the processor piece, in order to improve caching performance, reduces the cache invalidation rate, often is organized into the structure of multichannel set associative.
As shown in Figure 1, the level cache memory storage of prior art is generally the set associative level cache, and the set associative level cache comprises sign array, data array and data redundancy verification array three parts.Sign array and data array have consisted of a typical CAM-RAM structure, sign (tag) is stored in the CAM structure, data (data) are stored in the RAM structure, CAM item and RAM item are one to one, and the sign array of set associative level cache and data array have realized n road set associative structure.Every of the sign array has comprised road 0(way
0) to road n(way
n) the tag information on all roads, and press way
0Sign, way
1Be identified to way
nThe mode of sign is organized.Every of data array has comprised road 0(way
0) to road n(way
n) the data information on all roads, and press way
0Data, way
1Data are to way
nThe mode of data is organized, and every circuit-switched data comprises the i.e. Cache block size of a Cache line(), consisted of by m word (word), each word (word) is 32, every circuit-switched data is pressed word
0, word
1To word
mMode organize.When access group links level cache, come index sign array with low order address (address), the high address will be input in the sign array as a search word, walk abreast with the sign on all n roads in the sign array and compare, and produce the hit/miss signal on every road.Meanwhile low order address also is used for the index data array, read the data on all n roads of index entry, then based on certain circuit-switched data (i.e. Cache line) that the road road selects Information Selection to read of hitting that identifies the generation of array hit/miss (match/dismatch) signal.When filling the set associative level cache, data to be written (i.e. Cache line) will write data in the data volume on the corresponding road of set associative level cache according to filling road road selection information.
The level cache memory storage soft error fault tolerance of prior art is realized by data redundancy verification array.Data redundancy verification array is used for the soft error detection of set associative level cache, and is corresponding one by one with data array.When writing certain circuit-switched data, will generate check code according to data writing simultaneously, and check code be write in the redundancy check array on this road.When reading certain circuit-switched data, correspondingly also read the check code on this road, carry out error-detecting according to sense data and check code.Every of redundancy check array has comprised road 0(way
0) to road n(way
n) information of check code on all roads.Way
0Check code is for detection of way in the data array
0The soft error of data, way
1Check code is for detection of way in the data array
1The soft error of data, the rest may be inferred.The redundancy check mechanism of every circuit-switched data can adopt the complicated verification schemes (ECC) such as Hamming code in the level cache memory storage of prior art, also can adopt simple odd-even check mechanism (P).It is strong that the ECC verification scheme is held the soft error ability, but the single event upset of detection of stored body is wrong and the multidigit upset is wrong, but hardware realizes that expense is large.P verification scheme hardware realizes that expense is little, the single event upset of energy detection of stored body is wrong, when the adjacent cells multidigit upset that the single-particle initiation occurs is staggered the time, because adjacent cells multidigit mistake can occur on the different pieces of information position of the data volume of going the same way under the level cache set of storage devices associative structure of prior art, therefore the multidigit upset that the P verification scheme can't the detection of stored body occurs under this structure is wrong, hold the soft error ability relatively a little less than.
Summary of the invention
The technical problem to be solved in the present invention is to realize the high fault-tolerant ability of memory bank soft error under low hardware spending.The invention provides a kind of level cache date storage method and device with soft error fault tolerance that the soft error ability is strong, hardware spending is little, timing performance is good that hold.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is:
A kind of level cache date storage method with soft error fault tolerance, implementation step is as follows:
1) when receiving the data stuffing order, receive data to be filled and adopt odd-even check information redundancy coding to generate parity check code and storage parity code, described data to be filled are disperseed take data bit as unit respectively to be stored in the data storage array simultaneously;
2) when receiving the data hit order, from data storage array, read each data bit of disperseing storage, each data bit combination is obtained hitting circuit-switched data, to hit circuit-switched data adopts odd-even check information redundancy coding to generate parity check code, the parity check code that generates parity check code and storage is compared, if both unanimously then directly will hit circuit-switched data output, otherwise detect error in data, the report error message.
The further improvement that has the level cache date storage method of soft error fault tolerance as the present invention:
When in the described step 1) data being disperseed take data bit as unit to be stored in the data storage array respectively, and the identical data position of different circuit-switched data is stored in the same storage area in the data storage array.
The present invention also provides a kind of level cache data storage device with soft error fault tolerance, comprise that data storage array, verification array, demoder, data write path and data read path, described data storage array comprises a plurality of data item, any one described data item comprises a plurality of element word storages that are arranged in order, described element word storage comprises a plurality of memory modules that are arranged in order, institute's rheme memory module comprises the identical data position on all roads, a circuit-switched data of the data complete of the identical data position storage in all memory modules; Described verification array comprise with data storage array in every circuit-switched data parity checking item one to one, each parity checking storage unit is stored respectively the parity check code of corresponding data Xiang Zhongyi circuit-switched data in the described parity checking item; When receiving the data stuffing order, described verification array received data to be filled also adopt odd-even check information redundancy coding to generate parity check code and storage parity code, and the while data are write path and data to be filled disperseed take data bit as unit respectively be stored in each memory module of data storage array; When receiving the data hit order, described demoder according to data hit order obtain the data bit in each memory module in the data storage array, described data read path reads each data bit of dispersion storage and each data bit combination is obtained hitting circuit-switched data from described each memory module, to hit circuit-switched data adopts odd-even check information redundancy coding to generate parity check code, the parity check code that generates parity check code and storage is compared, if both unanimously then directly will hit circuit-switched data output, otherwise detect error in data, the report error message.
The further improvement that has the level cache data storage device of soft error fault tolerance as the present invention:
Described data are write path and are comprised and institute rheme memory module a plurality of MUX of writing one to one, and the described MUX of writing links to each other with corresponding position memory module; Described data read path comprises and institute rheme memory module a plurality of MUX of reading one to one, and the described MUX of reading links to each other with corresponding position memory module.
The level cache storage means that the present invention has the soft error fault tolerance has following advantage:
1, appearance soft error ability is strong.The present invention adopts simple odd-even check information redundancy coding that one-level cache memory bank is held the soft error protection; than complicated checking information redundancy encodings such as hamming ECC; the area that one-level cache memory bank is increased still less, less memory bank area can reduce memory bank soft error incidence.Simultaneously the present invention disperses one-level cache data respectively to be stored in the data storage array take data bit as unit, when reading, each data bit combination is obtained hitting circuit-switched data, the dispersion of data storage has guaranteed that the adjacent multi-bit memory cell mistake that the single-particle bombardment causes occurs over just in the data volume of not going the same way, and is different from the wrong situation that occurs in the data volume different pieces of information position of going the same way of multidigit upset under the level cache storage sets associative structure of prior art; Level cache storage for prior art, the multidigit that occurs in the data volume different pieces of information position of going the same way is wrong, odd-even check mechanism can't detect, but dispersion tissue's mode of intersecting by the memory bank road can be distributed to memory bank multidigit mistake on the data volume of not going the same way, every circuit-switched data body only comprises 1 bit-errors, at this moment can detect by the timesharing of odd-even check mechanism the unit mistake of every circuit-switched data body, thereby effectively solve the wrong problem of memory bank multidigit, improve the ability that memory bank holds soft error.
2, hardware spending is little.What the present invention adopted is the odd-even check information redundancy coding of hardware area expense minimum, this coding only needs that each basic verification unit is increased by 1 bit check code can finish verifying function, and the verification code bit that hamming ECC coding needs is far longer than parity code, for example 1 word of 1 basic verification unit (32) for buffer memory will need 7 bit check codes can finish verifying function, more complicated check code such as Reed-Solomon coding will need more check bit, this brings huge area overhead can for large capacity level cache memory bank, the present invention is than complicated checking information redundancy encodings such as hamming ECC, the area that the level cache memory bank is increased still less, so the present invention has the little advantage of hardware spending.
3, timing performance is good.The read-write path of level cache often is positioned on the critical path of chip memory access in the microprocessor, therefore the quality that is positioned at the redundancy encoding coding-decoding circuit sequential on the memory bank read-write path will directly affect the performance of processor, the performance of coding-decoding circuit depends on code decode algorithm and check figure place (comprising data bit and verification code bit) usually, and complicated redundancy encoding will need complicated coding-decoding circuit.And the present invention adopts the odd-even check redundancy encoding, and its code decode algorithm is simple and check figure place relatively still less, so that the timing performance of coding-decoding circuit is relatively better, processor performance is relatively better; Simultaneously Organization of Data form of the present invention can effectively be avoided the data line length and the line cross-cutting issue that cause under the level cache storage sets associative structure of prior art, data reading under the level cache storage sets associative structure of prior art with write the long line of fashionable intersection and become local short-term, can eliminate long line, the improvement of assurance memory bank read-write sequence, the lifting of performance from structure.
The present invention has the level cache memory storage of soft error fault tolerance owing to have the structure corresponding with the level cache storage means with soft error fault tolerance, therefore also have the technique effect identical with aforementioned level cache storage means with soft error fault tolerance, do not repeat them here.
Description of drawings
Fig. 1 is the framed structure synoptic diagram of prior art level cache memory storage.
Fig. 2 is the basic procedure synoptic diagram of embodiment of the invention storage means.
Fig. 3 is the framed structure synoptic diagram of embodiment of the invention memory storage.
Fig. 4 is the framed structure synoptic diagram that data are write path and data read path in the embodiment of the invention memory storage.
Marginal data: 1, data storage array; 11, element word storage; 12, position memory module; 2, verification array; 21, parity checking storage unit; 3, demoder; 4, data are write path; 41, write MUX; 5, data read path; 51, read MUX.
Embodiment
As shown in Figure 2, to have the implementation step of level cache date storage method of soft error fault tolerance as follows for present embodiment:
1) when receiving the data stuffing order, receive data to be filled and adopt odd-even check information redundancy coding to generate parity check code and storage parity code, data to be filled are disperseed take data bit as unit respectively to be stored in the data storage array simultaneously;
2) when receiving the data hit order, from data storage array, read each data bit of disperseing storage, each data bit combination is obtained hitting circuit-switched data, to hit circuit-switched data adopts odd-even check information redundancy coding to generate parity check code, the parity check code that generates parity check code and storage is compared, if both unanimously then directly will hit circuit-switched data output, otherwise detect error in data, the report error message.
In the present embodiment, in the step 1) data are disperseed take data bit as unit respectively to be stored in the data storage array, and the identical data position of different circuit-switched data is stored in the same storage area in the data storage array, and from left to right Organization of Data form is as follows in the data storage array: the 0th of the 0th word of the 0th circuit-switched data, the 0th of the 0th word of the 1st circuit-switched data ..., the n circuit-switched data the 0th of the 0th word; The 0th of the 1st word of the 0th circuit-switched data, the 0th of the 1st word of the 1st circuit-switched data ..., the n circuit-switched data the 0th bit organization of the 1st word; The 0th of m word of the 0th circuit-switched data, the 0th of m word of the 1st circuit-switched data ..., the n circuit-switched data the 0th bit organization of m word; Wherein n is the way of data, and m is the number of words in each circuit-switched data.The Organization of Data form has consisted of the mode that the road intersects in the data storage array of present embodiment, identical data position physical centralization with each circuit-switched data, the problem that can effectively avoid the data line length that causes under the level cache set of storage devices associative structure of prior art and line to intersect, can become local short-term reading and write the long line of fashionable intersection, the elimination of the long line of intersection will certainly guarantee the improvement of memory bank read-write sequence, the lifting of performance.
Every circuit-switched data of present embodiment adopts the soft error of parity redundancy code detection memory bank, checksum coding only needs 1 information redundancy check code, hardware realizes that expense is little, and the area of increase is few, effectively the single event upset soft error of detection of stored body generation.Wrong for the consecutive storage unit multidigit upset that single-particle causes, dispersion tissue's mode by memory bank road intersection, so that the adjacent cells multidigit mistake that causes be not distributed on the different pieces of information position of the data volume of going the same way, but be distributed on the data volume of not going the same way, therefore can detect by the parity check code timesharing unit mistake of every circuit-switched data body, finally solve the wrong problem of memory bank multidigit.Parity check code only can detect the single event upset soft error under the level cache storage sets associative structure compared to existing technology, level cache date storage method with soft error fault tolerance can not only be processed memory bank single event upset soft error, also can process memory bank multidigit upset soft error, strengthen the ability of memory bank appearance soft error.
As shown in Figure 3 and Figure 4, the level cache data storage device that present embodiment has a soft error fault tolerance comprises that data storage array 1, verification array 2, demoder 3, data write path 4 and data read path 5, data storage array 1 comprises a plurality of data item, any one data item comprises a plurality of element word storages 11 that are arranged in order, element word storage 11 comprises a plurality of the memory modules 12 that are arranged in order, position memory module 12 comprises the identical data position on all roads, a circuit-switched data of the data complete of the identical data position storage in all memory modules 12; Verification array 2 comprise with data storage array 1 in every circuit-switched data parity checking item one to one, each parity checking storage unit 21 is stored respectively the parity check code of corresponding data Xiang Zhongyi circuit-switched data in the parity checking item; When receiving the data stuffing order, verification array 2 receives data to be filled and adopts odd-even check information redundancy coding to generate parity check code and storage parity code, and the while data are write path 4 and data to be filled disperseed take data bit as unit respectively be stored in each memory module 12 of data storage array 1; When receiving the data hit order, demoder 3 according to data hit order obtain the data bit in each memory module 12 in the data storage array 1, data read path 5 reads each data bit of dispersion storage and each data bit combination is obtained hitting circuit-switched data from each memory module 12, to hit circuit-switched data adopts odd-even check information redundancy coding to generate parity check code, the parity check code that generates parity check code and storage is compared, if both unanimously then directly will hit circuit-switched data output, otherwise detect error in data, the report error message.
In the present embodiment, each data item of data storage array 1 has comprised road 0(way
0) to road n(way
n) data message on all roads, but different from the level cache set of storage devices associative structure of prior art is, Organization of Data in each data item has been broken the Method of Data Organization under the level cache set of storage devices associative structure of prior art, the dispersion tissue's structure that has adopted the memory bank road to intersect, namely from left to right Organization of Data form is as follows in the data storage array 1: the 0th (way of the 0th word of the 0th circuit-switched data
000), the 0th (way of the 0th word of the 1st circuit-switched data
100) ..., the n circuit-switched data the 0th (way of the 0th word
N00); The 0th (way of the 1st word of the 0th circuit-switched data
010), the 0th (way of the 1st word of the 1st circuit-switched data
110) ..., the n circuit-switched data the 0th bit organization (way of the 1st word
N10); The 0th (way of m word of the 0th circuit-switched data
0m0), the 0th (way of m word of the 1st circuit-switched data
1m0) ..., the n circuit-switched data the 0th bit organization (way of m word
Nm0).Wherein n is the way of data, and m is the number of words in each circuit-switched data.In the present embodiment data in the data storage array have been consisted of the mode of road intersection, concentrate on the same a data physical distribution on all roads under the decussate texture of road, the problem that the distribution of concentrating can effectively avoid the data line length that causes under the level cache set of storage devices associative structure of prior art and line to intersect, become local short-term reading and write the long line of fashionable intersection, the elimination of the long line of intersection will certainly guarantee the improvement of memory bank read-write sequence, the lifting of performance.
In the present embodiment, verification array 2 comprise with data storage array 1 in every circuit-switched data parity checking item one to one, adopt the little parity checking mechanism of hardware spending to generate identifying code, it is wrong that every circuit-switched data only needs 1 bit check code can detect every circuit-switched data unit.Cause the consecutive storage unit multidigit problem that parity checking mechanism can't detect of staggering the time for single-particle under the level cache set of storage devices associative structure of prior art, present embodiment can be avoided effectively by the data storage array 1 of road decussate texture.Wrong for the consecutive storage unit multidigit that single-particle causes, under the structure of the data storage array 1 that intersects on the road, its mistake be not distributed on the different pieces of information position of the data volume of going the same way, but is distributed on the data volume of not going the same way, and the data mistake of not going the same way can detect by the parity checking of not going the same way.For example in the data storage array 1 of present embodiment, way
000, way
100The consecutive storage unit multidigit upset mistake that single-particle causes has occured, when data access arrives way
0The time, can detect the way that is caused by the multidigit upset by parity checking
000Mistake is when data access arrives way
1The time, can detect the way that is caused by the multidigit upset by parity checking
100Mistake.Present embodiment has solved the soft error of multidigit upset by the wrong problem of this time-division processing unit with parity checking mechanism, has guaranteed the high fault-tolerant ability of soft error under the low hardware spending.
As shown in Figure 4, data are write path 4 and are comprised and position memory module 12 a plurality of MUX 41 of writing one to one, write MUX 41 and link to each other with corresponding position memory module 12; Data read path 5 comprises and position memory module 12 a plurality of MUX 51 of reading one to one, reads MUX 51 and links to each other with corresponding position memory module 12.Road road selection signal controlling is selected and filled to the data of reading or writing by hitting the road road in the data bit that reaches every circuit-switched data correspondence in each memory module 12.Under the level cache set of storage devices associative structure of prior art, relatively disperse on the same a data physical distribution on all roads, cause reading or data writing in each all need a large MUX to finish to read and write data and the data interaction of memory bank, large multichannel is selected to produce a large amount of long lines of intersection, has increased the difficulty of level cache memory bank timing Design; And under the level cache set associative structure of present embodiment road intersection, concentrate on the same a data physical distribution on all roads, read or data writing in each only need a little MUX (write MUX 41 or read MUX 51) to finish to read and write data and the data interaction of memory bank, such as a plurality of little MUX mux that shows among the figure
00(mux
00The 0th of the 0th word who represents all roads), mux
01(mux
01The 1st of the 0th word who represents all roads) ..., mux
Mn(mux
MnThe n position that represents m the word on all roads), the a data of of having realized by the little MUX of writing MUX 41 or reading MUX 51 reading and writing data of present embodiment and memory bank mutual, eliminated the problem of the long line of intersection, the long line that will intersect becomes local short-term, thereby the raising of optimization of orderings and performance can be offered help for the performance optimization of microprocessor when being conducive to the level cache read/write circuit of sequential anxiety.
Present embodiment has been successfully applied among the high-performance microprocessor chip FT1000 and the follow-up family chip of soaring that computing machine institute of the National University of Defense technology designs and Implements.FT1000 and the follow-up family chip of soaring have all comprised jumbo level cache memory bank (L1 Cache), in order to guarantee the high reliability of chip, level cache memory bank (L1 Cache) has adopted present embodiment to have the level cache memory storage of soft error fault tolerance in the sheet, through FT1000 and the follow-up family chip prototype test of soaring, this invention can correctly be carried out in FT1000 and the follow-up family chip processor of soaring effectively, it is little to have the design cost, hold the strong advantage of soft error ability, can effectively detect single event upset and the multidigit upset soft error of level cache memory bank.
The above only is preferred implementation of the present invention, and protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art in the some improvements and modifications that do not break away under the principle of the invention prerequisite, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. level cache date storage method with soft error fault tolerance is characterized in that implementation step is as follows:
1) when receiving the data stuffing order, receive data to be filled and adopt odd-even check information redundancy coding to generate parity check code and storage parity code, described data to be filled are disperseed take data bit as unit respectively to be stored in the data storage array simultaneously;
2) when receiving the data hit order, from data storage array, read each data bit of disperseing storage, each data bit combination is obtained hitting circuit-switched data, to hit circuit-switched data adopts odd-even check information redundancy coding to generate parity check code, the parity check code that generates parity check code and storage is compared, if both unanimously then directly will hit circuit-switched data output, otherwise detect error in data, the report error message.
2. the level cache date storage method with soft error fault tolerance according to claim 1, it is characterized in that: when in the described step 1) data being disperseed take data bit as unit to be stored in the data storage array respectively, and the identical data position of different circuit-switched data is stored in the same storage area in the data storage array.
3. level cache data storage device with soft error fault tolerance, comprise data storage array (1), verification array (2), demoder (3), data are write path (4) and data read path (5), it is characterized in that: described data storage array (1) comprises a plurality of data item, any one described data item comprises a plurality of element word storages (11) that are arranged in order, described element word storage (11) comprises a plurality of the memory modules (12) that are arranged in order, institute's rheme memory module (12) comprises the identical data position on all roads, a circuit-switched data of the data complete of the identical data position storage in all memory modules (12); Described verification array (2) comprise with data storage array (1) in every circuit-switched data item parity checking item one to one, each parity checking storage unit (21) is stored respectively the parity check code of corresponding data Xiang Zhongyi circuit-switched data in the described parity checking item; When receiving the data stuffing order, described verification array (2) receives data to be filled and adopts odd-even check information redundancy coding to generate parity check code and storage parity code, and the while data are write path (4) and data to be filled disperseed take data bit as unit respectively be stored in each memory module (12) of data storage array (1); When receiving the data hit order, described demoder (3) according to data hit order obtain the data bit in each memory module (12) in the data storage array (1), described data read path (5) reads each data bit of dispersion storage and each data bit combination is obtained hitting circuit-switched data from described each memory module (12), to hit circuit-switched data adopts odd-even check information redundancy coding to generate parity check code, the parity check code that generates parity check code and storage is compared, if both unanimously then directly will hit circuit-switched data output, otherwise detect error in data, the report error message.
4. described level cache data storage device with soft error fault tolerance according to claim 3, it is characterized in that: described data are write path (4) and are comprised and institute's rheme memory module (12) a plurality of MUX (41) of writing one to one, and the described MUX (41) of writing links to each other with corresponding position memory module (12); Described data read path (5) comprises and institute's rheme memory module (12) a plurality of MUX (51) of reading one to one, and the described MUX (51) of reading links to each other with corresponding position memory module (12).
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103645964A (en) * | 2013-11-22 | 2014-03-19 | 中国电子科技集团公司第三十二研究所 | Cache fault tolerance mechanism for embedded processor |
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