CN220064808U - System on chip and car - Google Patents

Abstract

The embodiment of the utility model provides a system-on-chip and an automobile, wherein the system-on-chip comprises: a bus; a main kernel connected to the bus; a memory connected to the bus; the first ECC module is connected with the bus or integrated in the memory, and is configured to detect and correct data when the memory interacts with the main kernel. By the mode, the accuracy of data interaction can be improved, and therefore the safety of an automobile is improved.

Description

System on chip and car

Technical Field

The utility model relates to the technical field of automobile safety, in particular to a system on a chip and an automobile.

Background

The rapid development of electronic technology integration and the large amount of application thereof on automobiles greatly promote the development of automobile industry, and the safety problem brought by automobile electronic and electric products is more important when the dependence degree of automobiles on the electronic technology is higher and higher.

In recent years, automobiles are continuously enhancing safety measures, and general-purpose automobile safety MCUs (micro processing units) are required to conform to the ISO26262 (ASIL-D) standard. In order to improve the safety of an automobile, the safety of data is particularly important when the MCU is used for data interaction with other components or other components, and once the data is wrong, the error of an automobile control instruction can be caused, so that safety accidents occur.

Disclosure of Invention

The embodiment of the utility model discloses a system on a chip and an automobile, which are used for solving the problem of automobile safety accidents caused by data interaction errors in the related technology.

To solve the above problems, the present utility model provides a system on a chip, comprising: a bus; a main kernel connected to the bus; a memory connected to the bus; the first ECC module is connected with the bus or integrated in the memory, and is configured to detect and correct data when the memory interacts with the main kernel.

In an embodiment, the system on a chip further comprises a second ECC module, the second ECC module being connected to the bus or integrated with the main core, the second ECC module being configured to perform detection and correction of data when the memory interacts with the main core.

In an embodiment, the system on a chip further includes a third ECC module, the third ECC module being integrated with the bus, the third ECC module being configured to detect and correct data when the memory interacts with the primary core or the primary core interacts with the outside.

In one embodiment, the memory includes at least one of random access memory, read only memory, and flash memory.

In an embodiment, the system on a chip further includes a WDT module, the WDT module being connected to the master core, the WDT module being configured to receive the watchdog signal from the master core and to send a reset signal to the master core to reset the master core when the watchdog signal is not received within a set time.

In an embodiment, the system on a chip further comprises: checking the kernel, and checking the kernel and the master kernel to run in a lockstep manner; and the checking module is connected with the main kernel and the checking kernel and is configured to monitor the running deviation of the main kernel and the checking kernel.

In an embodiment, a Cache module is integrated in the main kernel, and the Cache module is configured to perform instruction Cache or data Cache, and perform read, modify and write operations on cached instructions or data, where the read, modify and write operations are based on an ECC protection mechanism.

In an embodiment, a TCM module is integrated in the main kernel, and the TCM module is configured to perform access writing, and perform reading, modifying and writing operations on data accessed and written, where the reading, modifying and writing operations are based on an ECC protection mechanism.

In an embodiment, a first MPU module and a second MPU module are integrated in the main kernel, the first MPU module configured to be accessed by the EL1 register and the second MPU module configured to be accessed by the EL2 register.

To solve the above problems, the present utility model provides an automobile comprising the above system-on-chip.

The beneficial effects of the utility model are as follows: the present utility model provides a system on a chip comprising: a bus; a main kernel connected to the bus; a memory connected to the bus; the first ECC module is connected with the bus or integrated in the memory, and is configured to detect and correct data when the memory interacts with the main kernel. Through the mode, the first ECC module is added to the memory, the data can be ECC protected in the process of reading and writing the memory, the data accuracy and the safety of the data interaction between the memory and the outside are ensured, and the form safety of the automobile can be further improved when the system on chip is applied to the automobile.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a first embodiment of a system-on-chip provided by the present utility model;

FIG. 2 is a flow chart of an embodiment of a data protection method according to the present utility model;

FIG. 3 is a schematic diagram of a second embodiment of a system-on-chip provided by the present utility model;

FIG. 4 is a schematic diagram of a third embodiment of a system-on-chip provided by the present utility model;

FIG. 5 is a schematic diagram of a fourth embodiment of a system-on-chip provided by the present utility model;

FIG. 6 is a schematic diagram of a fifth embodiment of a system-on-chip provided by the present utility model;

FIG. 7 is a schematic diagram of a sixth embodiment of a system-on-chip provided by the present utility model;

fig. 8 is a schematic structural view of an embodiment of an automobile provided by the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.

In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

The use of "adapted" or "configured" in this disclosure is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

In the present utility model, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the utility model. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present utility model may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the utility model with unnecessary detail. Thus, the present utility model is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of a system on a chip provided by the present utility model, where the system on a chip 100 includes a bus 10, a master core 20 and a memory 30, where the master core 20 is connected to the bus 10, and the memory 30 is connected to the bus 10.

Further, the system on chip 100 further includes a first ECC module 301, where the first ECC module 301 is connected to the bus 10 or integrated with the memory 30, and the first ECC module 301 is configured to perform data detection and correction when the memory 30 performs data interaction with the main core 20.

Among them, system-on-a-chip (SoC) refers to a technology of integrating a complete System on a single chip and grouping all or part of necessary electronic circuits into packets. So-called complete systems typically include a Central Processing Unit (CPU), memory, peripheral circuits, and the like. In this embodiment, the master core 20 may be regarded as a core in one Chip (CPU).

Alternatively, the memory 30 may be a read-only memory (ROM), a random-access memory (RAM), or a Flash memory (Flash), which is not limited in this embodiment. It will be appreciated that the number and variety of the memories 30 may be adjusted according to the actual application environment or functional requirements of the system on chip 100, for example, a plurality of memories may be provided, each for storing one type of data. For an automobile, such data may include sensor data, engine data, battery data, travel data, user operation data, and the like.

Alternatively, bus 10 may be an AXI bus. With the increase in SoC design complexity and the increase in CPU processing power, the bus architecture may become a bottleneck for system performance. In a multiprocessor SoC design, the AXI bus, especially the 3.0AXI bus, is an ideal choice in the SoC design considering cost, power consumption and area comprehensively, and of course, the present embodiment is not limited to the choice of the overall selection protocol.

Wherein the first ECC module 301 may be implemented based on the bus 10 or the resources of the memory 30, in an embodiment, the first ECC module 301 is implemented based on a region of the memory 30.

Referring to fig. 2, fig. 2 is a flow chart of an embodiment of a data protection method according to the present utility model, where the method includes:

step 21: when the memory performs writing operation, first check data of the target data are calculated based on the ECC protection mechanism, and the target data and the first check data are stored.

The target data may be data written by the core 20 or data written by another module.

Step 22: when the target data is read, second check data of the target data is calculated based on the ECC protection mechanism.

Step 23: and reading the target data in response to the first check data and the second check data being identical.

Specifically, the ECC (Error Checking and Correcting, error checking and correction) requires additional space to store the check code, as with the parity technique, but the number of bits it occupies is not linear with the length of the data. Specifically, it uses 8-bit data and 5-bit ECC code as reference, then only one bit of ECC code is added for every 8-bit data. In popular terms, an ECC code generated from 8-bit data occupies 5-bit space, and a 16-bit data ECC code needs to be added with one more bit, that is, 6 bits, based on the original data; and 32-bit data can be obtained by adding one bit of ECC code, namely 7 bits, on the original basis, and the like.

The ECC codes encode 8 bits of information, and in this way 1bit errors can be recovered. Each time data (target data) is written into the memory, the ECC code uses a special algorithm to calculate the data, the result of which is called check bits. The sum of all check bits added together is then the "checksum" (checksum) as the first check data, which is stored with the target data. When these target data are read out from the memory, the checksum is calculated again as second check data using the same algorithm and compared with the calculation result of the previous first check data, and if the result is the same, it is indicated that the data are correct.

Further, on the basis of the step 23, determining the number of error bits of the target data in response to the first check data and the second check data being different; responding to the target data as single bit errors, and correcting the error of the target data; or responding to the target data as the double-bit error, and reporting the error of the target data.

Specifically, when the first check data and the second check data are different, indicating that there is an error, the ECC may logically separate the error and notify the system. When only a single bit error occurs, the ECC can correct the error without affecting the system operation. In addition to being able to detect and correct single bit errors, ECC codes can also detect (but not correct) any 2 random errors that occur on a single DRAM chip, and can detect up to 4bit errors. When a multi-bit error occurs, the ECC memory generates an unhidden (non-maskable interrupt) interrupt (NMI) that suspends system operation to avoid corruption of data.

It is apparent that the length of the ECC code is a logarithmic relationship with the length of the data, and when the data length is more than 64 bits, the ECC code is advantageous in terms of space occupation. Furthermore, the greatest advantage of ECC checking is that if there is a single bit error in the data, it can be found and corrected, and the ECC checking can also find 2-4 bits (uncorrectable), although the probability of such a situation being very low. However, the checking algorithm of the ECC code is more complicated than parity check, and a special chip is needed for supporting the checking algorithm. Moreover, since the system needs time to wait for the result of the verification, the ECC verification can reduce the system speed by about 2% -3%, but this is very costly to greatly improve the system stability.

Further, for the memory 30, in addition to the above-mentioned ECC protection, when the first ECC module 301 determines that there is a read-write error, corresponding protection measures may be performed in terms of both hardware and software. Specifically, specific protection measures are different for different types of the memory 30, and the following table is specifically referred to:

the system on a chip provided in this embodiment includes: a bus; a main kernel connected to the bus; a memory connected to the bus; the first ECC module is connected with the bus or integrated in the memory and is configured to detect and correct data when the memory and the main kernel interact with each other. Through the mode, the first ECC module is added to the memory, the data can be ECC protected in the process of reading and writing the memory, the data accuracy and the safety of the data interaction between the memory and the outside are ensured, and the form safety of the automobile can be further improved when the system on chip is applied to the automobile.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a second embodiment of a system on a chip provided by the present utility model, where the system on a chip 100 includes a bus 10, a master core 20 and a memory 30, and the master core 20 is connected to the bus 10, and the memory 30 is connected to the bus 10.

Further, the system on chip 100 further comprises a first ECC module 301, a second ECC module 201 and a third ECC module 101. The first ECC module 301 is connected to the bus 10 or integrated with the memory 30, and the first ECC module 301 is configured to perform data detection and correction when the memory 30 performs data interaction with the main core 20. The second ECC module 201 is connected to the bus 10 or integrated with the main core 20, and the second ECC module 201 is configured to perform detection and correction of data when the memory 30 performs data interaction with the main core 20. The third ECC module 101 is integrated with the bus 10, and the third ECC module 101 is configured to perform detection and correction of data when the memory 30 and the main core 20 interact with each other or when the main core 20 interacts with the outside.

It will be appreciated that the data protection of the second ECC module 201 for the master core 20 and the data protection of the third ECC module 101 for the bus 10 are similar to the first ECC module 301 in the first embodiment, and will not be described in detail herein.

Alternatively, the ECC protection in this embodiment is E2E-ECC (end-to-end ECC) protection. Specifically, the ECC module is implemented on data, address signals, and stored in memory along with the data through a write operation. When a read operation is initiated, the ECC module recalculates the retrieved data and the requested address and verifies the data with the stored ECC check code. The mechanism is as follows:

1) Data from the master is encoded by ECCSECDED code. The data encoding includes addressing information coverage.

2) The various modules of the path include local mechanisms such as ensuring proper transmission of control data and proper address decoding.

The method can ensure that no data is damaged on the data path. E2E-ECC protection exists in each system of the kernel, E2E-ECC protection exists between the kernel and the bus, E2E-ECC protection exists between data interaction between the bus and the memory, E2E-ECC protection exists between data interaction between the kernel and the outside, and accuracy of data interaction between the systems is fully guaranteed. Whenever a correctable (single bit) or uncorrectable (multi bit) error occurs, the system receives an error signal and then records the error address, sets the corresponding error flag and reports.

Furthermore, the bus in this embodiment also adopts an E2E-ECC protection mechanism, and data interaction between the kernel and the memory in the system is performed by using an AXI bus, and the purpose of bus protection is to correct errors and transmit the errors through the bus when detecting that a signal is wrong, and to protect the errors by using an E2E-ECC method.

Optionally, when the bus is protected, besides the above E2E-ECC protection, a hardware or software manner may be adopted, which specifically includes:

hardware processing:

1. when address and data errors on the bus interface occur, the ECC-SECDED performs error correction and detection.

2. Control and response signals on the bus interface, ECC-DEC error detection.

3. Handshake signals, parity, on the bus interface.

4. Timeout protection for Master bus interfaces.

5. The bus configuration register performs ECC protection and access protection.

And (3) software processing: resetting and reporting.

Further, in this embodiment, a corresponding ECC module may be added between the system on chip 100 and the external system, so as to ensure accuracy and security of data interaction between the system on chip 100 and the external system.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a third embodiment of a system on a chip provided in the present utility model, where the system on a chip 100 includes a bus 10, a master core 20, a memory 30 and a WDT module 40, where the master core 20 is connected to the bus 10, the memory 30 is connected to the bus 10, and the WDT module 40 is connected to the master core 20.

Further, the system on chip 100 further includes a first ECC module 301, where the first ECC module 301 is connected to the bus 10 or integrated with the memory 30, and the first ECC module 301 is configured to perform data detection and correction when the memory 30 performs data interaction with the main core 20.

Wherein the WDT module 40 is connected to the master core 20, and the WDT module 40 is configured to receive the watchdog signal of the master core 20, and send a reset signal to the master core 20 when the watchdog signal is not received within a set time, so as to reset the master core 20.

It can be understood that in a microcomputer system composed of chips (such as a single-chip microcomputer, a CPU, an MCU, etc.), since the operation of the chips is often interfered by an external electromagnetic field, resulting in data confusion of various registers and memories, errors of program pointers, erroneous program instructions and the like are not in a program area, and the program instructions and the like may be trapped in dead loops, normal operation of the program is interrupted, and a system controlled by the single-chip microcomputer cannot continue to normally operate, resulting in a trapped and stagnant state of the whole system, which has unexpected consequences. WDT (watchdog) is a timer circuit, generally has an input called a dog feeding (dog/service dog), an RST end is output to the chip, when the chip works normally, a signal is output to the dog feeding end at intervals, WDT is cleared, if the WDT is not fed for a prescribed time (generally when the program runs off), a reset signal is given to the chip if the WDT is exceeded, the chip is reset, and the chip is prevented from being dead. The function of the watchdog is to prevent the program from endless loops, or running off.

It will be appreciated that when the number of master cores 20 in the system on chip 100 is plural, the number of WDT modules 40 may be plural, with one WDT module 40 configured for each master core 20.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a fourth embodiment of a system on a chip provided by the present utility model, where the system on a chip 100 includes a bus 10, a master core 20 and a memory 30, and the master core 20 is connected to the bus 10, and the memory 30 is connected to the bus 10.

Further, the system on chip 100 further includes a first ECC module 301, where the first ECC module 301 is connected to the bus 10 or integrated with the memory 30, and the first ECC module 301 is configured to perform data detection and correction when the memory 30 performs data interaction with the main core 20.

Further, the system on chip 100 further includes an inspection kernel 50 and an inspection module 60, the inspection kernel 50 and the master kernel 20 are in lockstep operation; the checking module 60 connects the master core 20 and the checking core 50, and the checking module 60 is configured to monitor the running deviation of the master core 20 and the checking core 50.

It will be appreciated that the checking kernel 50 is also known as a lock-step kernel (lock-step core), which is a conventional method of achieving high diagnostic coverage (the ability to detect the occurrence of errors). The implementation method is as follows: the two cores run the same program or instruction and input the results into a comparison logic (implemented by the check module 60) to periodically compare whether the output results of the two cores are the same. Specifically, the address of the core and the data bus are compared at the checking module 60 to detect the running deviation. The detected errors are reported to an error collection and countermeasures module. Due to the lockstep, from a software perspective, the two kernels run as a single kernel, reducing software implementation.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a system-on-chip 100 according to a fifth embodiment of the present utility model, where the system-on-chip 100 includes a bus 10, a master core 20 and a memory 30, and the master core 20 is connected to the bus 10, and the memory 30 is connected to the bus 10.

Further, the system on chip 100 further includes a first ECC module 301, where the first ECC module 301 is connected to the bus 10 or integrated with the memory 30, and the first ECC module 301 is configured to perform data detection and correction when the memory 30 performs data interaction with the main core 20.

Further, in this embodiment, the Cache module 22 is integrated in the main kernel, where the Cache module 22 is configured to perform instruction Cache or data Cache, and perform read, modify, and write operations on the cached instruction or data, where the read, modify, and write operations are based on an ECC protection mechanism.

Specifically, the Cache protection mechanism supports single-bit error correction and double-bit error detection, and can perform instruction Cache, data Cache and kernel automatic read, modification and write operations (RMW) on the data Cache. The Cache ECC error can be recovered, the Write-through can determine that the Cache data is consistent with the external memory, the mechanism is that when single bit or double bit error is detected, self-checking can be carried out, a Cache identification bit is automatically set to be invalid, and the kernel accesses to directly acquire the data from the external memory; when a multi-bit error is detected, reporting the error to a corresponding processing unit.

When the Cache protection mechanism is started, a corresponding processing mode is set in the aspect of software operation, reset and reporting can be performed, meanwhile, MBIST (memory build-in-self test) can be started by software, the MBIST can identify faults of all memories, ECC logic, time sequences and the like in a system, and the software checks reports by starting the MBIST, so that the working state of the system is judged, and the accuracy of functional safety is ensured.

Further, in the present embodiment, the TCM module 23 is integrated in the main kernel, and the TCM module 23 is configured to perform access writing, and perform reading, modifying, and writing operations on the data accessed and written, where the reading, modifying, and writing operations are based on an ECC protection mechanism.

Specifically, the TCM (Tightly coupled memory ) protection mechanism may implement single bit error correction and double bit error detection, specifically including ECC code generation, verification, and writing of correct correction data. To support partial storage, the processor includes logic to perform read, modify, write (RMW) operations, so a complete ECC module can implement any write access write. Generating ECC check bits according to the bit width (chunk width) of the ECC module, wherein a write operation smaller than the chunk width needs to regenerate the ECC check bits, and when a check error occurs in a read operation of the RMW, an RMW error warning is generated in addition to a normal read error warning.

It will be appreciated that kernel access and AXIS interface access can be accomplished in the TCM protection mechanism.

For kernel access:

when a single bit error is detected, directly correcting by ECC logic and outputting corrected data; when a double bit error is detected, a fault (fault) indication is sent to an LSU (Load/Store Unit) or a PFU (Prefetch Unit).

Access to the AXIS interface:

read access: the single bit error is directly corrected by ECC logic, and the corrected data (and OKEY indication) is written back to the TCM while being returned to the Master through the AXIS port; the double bit error cannot be corrected and only an SLVERR indication can be returned to the Master.

Write access: the single bit error is directly corrected by ECC logic, the corrected data is written into the TCM, and meanwhile, the Master returns an OKEY indication; the double bit error cannot be corrected and only the Master can be supposed to return an SLVERR indication.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a sixth embodiment of a system on a chip 100 according to the present utility model, where the system on a chip 100 includes a bus 10, a master core 20 and a memory 30, and the master core 20 is connected to the bus 10, and the memory 30 is connected to the bus 10.

Further, the system on chip 100 further includes a first ECC module 301, where the first ECC module 301 is connected to the bus 10 or integrated with the memory 30, and the first ECC module 301 is configured to perform data detection and correction when the memory 30 performs data interaction with the main core 20.

Further, in the present embodiment, a first MPU module 241 and a second MPU module 242 are integrated in the main kernel, the first MPU module 241 being configured to be accessed by the EL1 register, and the second MPU module 242 being configured to be accessed by the EL2 register.

Among them, there are four exception levels, EL0 to EL3, based on the ARMv8 chip architecture. For the exception level ELn, an increase in integer n indicates that the privilege level of software execution becomes greater. Execution at the EL0 level is called non-privileged execution (unprivileged execution). EL1 is used primarily to run operating system kernels. EL2 may support virtualization of non-secure operations. EL3 then supports transitions between secure and non-secure states. The security state is related to ARM trust zone technology. The secure state may run a trusted execution environment (TEE, trusted Execution Environment) and secure applications for securing private data and the program execution environment.

Specifically, each level of abnormality is controlled by one register, that is, an EL1 register is used to control abnormality of the EL1 level, and an EL2 register is used to control abnormality of the EL2 level.

In this embodiment, the first MPU module 241 defines a protection area accessed from the EL2 register. When virtualization is enabled, the second MPU module 242 uses its own protected area to modify the access rights and memory attributes assigned by the first MPU module 241 for accesses from the EL1 register and the EL0 register. In the system, the EL0 register, the EL1 register and the EL2 register have different storage spaces and have different access rights, if the access rights exceed the access rights, corresponding access warning can be generated, the specific access rights can be configured by system software, and when errors occur, the software can reset the system or report the corresponding errors.

It will be appreciated that in the embodiments of FIGS. 1-6 described above, the master core, the check module, and the WDT module, ECC module integrated with the master core, cache module, and TCM module that connect to the master core may be considered a unit, whereas in the system on a chip 100, such a unit may be multiple. Taking the Cortex-R52 architecture as an example, the number of such units is 3.

Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of an automobile provided by the present utility model, the automobile 800 includes a system-on-chip 100, and the system-on-chip 100 is described in the above embodiment.

Optionally, the automobile 800 of the present embodiment is an electric automobile, and the system on chip 100 is mainly applied to a vehicle-mounted system of the automobile 800 for data management.

In the several embodiments provided in the present utility model, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional unit in each embodiment of the present utility model may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The key recognition method, the electronic device and the computer readable storage medium provided by the embodiments of the present utility model are described in detail, and specific examples are applied to illustrate the principles and the implementation of the present utility model, and the description of the above embodiments is only used to help understand the method and the core idea of the present utility model; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present utility model, the present description should not be construed as limiting the present utility model.

Claims (10)

1. A system-on-chip, the system-on-chip comprising:

a bus;

the main kernel is connected with the bus;

a memory, the memory being connected to the bus;

the first ECC module is connected with the bus or integrated in the memory, and is configured to detect and correct data when the memory and the main kernel perform data interaction.

2. The system on a chip of claim 1, wherein the system on a chip,

the system on chip further comprises a second ECC module, wherein the second ECC module is connected with the bus or integrated with the main kernel, and the second ECC module is configured to detect and correct data when the memory and the main kernel interact with each other.

3. The system on a chip of claim 1 or 2, wherein,

the system on chip further comprises a third ECC module integrated with the bus, wherein the third ECC module is configured to detect and correct data when the memory and the main kernel interact data or the main kernel interacts data with the outside.

4. The system on a chip of claim 1, wherein the system on a chip,

the memory includes at least one of random access memory, read only memory, and flash memory.

5. The system on a chip of claim 1, wherein the system on a chip,

the system on a chip further comprises a WDT module, wherein the WDT module is connected with the main kernel, and is configured to receive a dog feeding signal of the main kernel, and send a reset signal to the main kernel when the dog feeding signal is not received within a set time, so that the main kernel is reset.

6. The system on a chip of claim 1, wherein the system on a chip,

the system on a chip further comprises:

checking a kernel, wherein the checking kernel and the master kernel run in a lockstep manner;

and the checking module is connected with the main kernel and the checking kernel and is configured to monitor the running deviation of the main kernel and the checking kernel.

7. The system on a chip of claim 1, wherein the system on a chip,

the main kernel is integrated with a Cache module, the Cache module is configured to Cache instructions or data, and read, modify and write the cached instructions or data, and the read, modify and write operations are based on an ECC protection mechanism.

8. The system on a chip of claim 1, wherein the system on a chip,

the TCM module is integrated in the main kernel and is configured to perform access writing, and perform reading, modifying and writing operations on data accessed and written, wherein the reading, modifying and writing operations are based on an ECC protection mechanism.

9. The system on a chip of claim 1, wherein the system on a chip,

a first MPU module configured to be accessed by the EL1 register and a second MPU module configured to be accessed by the EL2 register are integrated in the main kernel.

10. An automobile, characterized in that it comprises a system on chip according to any one of claims 1-9.