CN107885611B - Fault-tolerant method and device for hierarchical instruction memory structure capable of actively writing back - Google Patents

Fault-tolerant method and device for hierarchical instruction memory structure capable of actively writing back Download PDF

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CN107885611B
CN107885611B CN201711195578.7A CN201711195578A CN107885611B CN 107885611 B CN107885611 B CN 107885611B CN 201711195578 A CN201711195578 A CN 201711195578A CN 107885611 B CN107885611 B CN 107885611B
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instruction
memory
word
address
register
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CN107885611A (en
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曹辉
何卫强
杨靓
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Xian Microelectronics Technology Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions

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Abstract

The invention provides a fault-tolerant method and a fault-tolerant device of a hierarchical instruction memory structure capable of actively writing back, wherein the device comprises a hierarchical instruction memory, an instruction error correction and detection module, an instruction word register and an instruction address register; the method comprises the steps that 1, a processor is started to run; 2. fetching instruction word data from a hierarchical instruction memory; 3. the instruction word data is sent to an instruction error correction and detection module; 4. judging whether the error correction and detection result is error-free or error-correctable; if yes, continuing to step 5; if not, turning to the step 10; 5. writing an instruction word into an instruction word register; 6. updating an instruction address register; 7. judging that a correctable error occurs; if yes, continue step 8; if not, turning to the step 9; 8. writing the instruction word data back to the hierarchical instruction memory; 9. finishing the treatment; turning to step 2, processing the next instruction address; 10. an uncorrectable error occurs in the instruction word data and the processor is suspended. The invention realizes the fault tolerance of the instruction and the instruction memory and has lower hardware cost.

Description

Fault-tolerant method and device for hierarchical instruction memory structure capable of actively writing back
Technical Field
The invention belongs to the field of microprocessor design, relates to a fault-tolerant structure design of a high-reliability and high-performance processor, and particularly relates to a fault-tolerant method and a fault-tolerant device of a hierarchical instruction memory structure capable of actively writing back.
Background
On-chip memory is a sensitive unit within a processor. On-chip memory typically occupies a large amount of area in the overall processor and is susceptible to high energy particles, cosmic rays, and the like. In particular, as the feature size of integrated circuits is dramatically reduced, memory cells are increasingly sensitive to operating environments due to the ever-decreasing supply voltages, ever-increasing operating frequencies, ever-decreasing node capacitances, and high-speed growth of chip transistor capacities. Therefore, in order to improve the reliability of the processor, on-chip memory needs to be fault-tolerant hardened. Moreover, in many processors with low reliability requirements, fault-tolerant hardening of on-chip memory is a necessary condition for ensuring reliability. For a processor having a radiation environment for aerospace applications and the like, in order to ensure reliability of tasks, fault-tolerant reinforcement processing is particularly required for an on-chip memory. For a processor facing image signal and digital signal processing, because the updating frequency of an instruction memory for storing instruction data of a core algorithm is far lower than that of a data memory, the influence of the instruction memory on the modes of single-particle error accumulation, total dose effect and the like in an irradiation environment is further increased.
The reinforcement of the on-chip instruction memory from the architecture level can correct the memory unit from the knocked-over state back to the correct state, and can keep the transparency to upper software, which is a preferred method in the reliability design of the memory. When the accessed data finds an error, the data block is forced to "miss", the processor core "hangs" and reloads the data from the outside to the on-chip memory, as disclosed in "A portable and fault-free microprocessor based on the spark v8 architecture" of the document Gaisler,2002, with parity code error detection for the first level program and the on-chip memory of the data. Since parity checks can only detect errors, when a data error occurs in memory (including data memory and instruction memory), the processor invalidates the current cache block and reloads the data from external memory. This "passive" approach not only allows the processor to wait for the instruction to reload, resulting in performance degradation; and for on-chip integrated multi-core processors, reloading data from a shared memory or an external memory through an on-chip bus or network on chip (NoC) may result in "reloading" transfers and normal data transfers competing for on-chip bandwidth. Most digital signal processors have only one memory structure, and are provided with independent program memories and Data memories, such as "MSC 8102 Technical Data" published in 2005 by Freescale, and "TriMedia (TM) -1300" published in 2000 by Philips, and "TMs 320C6000 CPU and Instruction Set Reference Guide" published in 2000 by Texas Instruments, which do not update the write-back of the on-chip Instruction memory in time, resulting in the cumulative effect of memory errors. In addition, the extreme approach of disabling on-chip instruction memory in aerospace embedded processor applications introduces significant performance loss.
Further, the operations of digital signal and image processing are mostly regular data flow operations. In order to improve the data processing throughput and speed up the algorithm execution during the processor implementation, the regular operation is often implemented as a core algorithm instruction, so that one instruction can control and implement a plurality of micro-operations. Therefore, a plurality of control fields are needed for the core algorithm instruction, and the instruction encoding field is long; and the general instruction has simple function and shorter encoding field. This further increases the vulnerability of the dsp instructions, because once a field error occurs to distinguish between long and short instructions, the dsp cannot distinguish and access subsequent instructions with the correct width, resulting in program execution exceptions.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a fault-tolerant method and a fault-tolerant device of a hierarchical instruction memory structure capable of actively writing back, wherein instruction data after error correction and detection are actively written back into the hierarchical instruction memory structure, the instruction data has higher refreshing frequency for instructions with high use frequency, and the instruction data is sent to a processor immediately after on-line error correction and detection, so that the problem of error accumulation of the instruction memory is solved.
The invention is realized by the following technical scheme:
the fault-tolerant device of the hierarchical instruction memory structure capable of actively writing back comprises a hierarchical instruction memory, an instruction error detection and correction module, an instruction word register and an instruction address register;
the input end of the hierarchical instruction memory is connected with the output end of the instruction address register, instruction word data are selected and output according to an instruction address stored in the input instruction address register, and the output is connected to the instruction error correction and detection block and the instruction address register; the input end of the hierarchical instruction memory is also connected with the output end of the instruction error detection and correction module, and refreshes and writes back the hierarchical instruction memory according to the instruction word data after error detection and correction output by the instruction error detection and correction module;
the input end of the instruction error detection and correction module is connected with the output end of the hierarchical instruction memory, receives instruction word data output by the hierarchical instruction memory, detects and corrects the instruction word data, outputs the instruction word data after error detection and correction and error state, and the output end of the instruction error detection and correction module is respectively connected with the input ends of the hierarchical instruction memory, the instruction word register and the instruction address register;
the instruction word register receives instruction word data output by the instruction error correction and detection module, selectively arranges the instructions in the instruction register and combines the instructions supported by the processor;
the input end of the instruction address register is accessed to instruction word data output by the hierarchical instruction memory, error correction and detection instruction word data and an error state output by the instruction error correction and detection module, and instruction jump information of the processor, and the output end of the instruction address register outputs a current instruction address temporarily stored in the instruction address register;
the instruction word data includes an instruction word and a check bit of the instruction word.
Preferably, the instruction address register includes an address register and an instruction address update logic module; the address register stores the address of the current instruction fetch; the instruction address updating logic is used for processing the memory address of the next instruction fetching instruction; the output of the instruction address updating logic module is connected to the address register; the address register latches the logic level output by the instruction address updating module; the instruction address updating logic generates a new value instruction address according to input instruction word data, the instruction data after error correction and detection, error states and jump information of processor instructions; latching an instruction fetching address output by the instruction address updating logic by the address register;
the instruction address register is sequentially divided into three parts from high order to low order: a first bit section, a second bit section and a third bit section; the first bit segment is matched with the base address identifier of each instruction cache block of the first instruction memory, and whether the current access instruction is in the first instruction memory is judged; if the instruction accessed by the instruction address is not in the first instruction memory, the second instruction memory needs to be accessed by the first bit segment, and the instruction word block pointed by the first bit segment of the address is written into the first instruction memory; the second bit segment is used for selecting the L pointed by the second bit segment of the address from the matched instruction cache block under the condition that the first bit segment is matched1A bit instruction word and corresponding check bits; the third field is used for selecting a starting instruction word from all instruction words of the instruction word data to write into the 1 st instruction word register, and other instruction words are sequentially written into the corresponding instruction word registers in sequence.
Further, the hierarchical instruction memory is used for storing processor instructions of different lengths, the processor instructions including lengths distinguished by instruction identification bit segments SIs L1Is a first length instruction and has a length of L2A second length instruction of (1); the length of the first length instruction is greater than that of the second length instruction; the first length instructions and the second length instructions are stored aligned in a mixed manner in the hierarchical instruction memory;
the hierarchical instruction memory comprises a first instruction memory and a second instruction memory which are interactive; wherein the output of the first instruction memory is connected to the instruction word data output of the hierarchical instruction memory; the input of the first instruction memory is connected to the input of the hierarchical instruction memory, and the instruction word data after error correction and detection, the error state and the instruction address register output by the instruction error correction and detection module are connected;
the first instruction memory selects and outputs instruction word data according to the address of the instruction address register, and when the error state of the instruction word is identified as that a correctable error of data occurs, the instruction word data after error correction and detection is written back to the first instruction memory; the first instruction memory and the second instruction memory are connected through a data exchange bus, instruction word data stored in the second instruction memory are loaded to the first instruction memory, and instruction word data stored in the first instruction memory are written back to the second instruction memory; the stored instruction word data is exchanged between the first instruction memory and the second instruction memory in instruction word blocks.
Still further, the first instruction memory includes at least one set of instruction bits L having a first length1The instruction cache unit and the check word cache unit; the first instruction memory outputs L bit width according to the current instruction address of the instruction address register1The check word corresponding to the instruction word is output at the same time;
the first instruction memory judges whether the instruction word data accessed by the current instruction address is in an instruction cache unit of the first instruction memory according to the first bit segment of the instruction address register; if the accessed instruction word is in the instruction cache unit, outputting the accessed instruction word and the corresponding check word from an instruction word data output end; if the accessed instruction is not in the instruction cache unit, waiting for the writing of the capacity of the instruction cache unit from the second instruction memory to the first instruction memory to beQ, bit width is the first length instruction bit width L1After the instruction word with the size is processed, judging that the accessed instruction is already in the instruction cache of the first instruction memory again; if the accessed instruction word is in the instruction cache unit, outputting the accessed instruction word and the corresponding check word from an instruction word data output end;
the first instruction memory receives the instruction word data after error correction and detection and writes the instruction word data after error correction and detection back to the hierarchical instruction memory; if the error state of the input instruction word data is identified as correctable error of the instruction word data, writing the instruction word data back to an instruction cache unit in the first instruction memory;
the second instruction memory writes instruction word data into the first instruction memory; the first instruction memory writes the instruction word data in the selected instruction cache block and check word cache block for storing the input instruction word data of the second instruction memory back to the second memory before receiving the instruction word data written in the second instruction memory;
the instruction memory of the second instruction memory stores the first length instruction and the second length instruction in such a way that if the type identification bits of the first length instruction and the second length instruction are at the highest bit of the instruction, the instruction stores the high bit at the low address and the low bit at the high address in units of words; if the type identification bits of the first length instruction and the second length instruction are on the lowest order bits of the instruction, the instruction stores the high order bits at a high address and the low order bits at a low address in units of words, wherein the words are the greatest common denominator words of the first length instruction and the second length instruction.
When the second instruction memory writes instruction word data into the first instruction memory, if the instruction word data has already been written into the instruction cache block and the check word cache block in the selected first instruction memory, the first instruction memory writes the instruction word data in the selected instruction cache block and check word cache block back to the second instruction memory according to the original base address of the instruction word data in the second instruction memory; then, writing instruction word data into the first instruction memory by the second instruction memory; first of allInstruction memory stores L in instruction cache block1The instruction word block with bit width is disassembled into instruction data in word bit unit and written back to the second instruction memory.
Further, the instruction address updating logic module is used for carrying out processing logic with priority order; the priority order of updating the instruction addresses is as follows from high to low: instruction branch jumping, instruction address compensation correction and instruction address self-increment;
the instruction address compensation correction is used for compensating and correcting the address register after the address is increased; when a correctable error occurs and the error bit is an instruction type identification bit, the instruction address compensation correction logic corrects the increment of the current instruction address back to the correct address of the next instruction fetch instruction;
when the instruction address is corrected, if the instruction type identification bit is judged to be wrong,
when the first length instruction is judged to be the second length instruction, the compensation increment of the instruction address is positive compensation;
when the second length instruction is judged to be the first length instruction, the compensation increment of the instruction address is negative compensation.
Further, the instruction word registers include a set of registers capable of storing at least instructions of a first length, including a 1 st instruction word register, a 2 nd instruction word register, … …, a l1An instruction word register;
the first length instruction and the second length instruction identify the instruction type through a bit segment S in the instruction;
if the bit segment for marking the instruction type is at the highest position of the instruction, the instruction register is marked with 1, 21And storing the first length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2An instruction word register;
if the bit segment identifying the instruction type is at the least significant bit of the instruction, the instruction register is word-wise orderedBit width is unit, and according to instruction length type, the numbers of low word and high word are 1, 21And storing the first length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2An instruction word register.
Wherein l1Is the number of instruction words after the first length instructions are grouped by word, l2The instruction word number of the second length instruction after being grouped according to words, the instruction word register selects the starting instruction word from the instruction word data according to the third bit segment of the instruction address register, the starting instruction word is written into the 1 st instruction word register, the subsequent instruction words are sequentially written into the k th instruction register, and k can arbitrarily take 1, 21。
The invention discloses a fault-tolerant method of a hierarchical instruction storage structure capable of actively writing back, which comprises the following steps:
step 1, starting a processor to operate;
step 2, according to the address in the present instruction address register, fetch the instruction word data from the hierarchical instruction memory;
step 3, the instruction word data is sent to an instruction error correction and detection module to carry out error correction and detection judgment;
step 4, judging whether the error correction and detection result is error-free or error-correctable; if yes, continuing to step 5; otherwise, turning to step 10;
step 5, writing the instruction word into an instruction word register;
step 6, updating an instruction address register;
step 7, judging whether a correctable error occurs or not; if yes, continuing to step 8; otherwise, turning to step 9;
step 8, writing the instruction word data back to the hierarchical instruction memory;
step 9, finishing the current processing; turning to step 2, processing the next instruction address;
and 10, sending an uncorrectable error interrupt when the instruction word data generates an uncorrectable error, and suspending the processor.
Preferably, in step 2, the method for fetching instruction word data from the hierarchical instruction memory includes:
step 2-1: matching whether an instruction cache block accessed by an instruction address is in a first instruction memory or not according to a first bit segment of an instruction address register; if yes, turning to the step 2-3; otherwise, continuing the step 2-2;
step 2-2: reading an instruction word block addressed by a first bit field of an instruction address register from a second instruction memory, and writing the instruction word block into a first instruction memory; turning to step 2-1;
step 2-3: and in the matched instruction word cache block, addressing according to a second bit segment of the instruction address register, selecting a row of instruction words in the instruction cache block to output, and simultaneously selecting a check word corresponding to the instruction word to output as instruction word data.
Further, step 2-2 further comprises the steps of:
step 2-2-1, selecting one instruction cache block from the instruction cache blocks of the first instruction memory as an instruction cache block to be written in;
step 2-2-2, judging whether the instruction word block is stored in the current instruction cache block; if yes, continuing the step 2-2-3; otherwise, turning to the step 2-2-5;
step 2-2-3, judging whether the error state of the selected instruction cache block has an uncorrectable error; if yes, outputting an uncorrectable error signal by the instruction error correction and detection module, connecting the signal to the interrupt processing of the main processor, and turning to 2-2-7; otherwise, continuing the step 2-2-4;
step 2-2-4, according to the instruction word block base address of the selected instruction cache block in the second instruction memory, writing the instruction word in the selected instruction cache block and the corresponding check word into the second instruction memory;
step 2-2-5, according to the first bit segment of the current instruction address register, addressing in the second instruction memory according to the first bit segment, reading the addressed instruction word block from the second instruction memory, writing the addressed instruction word block into the selected instruction cache block in the first instruction memory, and writing the first bit segment of the corresponding instruction address register into the base address register of the instruction cache block; reading the check bits corresponding to the instruction word block from the second instruction memory, and writing the check bits into the check word cache block corresponding to the instruction cache block;
step 2-2-6, marking the status register of the selected instruction cache block as error-free;
step 2-2-7, finishing the treatment;
when the instruction word data without errors or the instruction word data after error correction is written back from the first instruction memory to the second instruction memory by taking the instruction word block as a unit, the instruction word data are processed by the steps 2-2-1 to 2-2-7.
Compared with the prior art, the invention has the following beneficial technical effects:
the fault-tolerant method of the hierarchical instruction memory structure capable of actively writing back can write the corrected data back to the instruction memory actively after detecting the data error of the memory, and because a write-back path from fast memory to slow memory is provided, the reliability is ensured and the loss of the execution efficiency of a processor is avoided; the passive processing method uses the processing path from slow memory to fast memory, which is the opposite of the present invention, so that the processor has larger waiting delay and the execution efficiency of the processor is reduced. Especially, when tens or hundreds of processor cores are integrated by adopting an on-chip network, when data is requested passively from an external memory or a shared slow memory, a larger on-chip communication bandwidth is occupied, and larger data delay is generated. The invention fully utilizes the locality principle of the program, has higher updating frequency for frequently used local instructions and also improves the reliability of the partial instructions. The error detection and correction logic adopts odd weight and check word encoding of the shortest check word generation path, so that the delay of the error detection and correction logic is reduced, and the reliability of the instruction memory is improved compared with a simple check method. The method can be extended to a multiprocessor system or a logic processor with an operating system, and can be used for actively tolerating data.
Furthermore, the opportunity of writing the instruction word data back to the second instruction memory can utilize the gap of the first instruction memory to access the second memory, and the execution time of the processor is not occupied.
The fault-tolerant device provided by the invention can be realized by hardware, and the logic for accessing the first instruction memory, the error correction and detection module, the instruction address register and the instruction register is arranged in a production line of the processor, so that effective fault tolerance is realized under the condition of not reducing the main frequency of the processor. Further, once an instruction is found to be faulty and correctable, the instruction is sent to the decode unit after being corrected "on-line". The process has no condition that the processor waits for the correct instruction to be reloaded, and the execution efficiency of the instruction is not influenced. The invention has one-time correction to the instruction, and the error state detection of the error state of the whole instruction block is needed in the traditional passive replacement process, thereby undoubtedly increasing the data access delay. The method combines the instruction fetching access logic of the instruction words with indefinite length, realizes the fault tolerance of the instruction and the instruction memory under the condition of only increasing the data error correction and detection logic, and has lower hardware cost.
Drawings
FIG. 1: a system integration architecture for processor memory "passive" fault tolerant devices;
FIG. 2 is a drawing: the invention relates to a system integration structure of a hierarchical instruction memory structure fault-tolerant device capable of actively writing back;
FIG. 3: the invention can write back the fault-tolerant device of the hierarchical instruction memory voluntarily;
FIG. 4 is a drawing: the invention relates to an instruction type bit section of a first length instruction and a second length instruction;
FIG. 5: the storage mode of the first length instruction and the second length instruction in a second instruction memory is disclosed;
FIG. 6: the invention relates to a fault-tolerant method of a hierarchical instruction memory structure capable of actively writing back;
FIG. 7: the invention is a method for fetching instruction word data from a hierarchical instruction memory;
FIG. 8: the second instruction memory writes the data block into the first instruction memory;
FIG. 9: the invention relates to a method for writing error-corrected instruction word data back to a hierarchical instruction memory;
FIG. 10: the invention relates to a method for processing a device in a pipeline manner.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
Currently, most processors' fault-tolerant hardening of memory is a "passive" approach, as shown in FIG. 1, which illustrates the fault-tolerant process of instruction memory "passive" loading. The system integrates two processors 110 and 120. Each processor incorporates a separate instruction memory 111 and 121, instruction word checking logic 112 and 122 integrated between the processor and the instruction memory, the processors 110 and 120 are connected to an external memory or shared memory 140 via an on-chip bus or network 130. The output instruction data of the external memory or the shared memory is written into the instruction memories 111 and 121 through the bus or the on-chip network after passing through the error checking and correcting logic ECC 141 and parity encoding, the processor 110 or 120 accesses the instruction from the instruction memory, and when the checking logic 112 or 122 detects an instruction error, a request signal 113 or 123 for instruction error reloading is sent to the bus or the on-chip network, at this time, the processor 110 or 120 is in a suspend state, and waits for the instruction to be reloaded into the instruction memory 111 or 121 from the external memory or the shared memory 140, and the processor continues to execute the instruction. The arrowed directions of the thin and open lines in fig. 1 only indicate the direction of data transfer to support fault tolerance, and do not fully indicate the exchange of data between the instruction stores 111 and 121 and the memory 140 on the processor chip. The apparatus of fig. 1, when detecting an instruction error, the processor waits for the bus or network on chip to respond to the instruction reload request until the processor starts running again after the correct instruction reload is completed. If the processor priority is low, or the bus and network on chip are congested, it will cause the processor to wait longer.
The present invention provides a system integration structure of fault-tolerant device of hierarchical instruction memory structure capable of active write-back, as shown in FIG. 2, the system integrates two processors 210 and 220. Each processor integrates separate first instruction memory 211 and 221 and second instruction memory 212 and 222. Instruction word error correction and detection logic 213 and 223 is integrated within the processor; processors 210 and 220 are connected to external memory or shared memory 240 through an on-chip bus or network 230. The output command data of the external memory or the shared memory is written into the second command memories 212 and 222 through the error checking and correcting logic ECC 241 through the bus or the network on chip; processor 210 or 220 accesses instructions from first instruction memory and, when error correction detection logic 213 or 223 detects an instruction correctable error, first writes the corrected instruction word back to first instruction memory 211 or 221 at instruction word data granularity; and writes instruction word data back to the second instruction memory 212 or 222 at an instruction word block granularity when the second instruction memory 212 or 222 writes instructions to the first instruction memory 211 or 221. The arrow direction of the thin and open lines in fig. 1 indicates the direction of data transfer to support fault tolerance, and does not fully indicate the exchange of data between the instruction stores 211 and 212, 221 and 222 and the memory 240. The apparatus shown in fig. 2 can keep the instruction execution uninterrupted by the processor after detecting and correcting the instruction error, thereby improving the system reliability and ensuring the execution efficiency of the processor.
The invention relates to a fault-tolerant device of a hierarchical instruction memory structure capable of actively writing back, which comprises a hierarchical instruction memory, an instruction error correction and detection module, an instruction word register and an instruction address register. The connection relationship among the modules is as follows: the hierarchical instruction memory selects and outputs instruction word data according to an instruction address stored in an input instruction address register, and the output is connected to an instruction error correction and detection block and the instruction address register; furthermore, the hierarchical instruction memory receives the instruction word data after error detection and correction output by the instruction error detection and correction module, and refreshes and writes back the instruction word data to the hierarchical instruction memory. The instruction error detection and correction module receives instruction word data output by the hierarchical instruction memory, detects and corrects the instruction word data, outputs the instruction word data and error state after error detection and correction, and connects the output to the hierarchical instruction memory, the instruction word register and the instruction address register. The instruction word register receives the instruction word data output by the instruction error detection and correction module, selectively arranges the instructions in the instruction register and combines the instructions supported by the processor. The instruction address register has the input of instruction word data output by the hierarchical instruction memory, error correction and detection instruction word data and error state output by the instruction error correction and detection module, and instruction jump information of the processor, and the output of the instruction address register is the current instruction address temporarily stored in the instruction address register. The instruction word data includes an instruction word and a check bit of the instruction word.
The hierarchical instruction memory includes a first instruction memory and a second instruction memory. Wherein the output of the first instruction memory is connected to the instruction word data output of the hierarchical instruction memory; the input of the first instruction memory is connected to the input of the hierarchical instruction memory, namely instruction word data after error correction and detection, an error state and an instruction address register output by the instruction error correction and detection module. The first instruction memory selectively outputs instruction word data according to the address of the instruction address register. And when the instruction word error state is identified as that the data correctable error occurs, writing the instruction word data after error correction and detection back to the first instruction memory. The first instruction memory and the second instruction memory are connected through a data exchange bus; the instruction word data stored in the second instruction memory is loaded to the first instruction memory; the instruction word data stored in the first instruction memory is written back to the second instruction memory. Exchanging stored instruction word data between the first instruction memory and the second instruction memory according to instruction word blocks; the first instruction memory comprises at least one group of instruction bits L with a first length1An instruction cache unit and a check word cache unit.
The first instruction memory receives the instruction word data after error correction and detection and writes the instruction word data after error correction and detection back to the hierarchical instruction memory. And if the error state of the input instruction word data is identified as that the correctable error of the instruction word data occurs, writing the instruction word data back to the instruction cache unit in the first instruction memory. Wherein L is1The bit-wide instruction words are written sequentially into a row of the instruction cache unit of the first instruction memory. The check words are written into a row of the check word cache unit in sequence.
The instruction cache unit in the first instruction memory is a unit bit width based on word bit width, and the total bit width is a first length instructionBit width L1Of a plurality of parallel memory banks, l1And splicing the memory banks. Data input and output of instruction cache unit are controlled by1The data input and output of each instruction memory bank are spliced in sequence. Check word buffer unit is composed of1And the check word memory banks are spliced, and the memory bank of the instruction cache unit is provided with a corresponding check word memory bank. The word bit width is a minimum integer word access bit width of the first length instruction and the second length instruction.
The instruction cache unit and the check word cache unit of the first instruction memory at least comprise a read control port and a write control port which can read and write simultaneously. The instruction cache unit and the check word cache unit of the first instruction memory may be implemented by dual port bank stitching or packet register bank stitching.
An instruction memory of the second instruction memory stores a first length instruction and a second length instruction. The storage mode of the first length instruction and the second length instruction in the second instruction memory is as follows: if the type identification bits of the first length instruction and the second length instruction are positioned at the highest position of the instruction, the instruction stores the high position at a low address by taking a word as a unit, and stores the low position at the high address; if the type identification bits of the first length instruction and the second length instruction are at the lowest order bits of the instruction, the instruction stores the high order bits at the high address and the low order bits at the low address in units of words.
The first length instructions are aligned in the second instruction memory at even addresses, i.e. the first length instructions are stored in a contiguous word memory bank starting at the even addresses. The first length instruction and the second length instruction are stored in the first instruction memory in such a way that the instructions are organized into L according to the sequence of storage in the second instruction memory in word units1And storing the bit width data into an instruction cache of the first instruction memory.
When the second instruction memory loads instruction word data to the first instruction memory, according to the instruction base address required by the first instruction memory, sequentially writing instruction word blocks with the size of the instruction cache block of the first instruction memory into the first instruction memory, and correcting corresponding instruction word blocksAnd the check data block is written into a check word cache unit corresponding to the instruction cache unit. The instruction blocks of the second instruction memory are sequentially adjusted to L1The bit-wide data is written into an instruction cache block of the first instruction memory. The instruction base address is generated by a first instruction memory according to a first bit segment of a current instruction address register.
When the second instruction memory writes instruction word data into the first instruction memory, if the instruction word data has been written into the instruction cache block and the check word cache block in the selected first instruction memory, the first instruction memory writes the instruction word data in the selected instruction cache block and check word cache block back to the second instruction memory according to the original base address of the instruction word data in the second instruction memory; then, the second instruction memory writes the instruction word data into the first instruction memory. The first instruction memory stores L in the instruction cache block1The instruction word block with bit width is disassembled into instruction data in word bit unit and written back to the second instruction memory.
And the instruction word error correction module is used for carrying out error detection and correction on the instruction word data output by the hierarchical instruction memory. Under the condition that the instruction word has no error, the data is normally output; outputting corrected data and outputting a 'correctable error state' under the condition that correctable errors occur in the instruction words; in the case where an uncorrectable error occurs in the instruction word, error data is output, and an "uncorrectable error state" is output.
Preferably, the instruction word data error correction and detection processing is performed in units of words. The error correction and detection module comprises1Parallel error correction module with word-by-word unit capable of correcting1Bit errors, detecting 2 × l1A bit error. The correctable error state of the instruction word data is l1A correctable error state combination of the group instructions; the uncorrectable error state is l1An uncorrectable error state combination of the group instruction words.
The instruction word registers include a set of registers capable of storing at least instructions of a first length, including a 1 st instruction word register, a 2 nd instruction word register, … …, an l1An instruction word register. Preferably, the bit width of the k-th instruction register is a word bit width. Storing a first length instruction in an instruction 1 st instruction word register, an instruction 2 nd instruction word register, to an instruction l1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2Instruction word register of which2Is the number of instruction words after the second length instruction is grouped by word.
Preferably, the first length instruction and the second length instruction identify the instruction type by a bit segment S in the instruction. If the bit segment for identifying the instruction type is the highest bit of the instruction, the instruction register is numbered as 1, 2, the1And storing the first length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2An instruction word register. If the bit segment for identifying the instruction type is at the lowest bit of the instruction, the instruction register is numbered as 1, 2 from low word to high word in sequence by taking word bit width as a unit1And storing the first length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2An instruction word register.
The instruction word register selects the starting instruction word from the instruction word data according to the 'third bit segment' of the instruction address register, writes the starting instruction word into the 1 st instruction word register, and sequentially writes the following instruction words into the k-th instruction register.
The instruction address register comprises an address register and an instruction address updating logic module. The address register stores the address of the current instruction fetch; the instruction address update logic is to process a memory address of a next instruction fetch. The output of the instruction address updating logic module is connected to the address register; the address register latches the logic level output by the instruction address updating module. The instruction address updating logic generates a new value instruction address according to input instruction word data, the instruction data after error correction and detection, error states and jump information of processor instructions; the instruction fetch address output by the instruction address update logic is latched by the address register.
The instruction address update logic is prioritized processing logic. The priority order of updating the instruction addresses is as follows from high to low: (1) instruction branch jumping; (2) compensating and correcting the instruction address; (3) the instruction address is self-incrementing.
The instruction address compensation correction is used for compensating and correcting the address register after the address is increased. When a correctable error occurs and the error bit is an instruction type identification bit, the instruction address compensation correction logic corrects the increment of the current instruction address back to the address of the correct next instruction fetch.
And (4) compensating and correcting the instruction address, namely, if the instruction type identification bit is judged to be wrong when the instruction address is corrected. The following cases are divided:
judging the first length instruction into a second length instruction due to the error of the instruction type identification bit, wherein the compensation increment of the instruction address is positive compensation;
and judging the second length instruction into the first length instruction due to the error of the instruction type identification bit, wherein the compensation increment of the instruction address is negative compensation.
The instruction address is incremented by an integer multiple of the word bit width of the first length instruction and the second length instruction as the increment of the instruction address.
The instruction address register is sequentially divided into three parts from high order to low order: a first bit segment; a second bit segment; and a third bit segment. And the first bit segment is matched with the base address identifier of each instruction cache block of the first instruction memory, and whether the current access instruction is in the first instruction memory is judged. If the instruction accessed by the instruction address is not in the first instruction memory, the second instruction memory needs to be accessed by the first bit section, and the instruction word block pointed by the first bit section of the address is written into the first instruction memory. The second bit segment is used for selecting the L pointed by the second bit segment of the address from the matched instruction cache block under the condition that the first bit segment is matched1A bit instruction word and corresponding check bits. The third field is for data from the instruction word,/1One starting instruction word is selected from the instruction words to be written into an instruction word register 1, and other instruction words are sequentially written into an instruction word register 22,., instruction word register l1In (1).
Specifically, as shown in fig. 3, the fault-tolerant apparatus for hierarchical instruction storage capable of active write-back according to the present invention includes: hierarchical instruction memory 310, instruction error correction and detection module 330, instruction word register 340, and instruction address register 320. Hierarchical instruction memory 310 selects output instruction word data 350 from instruction address register 320 and couples the output to instruction error correction and detection block 330 and instruction address register 320. The instruction error detection and correction module 330 performs error detection and correction on the input instruction word data 350, outputs error detected and corrected instruction word data and an error status 360, and couples the output to the hierarchical instruction memory 310, the instruction word register 340, and the instruction address register 320. The instruction word register 340 selectively arranges instruction words in the instruction word data in the instruction word register according to the input instruction word data 360 to combine instructions supported by the processor. The instruction address register 320 updates the address register 322 based on the input instruction word data 350, the error corrected and detected instruction word data and error status 360, and the processor instruction jump information 321.
In a preferred embodiment of the present invention, the processor instruction set includes 64-bit instructions and 32-bit instructions. 64-bit instructions and 32-bit instructions are stored mixed in memory. The device distinguishes the instruction type according to the instruction word data, writes the instruction word combination into the instruction word register, generates the instruction supported by the processor, and sends the instruction to the processor decoding unit.
Wherein, the hierarchical instruction memory 310 in the implementation example comprises a first instruction memory and a second instruction memory, and combines the instruction word data output by the hierarchical instruction memory into the instruction supported by the processor and writes the instruction word data into the instruction word register. The output of the first instruction memory is connected to the instruction word data output 350 of the hierarchical instruction memory; the inputs of the first instruction memory are connected to the inputs of the hierarchical instruction memory, i.e. the error check and correction instruction word data output by the instruction error check and correction module, the error status 360 and the instruction address register 320. The first instruction memory selects and outputs instruction word data according to the content of the instruction address register. And when the instruction word error state is identified as that the data correctable error occurs, writing the instruction word data after error correction and detection back to the first instruction memory. The first instruction memory and the second instruction memory are connected by buses 312 and 311; the instruction word data stored in the second instruction memory is loaded to the first instruction memory via bus 312; the instruction word data stored in the first instruction memory is written back to the second instruction memory via the bus 311. Wherein the instruction word data comprises an instruction word and a check bit of the instruction word. Buses 312 and 311 include control signals and data buses for first and second instruction memory accesses.
In a preferred embodiment, hierarchical instruction memory 310 stores instructions of different lengths within an instruction set, including a first length instruction of length L1 and a second length instruction of length L2, the length of the first length instruction being greater than the length of the second length instruction. The first length instructions and the second length instructions are aligned for storage in a mixed manner in a first instruction memory and a second instruction memory of the hierarchical instruction memory. In the preferred embodiment, the first length instructions and the second length instructions are distinguished by an instruction bit field S as shown in FIG. 4. Where S is located at the most significant bit of the instruction. In a preferred embodiment, the first length instruction is a 64-bit instruction; the second length instruction is a 32-bit instruction. The S bit of the 64/32 bit instruction occupies one bit, being the highest order bit of the instruction. S ═ 0' represents a 32-bit instruction; s ═ 1', indicates a 64-bit instruction.
In an embodiment, the first instruction memory includes two groups of instruction cache units with a capacity of 16 and a bit width of 64 bits, respectively, and a check word cache unit corresponding to the instruction cache. And the two groups of cache units are used for realizing ping-pong access of the instruction blocks. The instruction cache unit takes 32-bit words as unit bit width and is spliced by 2 memory banks. The data bus bit width of the instruction cache unit is spliced by the data buses of the two memories, 64 bits are obtained in total, and at least 1 64-bit instruction or 2 32-bit instructions are output each time. Each instruction cache bank has a corresponding check word bank as a check bit in words. The bit width of the check word memory bank is determined according to the width of the instruction check bit.
Further, the second instruction memory includes at least one bulk instruction memory and a check word memory. The instruction memory stores instructions in units of words. The second instruction memory writes instruction word data to the first instruction memory. And the first instruction memory writes the instruction word data in the selected instruction cache block and check word cache block for storing the input instruction word data of the second instruction memory back to the second memory before receiving the instruction word data written in the second instruction memory. In the preferred embodiment, the second instruction memory is 64KB SRAM memory and is spliced in parallel by 4 blocks of 16KB memory, so that the data bandwidth of instruction access is increased, and the delay of data reading and writing between the second instruction memory and the first instruction memory is reduced. The second instruction memory further comprises a check word memory. The structure of the check word memory is the same as the structure of the instruction memory. The bit width of the check word memory is determined by the check word bit width of the instruction.
In the preferred embodiment shown in FIG. 5, 64-bit instructions and 32-bit instructions are stored in a mixed-aligned manner in the instruction memory of the second instruction memory. Preferably, the type identification bit of the instruction is positioned at the highest bit of the instruction, the 32-bit instruction is continuously stored in the memory by word unit, and the 64-bit instruction is stored in even address alignment. Meanwhile, for a 64-bit instruction, the high order word of the instruction is stored at the low address and the low order word of the instruction is stored at the high address. If the current address is an odd address and a 64-bit instruction 520 is to be stored, the odd address is filled with a "no operation instruction 510" and the even address is stored with the 64-bit instruction 520.
The 64-bit instruction and the 32-bit instruction are stored in the first instruction memory in a mode that the instructions are organized into 64-bit wide data according to the sequence of storage in the second instruction memory by taking a word as a unit and are stored in an instruction cache block of the first instruction memory.
The address register of instruction address register 320, which in an embodiment, has 14 bits, may address the 64KB address space of the second instruction memory. The high order is divided into three parts from the high order to the low order: a first bit segment (bits 5 to 14); a second bit segment (1 st to 4 th bits); the third bit segment (bit 0). The first bit segment (5-14 bits) is matched with the base address identifier of each instruction cache block of the first instruction memory, and whether the current access instruction is in the first instruction memory is judged. The second bit field is used to select the 64-bit instruction word and corresponding check bits to which the second bit field of the address points from the matching 16 x 64-bit instruction cache block if the first bit field matches. The third field is used to select an instruction word from the 2 instruction words of the instruction word data to write into the instruction word register.
In the preferred embodiment, the first instruction memory outputs the bit width L according to the current instruction address of the instruction address register1Is an instruction word of 64, and outputs a check word corresponding to the instruction word. The first instruction memory judges whether the instruction word data accessed by the current instruction address is in an instruction cache unit of the first instruction memory according to the first bit segment of the instruction address register. If the accessed instruction word is in the instruction cache unit, outputting the accessed instruction word and the corresponding check word from an instruction word data output end; if the accessed instruction is not in the instruction cache unit, waiting for writing an instruction word block with the capacity Q of 16 and the bit width of 64 times of the first length instruction bit width from the second instruction memory into the instruction cache unit of the first instruction memory, and then judging that the accessed instruction is already in the instruction cache of the first instruction memory again; and if the accessed instruction word is in the instruction cache unit, outputting the accessed instruction word and the corresponding check word from the instruction word data output end. And writing the instruction word into an instruction cache unit of the first instruction memory, and simultaneously writing the check word corresponding to the instruction word into a check word cache unit.
The first instruction memory also writes back the instruction that has been read out and subjected to the instruction error correction and detection processing into the instruction and check word cache block of the first instruction memory, at the same time as the instruction word data is read out from the first instruction memory. And if the input instruction word data error state after error correction and detection is identified as the instruction word data error correctable, writing the instruction word data back to the instruction cache unit in the first instruction memory. Wherein, the 64-bit wide instruction words are written into one line of the instruction cache unit in sequence. The check words are written into a row of the check word cache unit in sequence.
An instruction cache unit of the first instruction memory includes a status register for identifying an error status of the cache unit. The state register is initially 'error-free', and then the corresponding instruction cache unit is updated according to the error state of the input instruction word data after error correction and detection. When the input instruction word data has correctable errors, updating the status register to a 'correctable errors' status; when the input instruction word data has an uncorrectable error, the status register is updated to an "uncorrectable error" status. In the preferred embodiment, the status register is initially "error free". If the state identification of the instruction word data is judged to be 'no error', the instruction word data is not written back to the instruction word cache unit and the check word cache unit, and the state register is kept; if the status identifier of the instruction word data is judged to have correctable errors, the instruction word data is written back to the instruction word cache unit and the check word cache unit, and the status register is set to be in a 'correctable error' status; if the state identification of the instruction word data is judged to be that no error occurs or a multi-bit uncorrectable error of the data occurs, the instruction word data is not written back to the instruction word cache unit and the check word cache unit, and the state register is set to be in an uncorrectable error state.
In the hierarchical instruction memory, stored instruction word data is exchanged between a first instruction memory and a second instruction memory by instruction word blocks. The size of the instruction block is determined by the size of the instruction and check word cache blocks.
And the second instruction memory accesses the instruction word block in the second instruction memory according to the first bit segment of the instruction address register as the base address of the instruction word block when the instruction word data are loaded to the first instruction memory, sequentially writes the accessed instruction word block into the first instruction memory, and simultaneously writes the check data block corresponding to the instruction word block into the check word cache unit corresponding to the instruction cache unit. The instruction word block of the second instruction memory is sequentially adjusted to 64-bit wide data to be written in the instruction cache block of the first instruction memory.
When writing instruction word data into the first instruction memory in the second instruction memory, if the instruction word data is already written into the instruction cache block and the check word cache block in the selected first instruction memory, writing the instruction word data in the selected instruction cache block and the check word cache block into the second instruction memory according to the original base address of the instruction word data in the second instruction memory by the first instruction memory according to the error state of the selected instruction cache block; then, the second instruction memory writes the instruction word data into the first instruction memory. The first instruction memory disassembles the 64-bit wide instruction word block in the instruction cache block into instruction data in word bit unit in sequence and writes the instruction data back to the second instruction memory.
And the instruction word error correction and detection module is used for performing error correction and detection on the instruction word data output by the hierarchical instruction memory according to the word unit. Under the condition that the instruction word has no error, the data is normally output; under the condition that correctable errors occur in the instruction words, outputting corrected data, and positioning a correctable error state; in the event of an uncorrectable error in the instruction word, the error data is output and an uncorrectable error state is set.
In an implementation example, the error detection and correction module comprises 2 groups of word-by-word parallel error detection and correction modules, and detects and corrects the error of 64-bit instruction word data output by the hierarchical instruction memory. The instruction word error correction and detection logic uses the odd weight check bit and the check bit to generate a structure of a logic shortest path, performs error correction and detection on two 32-bit instruction words, corrects any one-bit data error in the 32-bit instruction words, and detects two-bit data errors. The error correction and detection logic for generating the shortest logic path by odd weight check bit and check bit uses 32 bit data bits
D＝d32d31…d4d3d2d1, (di,{1≤i≤32}＝{0,1})
And 8-bit check bit P '═ P'8p'7p'6p'5p'4p'3p'2p′1 (p′i,{1≤i≤8}＝{0,1})
Generating an 8-bit error identification bit P ═ P8p7p6p5p4p3p2p1 (pi,{1≤i≤8}＝{0,1})
The logic for generating the identification bits is:
Figure BDA0001481893320000171
wherein the content of the first and second substances,
Figure BDA0001481893320000172
is an exclusive or operation; order to
Figure BDA0001481893320000173
The method for error correction and detection according to the P value is as follows:
(1) if P is "000000, 0" indicates that the data and the check code are Error-free, Multiple _ Error is false, Single _ Error is false;
(2) if weight is '0' and p8p7p6p5p4p3p2p1Not equal to "0000000", indicating that two bits of the data D or the check code P' have errors, Multiple _ Error ═ true; the data or the check code is not corrected;
(3) if weight is 1' and p8p7p6p5p4p3p2p1Not equal to "0000000", indicating that an Error occurs in one bit of the data D or the check code P', Single _ Error ═ true; the method for correcting the data bit error comprises the following steps:
Figure BDA0001481893320000174
d′ii is more than or equal to 1 and less than or equal to 32 as a data bit diSingle error corrected data bits; "·" is a bitwise AND operation, KiThe calculation method of (2) is as follows:
Figure BDA0001481893320000181
the method for correcting the single error of the check bit comprises the following steps:
if p isiNot equal to '0', (1. ltoreq. i.ltoreq.8), and
Figure BDA0001481893320000182
then p'jThe occurrence of a single error is obvious,
Figure BDA0001481893320000183
wherein, p 'at the right end of equation'jJ is more than or equal to 1 and less than or equal to 8, which is the result after the single error correction of the check bit; p 'of the left end of equation'jJ is more than or equal to 1 and less than or equal to 8 and is a numerical value before single error correction of the check bit.
In the preferred embodiment, the instruction word register 340 comprises 2 instruction word registers that are 32 bits wide and can store at least one 64-bit instruction. The instruction word registers include instruction word register 1 and instruction word register 2 in the preferred embodiment, the type identification field S of the 64/32 bit instruction is located at the highest order bit of the instruction, so the high word of the 64 bit instruction is stored in instruction word register 1 and the low word is stored in instruction register 2; the 32-bit instruction is held in instruction register 1.
The instruction word data input by the instruction word register is a row of instruction words in an instruction cache block of a first instruction memory passing through the instruction word error detection and correction module. The bit width of the instruction word is 64 bits. And the instruction word register selects a starting instruction word of the instruction according to the third bit segment of the instruction address register corresponding to the current instruction word. In a preferred embodiment, the third bit segment of the instruction address register is bit 0 PC0If PC0Selecting the lower 32-bit word of the 64-bit instruction word as a starting instruction word of the instruction; if PC0The upper 32-bit word of the 64-bit instruction word is selected as the start instruction word of the instruction, 1. The start instruction word is written into the instruction word register 1, the identification bit segment S of the instruction is stored in the start instruction word. In the preferred embodiment, the bit segment S is located at bit 32I of the start instruction word31. If I31When the instruction is a 32-bit instruction, the instruction register 2 does not need to be updated; if I31The command is a 64-bit command, and it is necessary to write a command word after the start of a command word in the command word data into the command register 2. Since in the preferred embodiment of the present invention 64-bit instructions are aligned at even addresses in memory, when I is31When 1, PC0When the start instruction word is 0, the lower 32-bit word of the 64-bit instruction word data is used as the start instruction word, and the upper 32-bit word of the 64-bit instruction word data is used as the instruction word following the start instruction word. The apparatus of the present invention writes the upper 32-bit word into instruction word register 2. at this time, instruction word register 1 and instruction register 2 hold a 64-bit instruction. After the instructions are combined, the instruction register is sent to a decoding unit of the processor to process the decoding of the instructions.
As shown in FIG. 3, the instruction address register (320) includes an address register (322) and an instruction address update logic block (323). An address register (322) holds the instruction fetch address of the current instruction; instruction address update logic (323) handles the memory address of the next instruction to fetch. The instruction address updating logic generates a new value instruction address according to input instruction word data (350), the instruction data after error correction and detection and an error state (360) and jump information (321) of a processor instruction; the instruction fetch address generated by the instruction address update logic is latched by an address register (320). The priority order of the three logical branches updated for instruction addresses is, from high to low: (1) instruction branch jumping; (2) compensating and correcting the instruction address; (3) the instruction address is self-incrementing.
Due to the pipelined execution of the processor, in a machine cycle after the instruction address register increments, if a correctable error is detected in the instruction type flag of the previously read instruction word data, the current instruction address needs to be corrected to correctly fetch the next instruction. At the same time, the fetched instruction word data also needs to be flushed from the pipeline due to erroneous address self-growth.
And instruction address compensation correction is used for performing compensation correction on the address register after the address is increased. When a correctable error occurs and the error bit is an instruction type identification bit, the instruction address compensation correction logic corrects the increment of the current instruction address back to the address of the correct next instruction fetch.
In an embodiment of the present invention, when the instruction address compensation correction logic corrects the instruction address, if the instruction type identification bit is determined to have a correctable error. The following cases are divided:
if error correction and detection is performed before I311', error corrected and checked I31When the instruction length is equal to '0', the instruction length of 32 bits is misjudged to be 64 bits, and the instruction address needs to be compensated by-1;
if error correction and detection is performed before I310', error corrected and checked I31If the instruction length is equal to '1', the instruction length of 64 bits is misjudged to be 32 bits, and +1 compensation needs to be carried out on the instruction address;
if before or after error correction and detection I31The state is the same, and compensation correction is not carried out on the instruction address.
When calculating the instruction address self-increment and the correction quantity, the increment is calculated by taking the minimum unit which can be accessed by the instruction as an address boundary. For example, the minimum access unit of a 64-bit instruction and a 32-bit instruction is a 32-bit word, and a word is taken as the minimum calculation unit of address change; if a 32-bit instruction and a 16-bit child are included in the instruction set, 16-bit instruction data is used as the minimum count unit of address change.
As shown in fig. 6, the present invention is a fault tolerant method for active write-back hierarchical storage structure, which includes the following processing steps:
step 1, starting a processor to operate;
step 2, according to the address in the present instruction address register, fetch the instruction word data from the hierarchical instruction memory;
step 3, the instruction word data is sent to an instruction error correction and detection module to carry out error correction and detection judgment;
and 4, judging whether the error correction and detection result has no error or has correctable error. If yes, continuing to step 5; otherwise, turning to step 10;
step 5, writing the instruction into an instruction word register;
step 6, updating an instruction address register;
and 7, judging whether a correctable error occurs or not. If yes, continuing to step 8; otherwise, turning to step 9;
step 8, writing the instruction word data back to the hierarchical instruction memory;
and 9, finishing the current processing. Turning to step 2, processing the next instruction address;
step 10, an uncorrectable multi-bit error occurs to the instruction word data, a multi-bit interrupt is sent out, and the processor is suspended;
in step 3, the instruction word and the check bit in the instruction word data are subjected to error correction and detection of the instruction by using the 32-bit instruction word as a unit. The instruction word error correction and detection is a structure of generating a logic shortest path by odd weight check and check bits.
As shown in fig. 7, the method for fetching instruction word data from the hierarchical instruction memory in step 2 is illustrated as follows:
step 2-1: an instruction word cache block of the instruction fetch is matched to be in the first instruction memory according to a first bit segment of an instruction address register. If yes, turning to the step 2-3; otherwise, continuing the step 2-2;
step 2-2: and reading an instruction word block addressed by a first bit field of the instruction address register from the second instruction memory, and writing the instruction word block into the first instruction memory. Turning to step 2-1;
step 2-3: and in the matched instruction word cache block, addressing according to a second bit segment of the instruction address register, selecting a row of instruction words in the instruction word cache block to output, and simultaneously selecting a check word corresponding to the instruction word to output as instruction word data.
Further, as shown in fig. 8, it is illustrated that step 2-2 further comprises the following steps:
step 2-2-1, selecting one instruction cache block from the instruction cache blocks of the first instruction memory as an instruction cache block to be written in;
and 2-2-2, judging whether the instruction word block is stored in the current instruction cache block. If yes, continuing the step 2-2-3; otherwise, turning to the step 2-2-5;
and 2-2-3, judging whether the error state of the selected instruction cache block has an uncorrectable error or not. If yes, 2-2-7 is rotated; otherwise, continuing the step 2-2-4;
step 2-2-4, according to the instruction word block base address of the selected instruction cache block in the second instruction memory, writing the instruction word in the selected instruction cache block and the corresponding check word into the second instruction memory;
step 2-2-5, according to the first bit segment of the current instruction address register, addressing in the second instruction memory according to the first bit segment, reading the addressed instruction word block from the second instruction memory, writing the addressed instruction word block into the selected instruction cache block in the first instruction memory, and writing the first bit segment of the corresponding instruction address register into the base address register of the instruction cache block; reading the check bits corresponding to the instruction word block from the second instruction memory, and writing the check bits into the check word cache block corresponding to the instruction cache block;
and 2-2-6, identifying the state register of the selected instruction cache block as error-free.
And 2-2-7, finishing the treatment.
In step 2-2-3, when an uncorrectable error of instruction word data occurs, an uncorrectable error signal is output by the instruction error correction and detection module and is connected to the interrupt process 390 of the main processor.
In the preferred embodiment shown in fig. 9, the method for writing the error-corrected instruction word data back to the hierarchical instruction memory in step 8 is as follows:
step 8-1: matching all instruction cache blocks of a first instruction memory according to a first bit section of an instruction address register corresponding to the current error-corrected instruction word data;
step 8-2: and in the matched instruction cache block, addressing the instruction cache block according to the second bit segment of the instruction address, and writing the error-corrected instruction word data back to the matched instruction cache block.
And writing the error-corrected instruction word data back to the second instruction memory from the first instruction memory according to the unit of the instruction word block, and processing the error-corrected instruction word data by the steps 2-2-1 to 2-2-7 of the step 2-2.
And writing the instruction word data back to the second instruction memory from the first instruction memory, and processing by the steps 2-2-1 to 2-2-7 when no instruction word data error occurs according to the instruction word block as a unit.
As shown in FIG. 10, the fault-tolerant device of the hierarchical instruction memory capable of active write-back of the present invention is divided into three machine cycles in the processor. FIG. 10 illustrates the manner in which four instructions are pipelined in a processor. Only the pipeline of fault-tolerant processing of instructions in a processor pipeline is shown in fig. 10. The fault tolerance apparatus of the present invention is divided into three machine cycles in the processor for processing and execution, which correspond to the devices 1, 2 and 3 in fig. 10.
The operational process in the first processor cycle (device 1) is:
(1) instruction address register update;
the operational process in the second machine processor cycle (device 2) is:
(1) accessing instruction word data from a hierarchical memory according to an instruction address register;
(2) sending the instruction word data to an instruction error correction and detection module;
(3) generating an instruction address self-increment;
the operation process in the third machine processor cycle (device 3) is:
(1) updating the instruction word register;
(2) generating a command address compensation modifier.
The apparatus and method of the present invention may also be used for 31-bit and 16-bit instructions; 16-bit and 8-bit instructions, and the like.
The above description is provided for further details of the present invention, and it should not be considered that the present invention is limited to the above embodiments, and it should be understood by those skilled in the art of digital integrated circuit design that the present invention belongs to the claims of the present invention without departing from the spirit of the present invention.

Claims (10)

1. The fault-tolerant device of the hierarchical instruction memory structure capable of actively writing back is characterized in that: the system comprises a hierarchical instruction memory, an instruction error correction and detection module, an instruction word register and an instruction address register;
the input end of the hierarchical instruction memory is connected with the output end of the instruction address register, the instruction word data is selected to be output according to the instruction address stored in the input instruction address register, and the output instruction word data is connected to the instruction error correction and detection block and the instruction address register; the input end of the hierarchical instruction memory is also connected with the output end of the instruction error detection and correction module, and the hierarchical instruction memory is refreshed after the hierarchical instruction memory is written back according to the instruction word data after error detection and correction output by the instruction error detection and correction module;
the input end of the instruction error correction module is connected with the output end of the hierarchical instruction memory, receives instruction word data output by the hierarchical instruction memory, performs error correction and detection on the instruction word data, outputs the instruction word data after error correction and detection and an error state, and the output end of the instruction error correction and detection module is respectively connected with the input ends of the hierarchical instruction memory, the instruction word register and the instruction address register;
the instruction word register receives the instruction word data after error correction and detection output by the instruction error correction and detection module, selectively arranges the instruction word data after error correction and detection in the instruction register, and combines instructions supported by the processor;
the input end of the instruction address register respectively receives instruction word data output by the hierarchical instruction memory, error correction and detection instruction word data and error states output by the instruction error correction and detection module, and jump information of processor instructions; the output end outputs the current instruction address temporarily stored in the instruction address register;
the instruction word data includes an instruction word and a check bit of the instruction word.
2. The fault tolerant device of an active writeback hierarchical instruction memory structure of claim 1, wherein: the instruction address register comprises an address register and an instruction address updating logic module; the address register stores the address of the current instruction; the instruction address updating logic module is used for processing the memory address of the next instruction; the address output by the instruction address updating logic module is connected to the address register; the address register latches the logic level output by the instruction address updating module; the instruction address updating logic module generates a new instruction address according to the input instruction word data, the error correction and detection instruction word data and the error state and the jump information of the processor instruction; the address register latches the instruction address output by the instruction address updating logic module;
the instruction address register is sequentially divided into three parts from high order to low order: a first address bit segment, a second address bit segment and a third address bit segment; the first bit segment of the address is matched with the base address identifier of each instruction cache block of the first instruction memory, and whether the current access instruction is in the first instruction memory is judged; if the instruction accessed by the instruction address register is not in the first instruction memory, the second instruction memory needs to be accessed by the first bit segment, and the instruction word block pointed by the first bit segment of the address is written into the first instruction memory; the second address bit segment is used for selecting the instruction word and the corresponding check bit pointed by the second address bit segment from the matched instruction cache block under the condition that the first bit segment is matched; the third bit field of the address is used for selecting a starting instruction word from all instruction words of the instruction word data to write into the first instruction word register, and other instruction words are sequentially written into the corresponding instruction word registers.
3. The fault tolerant device of an active writeback hierarchical instruction memory structure of claim 2, wherein: the hierarchical instruction memory is used for storing processor instruction words with different lengths, and the processor instruction words comprise lengths L distinguished by instruction identification bit sections S1Is a first length instruction and has a length of L2A second length instruction of (1); the length of the first length instruction is greater than that of the second length instruction; the first length instructions and the second length instructions are stored aligned in a mixed manner in the hierarchical instruction memory;
the hierarchical instruction memory comprises a first instruction memory and a second instruction memory which are interactive; wherein, the output end of the first instruction memory is connected to the instruction word data output end of the hierarchical instruction memory; the input end of the first instruction memory is connected to the input end of the hierarchical instruction memory, and the input end of the first instruction memory is also connected with instruction word data after error correction and detection, an error state and an instruction address register which are output by the instruction error correction and detection module;
the first instruction memory selects and outputs instruction word data according to the address of the instruction address register, and when the error state of the instruction word is identified as that a correctable error of data occurs, the instruction word data after error correction and detection is written back to the first instruction memory; the first instruction memory and the second instruction memory are connected through a data exchange bus, instruction word data stored in the second instruction memory are input into the first instruction memory, and instruction word data stored in the first instruction memory are written back to the second instruction memory; the stored instruction word data is exchanged between the first instruction memory and the second instruction memory in instruction word blocks.
4. The fault tolerant device of an active writeback hierarchical instruction memory structure of claim 3, wherein: the first instruction memory comprises at least one group of instruction bits L with a first length1The instruction cache unit and the check word cache unit; the first instruction memory outputs L bit width according to the current instruction address of the instruction address register1The check word corresponding to the instruction word is output at the same time;
the first instruction memory judges whether the instruction word data accessed by the current instruction address register is in an instruction cache unit of the first instruction memory according to the first bit segment of the instruction address register; if the accessed instruction is not in the instruction cache unit, waiting for writing the instruction cache unit of the first instruction memory from the second instruction memory with the capacity of Q and the bit width of the instruction cache unit of the first length1After the instruction word with the size is processed, judging the accessed instruction word to be in an instruction cache unit of the first instruction memory again; if the accessed instruction word is in the instruction cache unit, outputting the accessed instruction word and the corresponding check word from an instruction word data output end;
the first instruction memory receives the instruction word data after error correction and detection and writes the instruction word data after error correction and detection back to the hierarchical instruction memory; if the error state of the input instruction word data is identified as correctable error of the instruction word data, writing the instruction word data back to an instruction cache unit in the first instruction memory;
the second instruction memory writes instruction word data into the first instruction memory; the first instruction memory writes the instruction word data in the selected instruction cache block and check word cache block for storing the input instruction word data of the second instruction memory back to the second memory before receiving the instruction word data written in the second instruction memory;
the second instruction memory stores the first length instruction and the second length instruction in a way that if the type identification bits of the first length instruction and the second length instruction are positioned at the highest position of the instruction, the instruction stores the high position at a low position address according to a word unit, and the low position at the high position address; if the type identification bits of the first length instruction and the second length instruction are on the lowest order bits of the instruction, the instruction stores the high order bits in a high order address and the low order bits in a low order address in units of words, wherein the words are maximum common denominators of the first length instruction and the second length instruction.
5. The fault tolerant device of an active writeback hierarchical instruction memory structure of claim 3, wherein: when the second instruction memory writes instruction word data into the first instruction memory, if the instruction word data are written into the instruction cache block and the check word cache block in the selected first instruction memory, the first instruction memory writes the instruction word data in the selected instruction cache block and the check word cache block back to the second instruction memory according to the original base address of the instruction word data in the second instruction memory; then, writing instruction word data into the first instruction memory by the second instruction memory; the first instruction memory stores L in the instruction cache block1The instruction word block with bit width is disassembled into instruction word data with word as unit and written back to the second instruction memory.
6. The fault tolerant device of an active writeback hierarchical instruction memory structure of claim 2, wherein: the processing logic of the instruction address updating logic module is provided with a priority sequence, and the priority sequence for updating the instruction address is as follows from high to low: instruction branch jumping, instruction address compensation correction and instruction address self-increment;
the instruction address compensation correction is used for compensating and correcting the self-increased address register; when a correctable error occurs and the error bit is an instruction type identification bit, the instruction address compensation correction logic corrects the increment of the current instruction address back to the address of the correct next instruction;
when the instruction address is corrected, if the instruction type identification bit is judged to be wrong,
when the first length instruction is judged to be the second length instruction, the compensation increment of the instruction address is positive compensation;
when the second length instruction is judged to be the first length instruction, the compensation increment of the instruction address is negative compensation.
7. The fault tolerant device of an active writeback hierarchical instruction memory structure of claim 2, wherein: the instruction word registers include a set of registers capable of storing at least instructions of a first length, including a 1 st instruction word register, a 2 nd instruction word register, … …, an l1An instruction word register;
the first length instruction and the second length instruction identify the instruction type through a bit segment S in the instruction;
if the bit segment for identifying the instruction type is the highest bit of the instruction, the instruction register is numbered as 1, 2, … …, l in sequence from high word to low word according to the instruction length type by taking the bit width of the word as a unit1And storing the first length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2An instruction word register;
if the bit segment for identifying the instruction type is at the lowest order of the instruction, the instruction register is numbered 1, 2, … …, l in sequence from the low word to the high word according to the instruction length type by taking the bit width of the word as a unit1And holding the first length instructionThere is an instruction word 1 register, an instruction word 2 register, to1An instruction word register; saving the second length instruction in the 1 st instruction word register, the 2 nd instruction word register, to the l2An instruction word register;
wherein l1Is the number of instruction words after the first length instructions are grouped by word, l2The number of instruction words after the instructions with the second length are grouped according to words, the instruction word register selects the starting instruction word from the instruction word data according to the third bit segment of the instruction address register, the starting instruction word is written into the 1 st instruction word register, the subsequent instruction words are sequentially written into the k th instruction register, and k is 1, 2, … …, l arbitrarily1。
8. The fault-tolerant method of the hierarchical instruction storage structure capable of being written back actively is characterized by comprising the following steps:
step 1, starting a processor to operate;
step 2, according to the address in the present instruction address register, fetch the instruction word data from the hierarchical instruction memory;
step 3, the instruction word data is sent to an instruction error correction and detection module to carry out error correction and detection judgment;
step 4, judging whether the error correction and detection result is error-free or error-correctable; if yes, continuing to step 5; otherwise, turning to step 10;
step 5, writing the instruction word into an instruction word register;
step 6, updating an instruction address register;
step 7, judging whether a correctable error occurs or not; if yes, continuing to step 8; otherwise, turning to step 9;
step 8, writing the instruction word data back to the hierarchical instruction memory;
step 9, finishing the current processing; turning to step 2, processing the next instruction address;
and 10, sending an uncorrectable error interrupt when the instruction word data generates an uncorrectable error, and suspending the processor.
9. The fault tolerant method of claim 8, wherein in step 2, the method for fetching instruction word data from the hierarchical instruction memory is:
step 2-1: whether an instruction cache block accessed by an instruction address is matched in a first instruction memory or not is judged according to the first bit section of the address of the instruction address register; if yes, turning to the step 2-3; otherwise, continuing the step 2-2;
step 2-2: reading an instruction word block addressed by a first bit field of an address of an instruction address register from a second instruction memory, and writing the instruction word block into a first instruction memory; turning to step 2-1;
step 2-3: and in the matched instruction word cache block, addressing according to the second bit segment of the address of the instruction address register, selecting a row of instruction words in the instruction cache block to output, and simultaneously selecting check words corresponding to the instruction words to output as instruction word data.
10. The fault tolerant method of active writeback hierarchical instruction storage structure of claim 9 wherein said step 2-2 further comprises the steps of:
step 2-2-1, selecting one instruction cache block from the instruction cache blocks of the first instruction memory as an instruction cache block to be written in;
step 2-2-2, judging whether the instruction word block is stored in the current instruction cache block; if yes, continuing the step 2-2-3; otherwise, turning to the step 2-2-5;
step 2-2-3, judging whether the error state of the selected instruction cache block has an uncorrectable error; if so, outputting an uncorrectable error signal by the instruction error correction and detection module, connecting the uncorrectable error signal to an interrupt processing module of the main processor, and turning to 2-2-7; otherwise, continuing the step 2-2-4;
step 2-2-4, according to the instruction word block base address of the selected instruction cache block in the second instruction memory, writing the instruction word in the selected instruction cache block and the corresponding check word into the second instruction memory;
step 2-2-5, according to the first bit segment of the current instruction address register, addressing in the second instruction memory according to the first bit segment, reading the addressed instruction word block from the second instruction memory, writing the addressed instruction word block into the selected instruction cache block in the first instruction memory, and writing the first bit segment of the corresponding instruction address register into the base address register of the instruction cache block; reading the check bits corresponding to the instruction word block from the second instruction memory, and writing the check bits into the check word cache block corresponding to the instruction cache block;
step 2-2-6, marking the status register of the selected instruction cache block as error-free;
step 2-2-7, finishing the treatment;
when the instruction word data without errors or the instruction word data after error correction is written back from the first instruction memory to the second instruction memory by taking the instruction word block as a unit, the instruction word data are processed by the steps 2-2-1 to 2-2-7.
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