CN1627499A - 在半导体装置中制造电容器的方法 - Google Patents

在半导体装置中制造电容器的方法 Download PDF

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CN1627499A
CN1627499A CNA2004100626261A CN200410062626A CN1627499A CN 1627499 A CN1627499 A CN 1627499A CN A2004100626261 A CNA2004100626261 A CN A2004100626261A CN 200410062626 A CN200410062626 A CN 200410062626A CN 1627499 A CN1627499 A CN 1627499A
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dielectric layer
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source gas
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bottom electrode
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李起正
卢载盛
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SK Hynix Inc
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Abstract

本发明涉及通过使用氧化铪(Hf1-xTbxO)作为介电层在一半导体装置中制作电容器的方法。该方法包括下列步骤:在一基底上形成一下电极;在该下电极上形成一非晶体的氧化铪(Hf1-xTbxO)介电层;通过执行一热处理使该氧化铪(Hf1-xTbxO)介电层结晶;且在该氧化铪(Hf1-xTbxO)介电层上形成一上电极。

Description

在半导体装置中制造电容器的方法
技术领域
本发明涉及在一半导体装置中制造电容器的方法;且更具体地,涉及通过使用氧化铪铽(Hf1-xTbxO)在一半导体装置中制造电容器的方法。
背景技术
半导体技术中微粉化方面的最新进展已经导致了加速地获取存储装置的大规模集成。作为结果,单位晶格面积得到减少并且所需要的操作电压变低。尽管单位晶格面积被减少了,但为防止软错误的发生和更新时间被缩短,要求每一晶格所需的电容大于25fF。因此,有了多种手段以获取所需要的电容。例如在一动态随机访问存储器(DRAM)装置中使用的电容器中,其中通过使用二氯甲硅烷(DCS)气体形成的氮化硅(Si3N4)层被用作该电容器的介电层,下电极以三维方式形成,并且采用表面区域比较大的半球的形式;且该电容的高度被增加。
然而,该电容高度的增加引起晶格区域与该周边区域的高度差,并且不利地是,此高度差对在随后的照相曝光处理中的景深的获得带来了困难。因此,要获得存储量超过256MB的下一代DRAM装置所需的电容器的电容量受到限制。
由于此限制,当前电容器的发展已聚焦于通过使用具有高介电常数的介电材料来获得具有足够电容和合适高度的电容器。此介电材料的例子是氧化钽(Ta2O5),其介电常数为25,氧化铪(HfO2),其介电常数在20-30的范围内,以及氧化铝(Al2O3),其介电常数为9。
尽管使用高介电材料,Ta2O5介电层被怀疑可能有电流泄漏,因为Ta2O5介电层会由于在形成了Ta2O5层之后所执行的加热处理而退化。另外,形成具有足够电容的Al2O3介电层也是受到限制的,因为Al2O3与HfO2和Ta2O5
相比,介电常数相对较低。另外,HfO2介电层的击穿电压强度低,由此,其对重复的电介质应力非常敏感。因此具有HfO2介电层的电容器的寿命可能会缩短。
发明内容
因此,本发明的一个目标是提供一种在一半导体装置中制造电容器的方法,其能够提高一介电层的可靠性,并获得一高度集成装置进行操作所需的电容。
根据本发明的一个方面,提供了一种在一半导体装置中制造电容器的方法,包括下列步骤:在一基底上形成一下电极;在该下电极上形成一非晶体的氧化铪铽(Hf1-xTbxO)介电层;通过执行一热处理使该氧化铪铽(Hf1-xTbxO)介电层晶体化;并且在该氧化铪铽(Hf1-xTbxO)介电层上形成一个上电极。
附图说明
参考以下结合附图对优选实施方式进行的描述,可更好地理解本发明上述的以及其他的目标和特性,在附图中:
图1是描述根据本发明第一实施方式的用于制作一圆柱形电容器的方法的截面图;
图2示出通过采用根据本发明第一实施方式的原子层沉积方法形成氧化铪铽(Hf1-xTbxO)层的顺序步骤,其中,下标x表示铽(Tb)的原子比例;
图3是描述根据本发明第二实施方式的形成为洞穴形状的电容器的截面图;
图4是描述根据本发明第三实施方式的形成为内圆柱形电容器的截面图;
具体实施方式
现在结合附图并根据本发明的优选实施方式来描述在一半导体装置中制造电容器的方法。
图1是描述根据本发明第一实施方式的用于制作一圆柱形电容器的方法的截面图;
如图所示,在半成品的基底10上形成由二氧化硅(SiO2)制成的内层绝缘层11。尽管没有示出,上述半成品的基底10通过执行形成装置元件的预定处理被配备有所述多种装置元件,例如晶体管和位线。然后内部绝缘层11被蚀刻以形成接触孔12A,用于暴露基底10的预定部分。将一导电材料沉积到接触孔12A内以及内层绝缘层11上,直到接触孔12A被填满了该导电材料。然后,进行一化学机械抛光(CMP)处理或者深腐蚀处理以形成接触塞12B,用于将一电容器的后续下电极连接到该基底10。
尽管没有示出,在上面形成的基底结构上形成一用于形成电容器的氧化层,并且之后蚀刻该氧化层以形成暴露该接触塞12B的孔。
接着,在该孔和氧化层上形成用于形成一下电极的一金属层或者一多晶硅层。其中,该金属层由选自包括以下材料的组的材料制成:氮化钛(TiN)、钌(Ru)、氮化钽(TaN)、钨(W)、硅化钨(WSi)、氮化钨(WN)、氧化钌(RuO2)、铱(Ir)以及铂(Pt)。随后,对上述金属或者多晶硅层执行CMP处理或者深腐蚀处理。之后,除去氧化层以形成圆柱形的下电极13。
在下电极13是由多晶硅制成的情况下,该下电极13将在形成一介电层14之前进行一清洁处理,目的是去除在下电极13上形成的天然氧化层并且阻止氢气扩散。对于该清洁处理,优选使用水稀释的氢氟酸(HF)或用氢氧化铵(NH4OH)稀释的去离子水(DI)和HF的混合溶液,其中,在水稀释的氢氟酸(HF)中,优选大约1份的HF兑入大约10份到大约200份的水;在后一混合溶液中,一份的HF兑入大约5份到大约500份的NH4OH。
尽管没有示出,在该下电极13上形成一由选自氮化硅家族(SiNx)的材料制成的扩散阻挡层,目的是防止硅或者杂质扩散到随后要形成的介电层中。该扩散阻挡层是通过对下电极13的表面进行氮化而形成的,所述对下电极13的表面进行氮化是通过在氨(NH3)气环境中执行炉内退火处理和快速热处理(RTP)之一来实现的。
另外,在上面的清洁处理之前和之后,可以通过使用以下混合溶液执行一附加的清洁处理:氢氧化铵(NH4OH)、过氧化氢(H2O2)以及水(H2O)的混合溶液,硫酸(H2SO4)和H2O2的混合溶液,或者硫酸(H2SO4)和水的混合溶液来去掉有机或者无机颗粒,或者在由多晶硅制成的下电极13上残留的其他杂质。
然后在该下电极13上形成上述介电层14。此时,介电层14是由氧化铪铽(Hf1-xTbxO)制成的,且厚度小于大约100埃。这里,下标x表示铽(Tb)的原子比例。
更具体地,该Hf1-xTbxO介电层14是通过采用原子层沉积(ALD)方法或者低压化学汽相沉积(LPCVD)方法而形成的。此时,例如C13H36HfO4的材料,或铬(Hf)的前体,例如四羟二乙胺基-铬(TDEAHf)以及四羟乙基甲胺基-铬(TEMAHf)的有机金属化合物,被用作Hf的源气体。对于Tb的源气体,使用例如Tb(OC2H5)3的材料,或者Tb的前体,例如包含Tb的有机金属化合物,例如Tb(CH3)3。另外,反应气选自包括O3,O2等离子气体和水蒸汽的组。
另外,由于Hf1-xTbxO介电层14的介电常数,泄漏电流的等级以及击穿电压特性是由Tb的含量确定的,Tb的原子比例,即下标x被设置在大约0.030到大约0.1的范围内,以使Hf1-xTbxO介电层14的介电常数在大约30到大约50的范围内。也就是说,如果通过控制Tb的含量而形成介电常数在大约30到大约50的范围内的高介电常数的Hf1-xTbxO介电层14,则该介电层就可能具有等效氧化物层的厚度,其范围从大约10埃到大约20埃的。作为此效果的结果,还有可能获得一有足够电容的电容器,使泄漏电流等级低于氧化铪(HfO2)层,并且具有显著的击穿电压特性。另外,由于Hf1-xTbxO介电层14在高温条件下与HfO2层相比具有比较好的温度稳定性,于是在对Hf1-xTbxO介电层14进行高温加热处理以使其晶体化的过程中可能防止电气特性的下降,从而提高了电容器的寿命和可靠性。
优选地,每个Hf和Tb的源气体的流速被控制在从大约50sccm到大约500sccm的范围内。同时,该反应气体的流速被控制在从大约0.1slm到大约1slm的范围内。在O3被用作反应气体的情况下,O3反应气体的浓度被控制在大约220g/m3到大约180g/m3的范围内。
如果Hf1-xTbxO介电层14是通过使用一ALD方法形成的,则重复地执行分别用于形成HfO2层和氧化铽层(TbxOy)的两个循环,其中下标x和y分别表示Tb和O的比例。特别地,用于形成HfO2层的第一循环包括顺序提供Hf源气体,提供例如N2或者Ar的净化气体,提供O3反应气体,以及提供例如N2或者Ar的净化气体的步骤,并且用于形成TbxOy的第二重循环包括顺序提供Tb源气体,提供例如N2或者Ar的净化气体,提供O3反应气体,以及提供如N2或者Ar的净化气体的步骤。特别地,该第一和第二循环分别以小于大约9到大约1的比例而重复。也可以重复执行一个循环,其包括顺序提供Hf源气体,提供N2或者Ar净化气体,提供Tb源气体,提供N2或者Ar净化气体,提供O3反应气体,以及提供N2或者Ar净化气体的步骤。此时,提供Hf源气体的次数以及提供Tb源气体的次数被设置为小于大约9到大约1的比例。
如果采用LPCVD方法形成Hf1-xTbxO介电层14,单独包含Hf和Tb的无机金属化合物被控制为Hf和Tb的比例为小于大约9到大约1,所述控制通过使用一流体控制器,例如一个质量流量控制器(MFC)来进行,然后使用汽化器对其进行汽化,所述汽化器的温度保持在从大约150℃到大约300℃的范围内。之后,这些Hf和Tb源气体被提供到温度范围保持在大约250℃到大约500℃的LPCVD反应室。
然后,通过一热处理使该Hf1-xTbxO介电层1结晶,从而使其具有改进的介电特性。这里,加热处理是炉内退火处理以及快速热处理(RTP)中的一种,并且在增加或者减少压力的情况下,在从大约500℃到大约900℃的温度范围内,进行此处理的气体环境是N2,或者O2和N2的混合比例小于大约1到大约10的混合气体。特别地,执行此加热处理的目的是去掉包含在Hf1-xTbxO介电层中的碳杂质。
然后,通过使用选自包括TiN,Ru,TaN,W,WSi,WN,RuO2,Ir,IrO2以及Pt的组的金属层或者通过使用一多晶硅层在Hf1-xTbxO介电层14上形成上电极15。
尽管没有示出,在上电极15是由多晶硅制成的情况下,在上电极15和Hf1-xTbxO介电层14之间形成由选自SiNx家族的氮基材料制成的扩散阻挡层。该扩散阻挡层是通过使用与应用于氮化下电极13相同的方法来氮化Hf1-xTbxO介电层14而形成的。另外,尽管没有示出,在上电极15上形成一缓冲层,目的是保持结构相对于湿度、温度或者电击的稳定性。此时,该缓冲层是由多晶硅或者氮化硅制成的,并且其具有的厚度范围是从大约200埃到大约1000埃。
图2示出了根据本发明第一实施方式的用于形成铪-铽氧化物(Hf1-xTbxO)层的ALD方法的循环,其中,下标x表示Tb的原子比例。如图所示,每个循环包括顺序提供源气体、净化气体、反应气体以及净化气体的步骤。更具体地,如上所述,Hf1-xTbxO介电层14是通过重复地分别执行用于形成HfO2层和氧化铽(TbxOy)层的两个循环而形成的。其中下标x和y分别表示Tb和O的原子比例。用于形成HfO2层的第一循环包括顺序提供Hf源气体、提供例如N2或者Ar的净化气体、提供O3反应气体以及提供例如N2或者Ar的净化气体的步骤,并且用于形成TbxOy的第二循环包括顺序提供Tb源气体、提供例如N2或者Ar的净化气体、提供O3反应气体,以及提供例如N2或者Ar的净化气体的步骤。
特别地,该第一和第二循环分别以小于大约9到大约1的比例而重复。也可以重复执行一个循环,其包括顺序提供Hf源气体、提供N2或者Ar净化气体、提供Tb源气体、提供N2或者Ar净化气体、提供O3反应气体以及提供N2或者Ar净化气体的步骤。此时,提供Hf源气体的次数以及提供Tb源气体的次数被设置为小于大约9或者大约1的比例。
根据本发明的第一实施方式,该Hf1-xTbxO层被用作电容器的介电层,从而获得厚度(Tox)范围从大约10埃到大约20埃并且具有范围从大约30到大约50的高介电常数的等效氧化层。作为此效果的结果,可以得到高度集成的装置操作所需要的具有足够电容的电容器。并且可以提高介电层的可靠性,因为可以获得与HfO2层相比较低的泄漏电流以及显著的击穿电压特性。另外,由于在高温中的好的温度稳定性,从而可以进一步提高该电容器的寿命和可靠性。
同时,尽管对下电极使用半球形粒状(HSG)结构或者凸凹结构的情况没有在第一实施方式中举例说明,仍然可以通过形成以多晶硅制成的下电极和随后向该下电极应用HSG或凸凹结构而使该电容器的表面面积最大化。
另外,尽管本发明的第一实施方式举例说明了形成圆柱形下电极13的情况,本发明的第一实施方式可用于形成洞穴形的或者内圆柱形的下电极。
图3示出了根据本发明的第二实施方式形成凹入型下电极13的情况。同时图4示出了根据本发明第三实施方式形成内部半球形粒状(HSG)圆柱类型的下电极13B的情况。这里,第一实施方式中使用的同样的参考数字被用于第二实施方式和第三实施方式,并且详细的有关形成凹入型下电极13A以及形成内部HSG圆柱类型的下电极13B的描述被省略。需要注意的是,与在电容器的氧化层被去掉的状态下形成的圆柱状下电极13不同,下电极13A是在存在电容器氧化层11A的情况下形成的。同时,下电极13B是通过在圆柱状下电极的内壁上形成HSG而形成的。
另外,第一实施方式可以同样地应用到下述情况,即每个以圆柱形形成的下电极13A以及每个以内部圆柱形形成的下电极13B是由多晶硅制成的,以在该下电极13A以及下电极13B的表面上形成HSG结构或者凸凹结构。图3和4中的参考号20表示此HSG结构或凸凹结构。
根据本发明的第一到第三优选实施方式,由Hf1-xTbxO制成的介电层使得可以提高介电层的可靠性并且获得具有足够电容的电容器。
本发明包括的主题与2003年12月10日向韩国专利局提交的韩国专利申请KR 2003-0089418相关,这里参考引用该申请的整体内容。
尽管已经参照一定的实施方式对本发明进行了描述,但对于本专业技术人员来说,很明显可以在不脱离本发明的权利要求限定的精神和范围的情况下进行各种变化和修改。

Claims (28)

1.一种在半导体装置中制造电容器的方法,包括下列步骤:
在一基底上形成一下电极;
在所述下电极上形成一非晶体的氧化铪铽(Hf1-xTbxO)介电层;
通过执行一热处理使所述氧化铪铽(Hf1-xTbxO)介电层结晶;以及
在所述氧化铪铽(Hf1-xTbxO)介电层上形成一上电极。
2.如权利要求1所述的方法,其中,所述Hf1-xTbxO介电层的下标x表示铽(Tb)的原子比例,且所述下标的值在大约0.03到大约0.1的范围。
3.如权利要求1所述的方法,其中,形成的所述Hf1-xTbxO介电层的厚度小于大约100埃。
4.如权利要求3所述的方法,其中,所述Hf1-xTbxO介电层通过原子层沉积(ALD)方法而形成。
5.如权利要求3所述的方法,其中,所述Hf1-xTbxO介电层通过低压化学汽相沉积(LPCVD)方法而形成。
6.如权利要求4所述的方法,其中,所述Hf1-xTbxO介电层是通过使用选自包括C13H36HfO4和含铬(Hf)有机金属化合物的Hf前体的组的Hf源气体而形成的。
7.如权利要求4所述的方法,其中,所述Hf1-xTbxO介电层是通过使用选自包含Tb(OC2H5)3和含Tb有机金属化合物的Tb前体的组的Tb源气体而形成的。
8.如权利要求4所述的方法,其中,用于形成Hf1-xTbxO介电层的反应气体选自包括O3气、O2等离子气体和水蒸汽的组。
9.如权利要求6所述的方法,其中,所提供的Hf源气体的流速在从大约50sccm到大约500sccm的范围内。
10.如权利要求7所述的方法,其中,所提供的Tb源气体的流速在从大约50sccm到大约500sccm的范围内。
11.如权利要求8所述的方法,其中,所提供的Tb源气体的流速在从大约0.1slm到大约1slm的范围内。
12.如权利要求8所述的方法,其中,在使用O3气体作为反应气体的情况下,O3气体的浓度被设置在大约200±20g/m3的范围内。
13.如权利要求5所述的方法,其中,所述Hf1-xTbxO介电层是通过使用选自包含C13H36HfO4和含Hf有机金属化合物的Hf前体的组的Hf源气体而形成的。
14.如权利要求5所述的方法,其中,所述Hf1-xTbxO介电层是通过使用选自包含Tb(OC2H5)3和含Tb有机金属化合物的Tb前体的组的Tb源气体而形成的。
15.如权利要求5所述的方法,其中,用于形成Hf1-xTbxO介电层的反应气体选自包括O3气体、O2等离子气体和水蒸汽的组。
16.如权利要求13所述的方法,其中,所提供的Hf源气体的流速在从大约50sccm到大约500sccm的范围内。
17.如权利要求14所述的方法,其中,所提供的Tb源气体的流速在从大约50sccm到大约500sccm的范围内。
18.如权利要求15所述的方法,其中,所提供的反应气体的流速在从大约0.1slm到大约1slm的范围内。
19.如权利要求15所述的方法,其中,在使用O3作为反应气体的情况下,O3气体的浓度被设置在大约200±20g/m3的范围内。
20.如权利要求4所述的方法,其中,通过重复执行用于形成HfO2层的循环和用于形成氧化铽层(TbXOY)的循环来进行所述用于形成Hf1-xTbxO介电层的ALD方法,其中下标x和y分别表示铽(Tb)和氧的原子比例,其比例小于大约9到大约1。
21.如权利要求4所述的方法,其中,通过重复执行一循环来进行用于形成Hf1-xTbxO介电层的ALD方法,所述循环包括顺序提供Hf源气体、提供净化气体、提供Tb源气体、提供净化气体、提供反应气体以及提供净化气体的步骤,条件是所提供的Hf源气体以及Tb源气体的比例被设置为小于大约9或者大约1。
22.如权利要求5所述的方法,其中,用于形成Hf1-xTbxO介电层的LPCVD方法通过以下操作进行:汽化单独地包含Hf和Tb的有机金属化合物,其中,通过使用流量控制器使Hf和Tb的比例分别小于大约9到大约1,并单独地将所属汽化的有机金属化合物提供到用于所述LPCVD方法的反应室。
23.如权利要求22所述的方法,其中,用于所述LPCVD方法的反应室的温度被保持在从大约250℃到大约500℃的范围。
24.如权利要求1所述的方法,其中,所述热处理是炉内退火处理以及快速热处理(RTP)中的一种。
25.如权利要求1所述的方法,其中,所述热处理是在压力增加或者减少的情况下,在温度范围从大约500℃到大约900℃的情况下,在氮气的环境中进行的。
26.如权利要求1所述的方法,其中,所述热处理是在压力增加或者减少的情况下,在温度范围从大约500℃到大约900℃的情况下,在氧气与氮气的混合比例小于大约1到10的气体环境中进行的。
27.如权利要求1所述的方法,其中,所述下电极和上电极是由多晶硅制成的。
28.如权利要求1所述的方法,其中,所述下电极和上电极是由选自包括TiN、Ru、TaN、W、Wsi、WN、RuO2、Ir、IrO2以及Pt的组的金属制成的。
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US20040245602A1 (en) * 2003-05-21 2004-12-09 Kim Sun Jung Method of fabricating metal-insulator-metal capacitor (MIM) using lanthanide-doped HfO2
KR100590592B1 (ko) * 2004-08-20 2006-06-19 삼성전자주식회사 누설 전류를 감소시킨 유전체층을 포함하는 캐패시터 및그 제조 방법
KR100668832B1 (ko) * 2004-11-29 2007-01-16 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
JP2008244306A (ja) * 2007-03-28 2008-10-09 Nec Electronics Corp 半導体装置およびその製造方法
KR101446333B1 (ko) * 2007-08-24 2014-10-08 삼성전자주식회사 결정질 알루미늄 산화물층의 에너지 밴드 갭을 높이는 방법및 에너지 밴드 갭이 높은 결정질 알루미늄 산화물층을포함하는 전하 트랩 메모리 소자의 제조 방법
US10141194B1 (en) * 2017-05-24 2018-11-27 United Microeletronics Corp. Manufacturing method of semiconductor structure
CN108110005A (zh) * 2017-12-07 2018-06-01 睿力集成电路有限公司 晶体管结构、存储单元阵列及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5990507A (en) * 1996-07-09 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor device having ferroelectric capacitor structures
KR100390938B1 (ko) * 2000-02-09 2003-07-10 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
US6664186B1 (en) * 2000-09-29 2003-12-16 International Business Machines Corporation Method of film deposition, and fabrication of structures
US6667246B2 (en) * 2001-12-04 2003-12-23 Matsushita Electric Industrial Co., Ltd. Wet-etching method and method for manufacturing semiconductor device
US7041609B2 (en) * 2002-08-28 2006-05-09 Micron Technology, Inc. Systems and methods for forming metal oxides using alcohols
JP3791614B2 (ja) * 2002-10-24 2006-06-28 セイコーエプソン株式会社 強誘電体膜、強誘電体メモリ装置、圧電素子、半導体素子、圧電アクチュエータ、液体噴射ヘッド及びプリンタ
US6764770B2 (en) * 2002-12-19 2004-07-20 Ut-Battelle, Llc Buffer layers and articles for electronic devices
US20040245602A1 (en) * 2003-05-21 2004-12-09 Kim Sun Jung Method of fabricating metal-insulator-metal capacitor (MIM) using lanthanide-doped HfO2

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118591280A (zh) * 2024-08-06 2024-09-03 武汉新芯集成电路股份有限公司 电容器及其制造方法

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