CN1619781A - 处理方法及装置 - Google Patents
处理方法及装置 Download PDFInfo
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- CN1619781A CN1619781A CNA2004100085025A CN200410008502A CN1619781A CN 1619781 A CN1619781 A CN 1619781A CN A2004100085025 A CNA2004100085025 A CN A2004100085025A CN 200410008502 A CN200410008502 A CN 200410008502A CN 1619781 A CN1619781 A CN 1619781A
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- gas
- plasma
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- nitrogen
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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Abstract
本发明提供一种处理方法,是通过对被处理基体的表面进行氧氮化处理,形成绝缘膜的处理方法;其特征在于,所述方法具有如下步骤:对所述被处理基体照射含有氮原子的等离子体,将所述被处理基体的表面氮化的步骤,和对经过所述氮化处理的所述被处理基体的所述表面照射含有氧原子的等离子体,进行氧化的步骤。
Description
技术领域
本发明涉及处理方法及装置,特别涉及等离子体处理方法及装置。本发明适用于例如用于控制半导体元件绝缘膜膜厚的等离子体处理。
背景技术
目前,作为MOS型半导体元件(Metal Oxide Semiconductor)的绝缘膜使用的二氧化硅膜具有较高的带隙能量或优良的界面特性,支持需要高度可信性的半导体元件。但是,超LSI高集成化发展的现在,MOS晶体管的栅极绝缘膜也向着薄膜化的方向发展,使其膜厚降至2nm或更小。
在此薄膜区域内,就目前使用的二氧化硅膜而言,由于绝缘耐压性急剧降低或由直接隧道电压引起的漏泄电流显著增加,因此难以维持其作为绝缘膜的性能。另外,现有的二氧化硅膜是将加热至1000℃或1000℃以上的硅基板在氧气或水蒸气气氛下氧化而形成的,但是,高温处理对基板的热负荷高,导致基板中已经存在的杂质再扩散,无法进行微细化加工。
因此,开始就将介电常数高(High-k)的材料作为绝缘膜使用的情况进行研究,所述介电常数高的材料不仅能够维持与具有现有二氧化硅膜作为绝缘层的MOS型半导体元件相同的性能及物理膜厚,而且具有减小有效膜厚的效果。其中,由于氮化硅膜或氧氮化硅膜不仅对目前的半导体元件制造工艺适应性高,而且具有抑制嵌入P+Poly栅极的硼向基板内扩散的优良特性,因此,有希望成为90nm结点(node)以下的栅极绝缘膜材料。
作为氮化硅膜及氧氮化硅膜的形成方法,有如下方法:使用氨气(NH3)及甲硅烷(SiH4),利用热CVD法或等离子体CVD法等,将氮化硅膜沉积在硅基板上的方法;或在含有氮气或NH3等含氮气氛中,迅速加热至800~1200℃,进行氮化而形成的方法;或采用热氧化法在硅基板上形成氧化硅膜,在N2、NH3等含氮气氛中加热此氧化硅膜进行氮化的方法。作为进行热氮化处理的具体例,例如有特开2002-198522号公报。
但是,有人指出采用现有方法形成的氮化物膜与SiO2膜相比,膜中的固定电荷或界面能级较多,有时发生平带电压改变或电子迁移性降低等问题。另外,利用高温加热将氮导入膜中时,有时引起硅基板中已经存在的杂质再扩散,难以形成浅层结合,也成为微细化加工的障碍。
发明内容
因此,本发明的目的在于提供一种不采用高温加热的方法、形成具有高度可信性的绝缘膜的处理方法及装置。
本发明的一方面内容为一种处理方法,是通过对被处理基体的表面进行氧氮化处理,形成绝缘膜的处理方法;其特征在于,所述方法具有如下步骤:对上述被处理基体照射含有氮原子的等离子体,将上述被处理基体的表面氮化的步骤;和对经过上述氮化处理的上述被处理基体的上述表面照射含有氧原子的等离子体,进行氧化的步骤。
上述氮化步骤和上述氧化步骤优选将上述被处理基体放置在载置台上进行,优选将上述载置台的温度维持在600℃或600℃以下。上述被处理基体优选含有硅,优选控制上述氮化步骤及/或氧化步骤的处理时间,以便使上述绝缘膜的氧化膜换算膜厚(EOT)为3.0nm或3.0nm以下。上述氮化步骤中使用例如含有N2、NH3、N2H4中的至少一种气体的气体,或含有H2+N2混合气体的气体,或含有用He、Ne、Ar、Kr、Xe中的至少一种气体将所述气体稀释得到的混合气体的气体作为处理气体。上述氧化步骤中使用例如含有O2、O3、H2O、H2O2中的至少一种气体的气体,或含有用He、Ne、Ar、Kr、Xe、N2中的至少一种气体将所述气体稀释得到的混合气体的气体作为处理气体。
上述氧化步骤中,优选将由上述等离子体产生并入射至上述被处理基体的离子能量设定为5eV或5eV以下。上述被处理基体优选含有硅,在上述氧化步骤中,优选控制氧原子浓度,以便使上述绝缘膜的硅及氧氮化硅膜的界面近旁位置上氮原子浓度为5%或5%以下。上述氮化步骤中,优选控制处理时间,以便使上述绝缘膜中所含上述氮原子含量以面密度换算的结果为3×1014cm-2或3×1014cm-2以上、1.5×1015cm-2或1.5×1015cm-2以下。
下面,参照附图说明本发明的优选实施方案,以便明确本发明的其他目的及其特征。
附图说明
图1是本发明的一个实施方案的微波等离子体处理装置的简要剖面图。
图2A-2C是说明使用图1所示的微波等离子体处理装置的绝缘膜形成过程的简要剖面图。
图3是本发明实施例1的等离子体处理装置的简要剖面图。
图4是说明使用图3所示的等离子体处理装置制成的绝缘膜的氮浓度分布的曲线图。
图5是本发明实施例2的等离子体处理装置的简要剖面图。
图6是本发明实施例3的等离子体处理装置的简要剖面图。
图7是示出硅结晶中杂质扩散系数的温度依赖性的曲线图。
图8是适用于图1所示的微波等离子体处理装置的处理系统的简要结构图。
图9是用于说明本发明实施方案的等离子体处理的流程图。
具体实施方式
下面,参照附图详细说明作为本发明一个实施方案的等离子体处理装置(以下,简称为“处理装置”)100。此处,图1为处理装置100的简要剖面图。如图1所示,处理装置100连接图中未示出的微波发生源或高频波源,具有真空容器(或等离子体处理室)101、被处理基体102、载置台(或基座)103、温控部104、气体导入部105、压力调节机构106、电介质窗或高频波透过装置107、微波供给装置或高频波电功率供给装置108,对被处理体102实施等离子体处理。
微波发生源例如由磁电管组成,例如产生2.45GHz的微波。但是,本发明可以在0.8GHz~20GHz的范围内适当选择微波频率。然后,利用图中未示出的模式转换器将微波转换成TM、TE等模式,经导波管传送。微波的导波路径处设置了绝缘体或阻抗匹配器等。绝缘体用于防止被反射的微波返回微波发生源,并将反射波吸收。阻抗匹配器具有检测由微波发生源供给至负荷的前进波与被负荷反射回微波发生源的反射波各自的强度和相位的功率表,发挥了使微波发生源与负荷侧匹配的作用,由4E调谐器、EH调谐器或穿刺调谐器等构成。
作为等离子体激发装置,能够适用电感耦合型、电容耦合型、表面波型、磁电管型、电子回旋共振型等任一种等离子体源,另外氮化处理和氧化处理可以为相同的等离子体源,也可以为不同的等离子体源。
等离子体处理室101是收纳被处理基体102、在真空或减压环境下对被处理基体102实施等离子体处理的真空容器。需要说明的是,在图1中省略了用于将被处理基体102在图中未示出的负荷承载室与处理室间输送的门阀等。
被处理基体102被载置在载置台103上。根据需要,载置台103也可以为高度可调的结构。载置台103被收纳在等离子体处理室101内,用于支撑被处理基体102。
温控部104由加热器等构成,将温度控制在例如600℃或600℃以下,例如200℃或200℃以上、400℃或400℃以下适于进行处理的温度。温控部104具有例如测定载置台103温度的温度计和控制部,所述控制部例如控制由图中未示出的电源对加热线的通电,以便使温度计测定的温度为规定温度。
将温度控制在600℃或600℃以下是因为高温能够促进基板中已经存在的杂质扩散,成为微细化加工的障碍。图7示出硅结晶中硼(B)及磷(P)的扩散系数的温度依赖性。热氧化通常在800℃或800℃以上(通常在1000℃左右)的温度下进行。与此相反,如果如本实施方案所述,将温度设定为600℃或600℃以下,则扩散系数与800℃时相比降低了一个数量级或一个数量级以上,能够防止等离子体处理过程中基板内杂质的扩散。
气体导入部105设置在等离子体处理室101的上部,用于将等离子体处理用气体供给至等离子体处理室101。气体导入部105是气体供给装置的一部分,气体供给装置包括气体供给源、泵、质量流量控制器和用于连接各个部分的气体导入管,供给用于经微波激发获得规定等离子体的处理气体或放电气体。为了将等离子体迅速点火,也可以至少在点火时添加Xe或Ar、He等惰性气体。由于惰性气体没有反应性,因此对被处理基体102无不良影响;而且,由于惰性气体容易电离,因此能够提高微波导入时等离子体的点火速度。从而,如下所述,也可以将气体导入部105例如分成导入处理气体的导入部和导入惰性气体的导入部,将这些导入部配置在不同的位置上。
在本实施方案中,由于进行氧氮化处理,因此使用氮化处理用气体和氧化处理用气体。作为对被处理基体102进行氧化表面处理的氧化性气体,可以举出O2、O3、H2O、H2O2、NO、N2O、NO2等;作为对被处理基体102进行氮化表面处理的氮化性气体,可以举出N2、NH3、N2H4、六甲基二硅氮烷(HMDS)、H2+N2的混合气体等。如上所述,上述处理气体也可以由经He、Ne、Ar、Kr、Xe、N2中至少一种或一种以上的气体稀释得到的混合气体构成。
压力调节机构106设置在等离子体处理室101的下部或底部,具有压力调整阀106a、图中未示出的压力计、真空泵106b及图中未示出的控制部。图中未示出的控制部边运转真空泵106b,边通过控制压力调整阀106a(例如,VAT制带压力调整功能的门阀或MKS制排气隙缝阀)的开关来调整等离子体处理室101内的压力,以便使检测等离子体处理室101内压力的压力计显示为规定值。其结果为经由压力调节机构106,将等离子体处理室101的内部压力控制为适于进行处理的压力。压力优选在13mPa~1330Pa的范围内,更优选在665mPa~665Pa的范围内。真空泵106b例如由涡轮分子泵(TMP)构成,经由图中未示出的电导阀等压力调整阀连接在等离子体处理室101上。
电介质窗107使由微波发生源供给的微波透入等离子体处理室101,同时具有隔离等离子体处理室101的功能。
带隙缝的平板状微波供给装置108具有将微波经由电介质窗107导入等离子体处理室101内的功能,可以使用带隙缝的无终端环状导波管,也可以使用同轴导入平板多隙缝天线,只要能够供给平面微波即可。本发明的微波等离子体处理装置100中使用的平面微波供给装置108的材质只要是导电体即可,为了尽可能地减少微波的传送损失,最优选使用导电率高的Al、Cu、镀Ag/Cu的SUS等。
例如,带隙缝的平面微波供给装置108为带隙缝的无终端环状导波管时,设置冷却水路和隙缝天线。隙缝天线在电介质窗107表面的真空侧由干涉形成表面驻波。隙缝天线例如为具有径向排列的隙缝、沿圆周方向排列的隙缝、配置成大致呈同心圆状或螺旋状的多条T形隙缝、或4对V形隙缝对的金属制圆板。需要说明的是,为了在被处理基体102的整个表面内实施均匀的处理,在被处理基体102上供给表面内均匀性良好的活性物种是重要的。通过给隙缝天线配置至少1条或1条以上的隙缝,能够大面积生成等离子体,等离子体强度·均匀性的控制也变得容易。
下面,参照图9,说明利用处理装置100形成氧氮化膜(绝缘膜)的操作。首先,在利用公知的RCA及稀氢氟酸洗涤法清洗表面后,将结束洗涤后的被处理基体102放置在载置台103上。然后,经由压力调节机构106将等离子体处理室101内真空排气。接下来,将气体导入部105的图中未示出的阀打开,经由质量流量控制器,将处理气体以规定的流量导入等离子体处理室101。然后,调整压力调整阀106a,将等离子体处理室101内的压力保持在规定压力。另外,将微波发生源产生的微波经由微波供给装置108、电介质窗107供给至等离子体处理室101内,在等离子体处理室101内产生等离子体。被导入微波供给装置108内的微波以大于自由空间的管内波长传送,由隙缝开始,经由电介质窗107,导入等离子体处理室101内,在电介质窗107的表面作为表面波传送。此表面波在相邻的隙缝间发生干涉,形成表面驻波。利用此表面驻波形成的电场生成高密度等离子体。由于等离子体生成区域的电子密度高,因此能够效率良好地将处理气体解离。另外,由于电场局部存在于电介质窗附近,因此,电子温度在离开等离子体生成区域后急剧降低,从而能够抑制对装置的损害。等离子体中的活性种经扩散等传送至被处理基体102附近,到达被处理基体102表面。
在本实施方案中,氮化处理(步骤1100)后,交换气体源,进行氧化处理(步骤1200),在同一处理室101中进行氮化处理和氧化处理这样两种处理。参照图2对此进行说明。此处,图2A-2C是用于说明绝缘膜形成的简要剖面图。更具体而言,图2A是洗涤结束后被处理基体102的简要剖面图。图2B是氮化处理后被处理基体102的简要剖面图。图2C是氧化处理后被处理基体102的简要剖面图。
将被处理基体102暴露在产生的氮等离子体205中,如图2B所示,由此在被处理基体102上形成氮化硅膜201。形成所希望膜厚的氮化硅膜后,停止放电及供给处理气体,利用排气装置再次将真空容器充分排气。排气后,利用气体导入部105导入氧处理气体,将处理室101内的压力控制为规定压力。然后,利用微波供给装置108,经由电介质窗107,导入微波,生成等离子体P。将被处理基体102暴露在此处生成的氧等离子体206中,如图2C所示,由此在被处理基体102上将氮化硅膜改性为氧氮化硅膜(绝缘膜)202。204为空间固定电荷。对于绝缘膜的膜厚而言,氧化膜换算膜厚(有效氧化膜厚:EOT)优选为3.0nm或3.0nm以下。
在本实施方案中,形成在被处理基体102上的氮化硅膜201与按现有方法形成的氮化膜同样,在硅基板102和氮化硅膜201的界面附近,存在引起硅晶格变形的硅与氮的不完全结合区域,存在发挥界面能级203作用的缺陷,另外,绝缘膜中具有硅原子或氮原子间的未封端键,作为悬空键存在,发挥空间固定电荷的作用。但是,在等离子体氮化处理步骤后进行的等离子体氧化处理步骤中,反应性高的氧等离子体重新构成存在于界面近旁的变形原子序列,将硅基板表面在原子水平上均化,同时弥补了硅原子与氮原子间的键缺陷。而且,通过对存在于膜中的悬空键进行封端,能够获得界面能级或固定电荷少的高品质绝缘膜。
在本实施方案中,进行氮化硅膜形成步骤的处理室与随后进行氧化的处理室相同,但是,也可以为不同的处理室。此时,理想的情况是使用具有晶片分隔室的集结式装置,在高真空条件下进行氮化膜形成步骤至氧化步骤的一系列处理。具体例如图8所示。图8是处理系统的简要结构图。处理系统具有等离子体处理室301、等离子体处理室302、基板载置室303、运送室304和运送装置305。等离子体处理室301及302具有图1所示的处理装置100,基板载置室303收纳氧氮化处理后的被处理基体102。传送室304具有能够运送被处理基体102的运送装置(或自动设备),具有控制此自动设备的控制部。运送装置305具有可360度旋转的基部和能够保持并运送被处理基体102、并将被处理基体102在等离子体处理室301及302和基板载置室303间运送的机构。由于运送室304和运送装置305可采用集结式工具等业界周知的技术,因此此处省略了详细说明。
在操作过程中,运送装置305将洗涤后的被处理基体102从基板载置室303或其它收纳部内取出,导入等离子体处理室301内。等离子体处理室301在被处理基体102上进行等离子体氮化处理。在等离子体氮化处理后,运送装置305将被处理基体102从等离子体处理室301取出,导入等离子体处理室302。在等离子体处理室302中对被处理基体102进行等离子体氧化处理。等离子体氧化处理后,运送装置305将被处理基体102从等离子体处理室302取出,收纳在基板载置室303内。
本实施方案的绝缘膜是具有高介电常数且膜中的固定电荷、界面能级密度低的高品质绝缘膜。而且,因导入绝缘膜内的氮原子而变得较致密,能够防止硼等杂质向基板侧扩散,不仅能够单独用作绝缘膜,而且也可以作为其它高介电常数材料的底膜使用。
本实施方案在利用氮等离子体形成氮化硅膜后,进行等离子体氧化处理,由此将活性氧原子导入硅基板与氮化硅膜界面附近及膜中。结果引起存在于膜中的硅原子或氮原子重新排列,弥补界面上发生的缺陷,通过与悬空键的再结合,能够减少在氮化硅膜中存在问题的界面能级或固定电荷等各种缺陷。而且,氮化处理、氧化处理均使用能够在600℃或600℃以下较低的温度条件下进行处理的等离子体处理,因此形成绝缘膜时减轻降低了对基板的热处理,基板中形成的杂质不发生再次扩散,防止浅结合的发生,有利于微细化加工。通过改变在硅基板上最初形成氮化硅膜时的处理条件及氧化硅氮化膜时的处理条件,可以控制形成的绝缘膜的品质。
氮化硅膜的膜厚及导入膜中的氮原子含量可以由最初形成氮化硅膜时的处理条件及氧化硅氮化膜时的处理条件等进行控制,除此之外,膜中所含氮原子在深度方向的浓度分布也可以通过改变进行氧化处理的时间、温度、氧离子的入射能量而进行控制。
为了避免起因于具有高能量的氧离子被压入绝缘膜内的损害,导入基板内的氧离子的入射能量优选为5eV或5eV以下。作为氧离子能量的控制方法,有根据等离子体激发装置、高频波电场施加时间的脉冲化、处理条件等使鞘电位改变的方法,或使用能够对基板施加偏压电压的电源的方法等任一种方法。
对于绝缘膜中的氮原子而言,为了获得表面缺陷少的高介电常数的绝缘膜,优选形成这样的氧原子浓度分布,以便使硅/氧氮化硅膜间的界面近旁位置处氮原子浓度为5%或5%以下。另外,为了在获得抑制硼等杂质扩散效果的同时获得足够高的介电常数,优选使绝缘膜中所含氮原子的含量以面密度换算为3×1014cm-2或3×1014cm-2以上、1.5×1015cm-2或1.5×1015cm-2以下。
如上所述形成的氧氮化硅膜不仅可以以单体形式作为MISFET(Metal Insulator Semiconductor Field Effect Transistor)的栅极绝缘膜、或MIS结构存储元件的电容器绝缘膜使用,而且也可以作为HfO2、ZrO2等具有更高介电常数膜的底膜阻隔层使用。高介电常数材料能够适用以Al、Hf、Zr、Ti0、Ta等为主成分的金属氧化物或这些金属的硅酸盐膜,或以Y、La、Ce、Pr、Nd、Gd、Dy、Ho、Yb等为主成分的稀土金属氧化物膜。
为了在更低压力的条件下进行处理,也可以在处理装置100中使用磁场发生装置。作为在本发明的等离子体处理装置及处理方法中使用的磁场,只要是与在隙缝宽度方向上产生的电场相垂直的磁场即可。作为磁场发生装置,除了线圈以外,也可以使用永久磁石。使用线圈时,为了防止过热,也可以使用水冷机构或空气冷却机构等其它冷却装置。
下面,说明微波等离子体处理装置100的具体实施例,但是本发明并不限定于这些实施例。
(实施例1)
作为处理装置100的一实例,使用图3所示的微波等离子体处理装置100A,形成半导体元件的栅极绝缘膜。处理装置100A能够利用微波激发表面波干涉等离子体,在同一处理室内连续进行氮化处理及氧化处理。108A是用于将微波经由电介质窗107导入等离子体处理室101的带隙缝无终端环状导波管。需要说明的是,图3中,与图1相同的部件具有相同的附图标号,对应部件的变形例或具体例用相同的附图标号加上字母表示。
带隙缝的无终端环状导波管108A为TE10模式,内壁剖面的尺寸为27mm×96mm(管内波长158.8mm),导波管的中心直径为151.6mm(周长为管内波长的3倍)。为了减少微波的传送损失,带隙缝的无终端环状导波管108A的材质全部使用铝合金。在带隙缝的无终端环状导波管108A的H面上形成用于将微波导入等离子体处理室101的隙缝。隙缝为长40mm、宽4mm的矩形,在中心直径为151.6mm的位置处间隔60°放射状地形成6条隙缝。带隙缝的无终端环状导波管108A处依次连接4E调谐器、方向性耦合器、绝缘体、频率为2.45GHz的微波电源(图中未示出)。
作为被处理基体102,使用8英寸P型单晶硅(表面方位<100>,电阻率10Ωcm)。首先,将被处理基体102运送至等离子体处理室101,设置在载置台103上。此时,利用加热器104将被处理基体102加热并保持在300℃。
然后,以200sccm的流量将N2气导入处理室101内,调整设置在压力调整机构106处的压力调整阀106a的开启程度,将处理室101内的压力保持在133Pa。然后,经由微波供给装置108A及电介质窗107将2.45GHz、1kW的微波电功率导入处理室101内,产生等离子体P。将被处理基体102暴露在产生的氮等离子体中60秒,形成氮化硅膜。用偏振光测量仪测定此时形成的氮化硅膜膜厚,结果为1.8nm。
然后,用真空泵将处理室101内抽成真空至10-3Pa后,以200sccm的流量导入O2气,调整压力调整阀106a的开启程度,将处理室101内的压力保持在400Pa。然后,经由微波供给装置108A及电介质窗107将2.45GHz、1kW的微波电功率导入处理室101内,产生等离子体P。将氮化硅膜暴露在产生的氧等离子体中30秒,将其改性成氧氮化硅膜。
用偏振光测量仪测定如上所述形成的氧氮化硅膜的膜厚,结果为2.3nm。另外,使用RBS(Rutherford Back Scattering Spectroscopy)测定膜中氮浓度在深度方向的分布时,得到如图4所示的分布,估计导入膜中的氮的表面浓度约为1.3×1015cm-2。
接下来,使用利用上述处理方法制成的氧氮化硅膜,制造具有MOS结构的电容器,评价绝缘膜的电特性。测定结果显示,C-V特性产生的氧化硅膜换算膜厚(EOT)测定结果为2.0nm,表明通过将氮导入氧化膜中,提高了介电常数,能够获得薄膜化的效果。
(实施例2)
作为处理装置100的一实例,使用图5所示的处理装置100B,形成半导体元件的栅极绝缘膜。处理装置100B使用能够以RF方式激发等离子体、并且能够施加脉冲化的电功率的高频波电源110。使用此装置,进行氮化处理及氧化处理。如图8所示,本实施例的等离子体处理在独立的处理室301及302内分别进行氮化处理及氧化处理。需要说明的是,在图5中,与图1相同的部件具有相同的附图标号,对应部件的变形例或具体例用相同的附图标号加上字母表示。
作为被处理基体102,使用8英寸P型单晶硅(表面方位<100>,电阻率10Ωcm)。首先,将被处理基体102运送至等离子体处理室101,设置在载置台103上。此时,利用加热器104将被处理基体102加热并保持在400℃。
然后,利用气体导入部105B,以200sccm的流量将N2气导入处理室101内,调整设置在压力调整机构106处的压力调整阀106a的开启程度,将处理室101内的压力保持在63.3Pa。然后,经由高频波供给装置108B及高频波透过装置107A将13.56GHz、800W的RF电功率导入处理室101内,产生等离子体P。将被处理基体102在产生的氮等离子体中暴露120秒,形成氮化硅膜。用偏振光测量仪测定此时形成的氮化硅膜膜厚,结果为2.2nm。
然后,用真空泵将处理室101内抽成真空至10-3pa后,利用气体导入部105B,以200sccm的流量导入O2气,调整压力调整阀106a的开启程度,将处理室101内的压力保持在266Pa。然后,经由高频波供给装置108B及高频透过装置107B将13.56GHz、800W的RF电功率导入处理室101内,产生等离子体P。此时,将RF电功率的施加电压成为占空比30%的脉冲波,以便降低等离子体中的电子温度。由分布测定结果可知,基板上产生的鞘电位改变,入射氧离子的入射能量在RF连续放电时约为6eV,而将RF脉冲化后降至约4eV。将氮化硅膜在产生的氧等离子体中暴露30秒,将其改性成氧氮化硅膜。
用偏振光测量仪测定如上所述形成的氧氮化硅膜的膜厚,结果为2.6nm。另外,为了研究此时因氧离子导入而在绝缘膜中产生的损害,使用SCA,评价膜中产生的带电损害。结果为与在入射离子能量高的条件下固定电荷密度为6.3×1011qcm-2相反,入射离子能量低的条件下,固定电荷密度为3.7×1011qcm-2,得到显著的改善。
(实施例3)
在实施例3中,对氮化处理和氧化处理分别使用不同的等离子体激发装置。首先,在氮化步骤中,使用处理装置100A进行处理,制成氮化硅膜。
作为被处理基体102,使用8英寸P型单晶硅(表面方位<100>,电阻率10Ωcm)。首先,将被处理基体102运送至等离子体处理室101,设置在载置台103上。此时,利用加热器104将被处理基体102加热并保持在400℃。
分别以50、450sccm的流量将N2、He的混合气体导入等离子体处理室101内,调整压力调整阀106a的开启程度,将处理室101内的压力保持在26.6Pa。然后,经由微波供给装置108A及电介质窗107A将2.45GHz、1kW的微波电功率导入处理室101内,产生等离子体P。将被处理基体102在产生的氮等离子体中暴露20秒,形成氮化硅膜。用偏振光测量仪测定此时形成的氮化硅膜膜厚,结果为1.7nm。
然后,使用图6所示的RF磁电管激发等离子体处理装置100C进行等离子体氧化处理。将氮化硅膜运送至氧化处理用处理室302,设置在载置台103上。此时,用加热器将氮化处理后的被处理基体102加热并保持在300℃。接下来,利用气体导入部105B,分别以20、180sccm的流量导入O2、Ar的混合气体,调整压力调整阀106a的开启程度,将处理室101内的压力保持在400Pa。然后,对电极施加13.56MHz、450W的RF电功率,经由高频波透过窗107C导入处理室101内,产生等离子体P。将氮化硅膜在产生的氧等离子体中暴露45秒,将其改性成氧氮化硅膜。用偏振光测量仪测定此时形成的氧氮化硅膜膜厚,结果为2.3nm。
使用如上所述形成的绝缘膜,制成具有MOS结构的电容器,进行电特性评价。结果为固定电荷密度为2.2×1011cm-2左右,界面能级密度为6.5×1011eV-1cm-2左右,显示良好的结果。
(实施例4)
在本实施例中,使用等离子体处理装置100A,进行硅基板的氮化处理和氧化处理,形成氧氮化硅膜后,形成铪氧化物,进行半导体元件的栅极绝缘膜形成。
作为被处理基体102,使用8英寸P型单晶硅(表面方位<100>,电阻率10Ωcm)。首先,将被处理基体102运送至等离子体处理室101,设置在载置台103上。此时,利用加热器104将被处理基体102加热并保持在300℃。
以550sccm的流量将N2气导入等离子体处理室101内,调整压力调整阀106a的开启程度,将处理室101内的压力保持在133Pa。然后,经由微波供给装置108A及电介质窗107将2.45GHz、1kW的微波电功率导入处理室101内,产生等离子体P。将被处理基体102在产生的氮等离子体中暴露60秒,形成氮化硅膜。用偏振光测量仪测定此时形成的氮化硅膜膜厚,结果为1.7nm。
然后,用真空泵将处理室101内抽成真空至10-3Pa后,分别以20、180sccm的流量导入O2、He的混合气体,调整压力调整阀106a的开启程度,将处理室101内的压力保持在266Pa。然后,经由微波供给装置108A及电介质窗107将2.45GHz、1kW的微波电功率投入处理室101内,产生等离子体P。将氮化硅膜在产生的氧等离子体中暴露20秒,将其改性成氧氮化硅膜。
然后,在利用溅射法在氧氮化硅膜上沉积膜厚为2nm的铪后,利用RTO将被处理基体102氧化,形成氧化铪膜。
使用如上所述形成的绝缘膜,制成具有MOS结构的电容器,进行电特性评价。结果为:EOT为2.5nm,固定电荷密度为2.8×1011cm-2左右,界面能级密度为6.9×1010eV-1cm-2左右,显示良好的结果。
如上所述,根据本实施例,在半导体基板上进行等离子体氮化处理后,进行等离子体氧化处理,由此能够在低温条件下形成界面能级或固定电荷之类缺陷少的品质良好的氧氮化硅膜,通过使用此氧氮化硅膜,能够提供一种高性能的MOS装置。
以上说明了本发明的优选实施例,但是本发明并不限定于这些实施例,在其主旨的范围内,可以进行各种变形及改变。
根据本发明,能够提供一种不采用高温加热的方法、形成具有高度可信性的绝缘膜的处理方法及装置。更具体而言,能够提供一种具有高介电常数、且膜中的固定电荷、界面能级密度低的高品质绝缘膜。而且,通过在绝缘膜中导入氮原子,能够防止硼等杂质向基板侧扩散,得到的绝缘膜不仅能够单独作为绝缘膜使用,而且能够作为其它高介电常数材料的底膜使用。
Claims (8)
1.一种处理方法,是通过对被处理基体的表面进行氧氮化处理,形成绝缘膜的处理方法;其特征在于,所述方法具有如下步骤:
对所述被处理基体照射含有氮原子的等离子体,将所述被处理基体的表面氮化,和
对经过所述氮化处理的所述被处理基体的所述表面照射含有氧原子的等离子体,进行氧化。
2.如权利要求1所述的方法,其特征在于,将所述被处理基体放置在载置台上,将所述载置台的温度维持在600℃或600℃以下,进行所述氮化步骤和所述氧化步骤。
3.如权利要求1所述的方法,其特征在于,所述被处理基体含有硅,控制所述氮化步骤及/或氧化步骤的处理时间,以便使所述绝缘膜的氧化膜换算膜厚(EOT)为3.0nm或3.0nm以下。
4.如权利要求1所述的方法,其特征在于,所述氮化步骤使用含有N2、NH3、N2H4中的至少一种气体的气体,或含有H2+N2混合气体的气体,或含有用He、Ne、Ar、Kr、Xe中的至少一种气体将所述气体稀释得到的混合气体的气体作为处理气体。
5.如权利要求1所述的方法,其特征在于,所述氧化步骤使用含有O2、O3、H2O、H2O2中的至少一种气体的气体,或含有用He、Ne、Ar、Kr、Xe、N2中的至少一种气体将所述气体稀释得到的混合气体的气体作为处理气体。
6.如权利要求1所述的方法,其特征在于,所述氧化步骤将由所述等离子体产生、入射至所述被处理基体的离子能量设定为5eV或5eV以下。
7.如权利要求1所述的方法,其特征在于,所述被处理基体含有硅,在所述氧化步骤中,控制氧原子浓度,以便使所述绝缘膜的硅与氧氮化硅膜的界面近旁位置上的氮原子浓度为5%或5%以下。
8.如权利要求1所述的方法,其特征在于,在所述氮化步骤中,控制处理时间,以便使所述绝缘膜中所含所述氮原子含量以面密度换算的结果为3×1014cm-2或3×1014cm-2以上、1.5×1015cm-2或1.5×1015cm-2以下。
Applications Claiming Priority (2)
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JP389876/2003 | 2003-11-19 | ||
JP2003389876A JP2005150637A (ja) | 2003-11-19 | 2003-11-19 | 処理方法及び装置 |
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CN1619781A true CN1619781A (zh) | 2005-05-25 |
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US (1) | US20050106896A1 (zh) |
JP (1) | JP2005150637A (zh) |
KR (1) | KR20050049294A (zh) |
CN (1) | CN1619781A (zh) |
TW (1) | TW200517524A (zh) |
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CN101681833B (zh) * | 2007-06-14 | 2011-06-22 | 东京毅力科创株式会社 | 微波等离子体处理装置和微波等离子体处理方法以及微波透过板 |
CN106952810A (zh) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的制造方法 |
CN107768244A (zh) * | 2016-08-19 | 2018-03-06 | 圆益Ips股份有限公司 | 非晶质硅膜的形成方法 |
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JP2005317647A (ja) * | 2004-04-27 | 2005-11-10 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4028538B2 (ja) * | 2004-09-10 | 2007-12-26 | 株式会社東芝 | 半導体装置の製造方法およびその製造装置 |
KR100648632B1 (ko) * | 2005-01-25 | 2006-11-23 | 삼성전자주식회사 | 높은 유전율을 갖는 유전체 구조물의 제조 방법 및 이를 포함하는 반도체 소자의 제조 방법 |
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US20070010103A1 (en) * | 2005-07-11 | 2007-01-11 | Applied Materials, Inc. | Nitric oxide reoxidation for improved gate leakage reduction of sion gate dielectrics |
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-
2003
- 2003-11-19 JP JP2003389876A patent/JP2005150637A/ja active Pending
-
2004
- 2004-01-29 TW TW093102012A patent/TW200517524A/zh unknown
- 2004-01-30 US US10/766,854 patent/US20050106896A1/en not_active Abandoned
- 2004-01-31 KR KR1020040006417A patent/KR20050049294A/ko not_active Application Discontinuation
- 2004-03-11 CN CNA2004100085025A patent/CN1619781A/zh active Pending
Cited By (5)
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CN101681833B (zh) * | 2007-06-14 | 2011-06-22 | 东京毅力科创株式会社 | 微波等离子体处理装置和微波等离子体处理方法以及微波透过板 |
CN106952810A (zh) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的制造方法 |
CN106952810B (zh) * | 2016-01-06 | 2020-07-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的制造方法 |
CN107768244A (zh) * | 2016-08-19 | 2018-03-06 | 圆益Ips股份有限公司 | 非晶质硅膜的形成方法 |
CN107768244B (zh) * | 2016-08-19 | 2021-08-13 | 圆益Ips股份有限公司 | 非晶质硅膜的形成方法 |
Also Published As
Publication number | Publication date |
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TW200517524A (en) | 2005-06-01 |
JP2005150637A (ja) | 2005-06-09 |
KR20050049294A (ko) | 2005-05-25 |
US20050106896A1 (en) | 2005-05-19 |
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