CN1617300A - 多晶硅薄膜的制造方法和用多晶硅薄膜制造的显示器件 - Google Patents

多晶硅薄膜的制造方法和用多晶硅薄膜制造的显示器件 Download PDF

Info

Publication number
CN1617300A
CN1617300A CNA2004101005988A CN200410100598A CN1617300A CN 1617300 A CN1617300 A CN 1617300A CN A2004101005988 A CNA2004101005988 A CN A2004101005988A CN 200410100598 A CN200410100598 A CN 200410100598A CN 1617300 A CN1617300 A CN 1617300A
Authority
CN
China
Prior art keywords
laser
district
mask
transmitting
transmitting district
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004101005988A
Other languages
English (en)
Other versions
CN100375233C (zh
Inventor
朴志容
朴惠香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung SDI Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung SDI Co Ltd filed Critical Samsung SDI Co Ltd
Publication of CN1617300A publication Critical patent/CN1617300A/zh
Application granted granted Critical
Publication of CN100375233C publication Critical patent/CN100375233C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B13/00Single-crystal growth by zone-melting; Refining by zone-melting
    • C30B13/16Heating of the molten zone
    • C30B13/22Heating of the molten zone by irradiation or electric discharge
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • C30B29/605Products containing multiple oriented crystallites, e.g. columnar crystallites
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02595Microstructure polycrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678Beam shaping, e.g. using a mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691Scanning of a beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1296Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor

Abstract

本发明涉及一种多晶硅薄膜的制造方法,该方法通过使用具有激光透射区和非透射区混合结构的掩模而能够利用激光得到均匀结晶的多晶硅薄膜,其中激光透射区基于激光扫描方向轴线不对称,激光透射区基于某一中心轴线对称,将激光透射区在平行于该中心轴线的另一轴线的方向上移动一定距离,从而使激光透射区和非激光透射区交替地设置。

Description

多晶硅薄膜的制造方法和用多晶硅薄膜制造的显示器件
技术领域
本发明涉及一种用于设备中的多晶硅薄膜的制造方法和使用由该方法制造的多晶硅薄膜的设备,特别涉及能控制多晶硅薄膜晶粒形状的多晶硅薄膜的制造方法和使用多晶硅薄膜的设备。
背景技术
通常,连续横向固化(SLS)结晶法通过将激光束两次或更多次地照射在非晶硅层上来横向生长晶粒硅。如此形成的多晶硅晶粒为柱状;此外,由于晶粒的有限尺寸,在相邻的晶粒间出现晶粒边界。
通过SLS结晶技术可以在衬底上形成多晶或单晶的大硅晶粒,并且能获得与由单晶硅制造的薄膜晶体管(TFT)相似的特性。
图1A、图1B、图1C示出了普通的SLS结晶法。
在图1A中示出的SLS结晶法中,激光束穿过具有激光束透射区和激光束非透射区的掩模照射在非晶硅薄膜层上,从而熔化激光束透射区的非晶硅。
如果在激光束照射结束后开始冷却,那么结晶优先发生在非晶硅和熔化硅之间的界面处,其中形成从非晶硅和熔化硅界面向熔化硅层方向温度逐渐减小的温度梯度。
因此,参见图1B,由于热通量在从掩模的界面向熔化硅层中心部分的方向上流动,因此形成了具有横向生长的柱状晶粒的多晶硅薄膜层。多晶硅横向生长直到熔化硅层完全固化。
如图1C所示,通过移动载物台进而移动掩模、并且将激光束照射在非晶硅薄膜层和已结晶多晶硅层的露出部分上,将非晶硅和晶体硅熔化。硅原子粘附在被掩模覆盖的已形成的多晶硅晶粒上,所以在熔化以后当熔化非晶硅和晶体硅冷却时晶粒的长度增加。
图2A、图2B、图2C示出用普通制造多晶硅薄膜的掩模结构形成结晶晶粒硅的方法,图3A、图3B、图3C示出多晶硅薄膜制造的不同阶段的平面图。
在图2A中,使用具有激光束透射区和激光束非透射区的普通掩模将激光束照射在非晶硅上,使非晶硅熔化。当熔化非晶硅固化时形成多晶硅。
将掩模移动图2B所示的确定距离,激光束照射在部分以前形成的多晶硅和单晶硅上,如图2C所示。通过不断地扫描多晶硅并且以此方式在多晶硅上照射激光束,在非晶硅的掩模图案和透射区彼此重叠的位置处,多晶硅熔化并且在固化时结晶。
激光脉冲照射的每部分多晶硅的结晶度不同,原因在于,激光发射能量密度的偏差,或者激光束如图3A所示地曾经照射过的非晶硅中的激光束的能量密度不均匀。
具体地,如图3B和图3C所示,激光扫描线在不同激光发射之间的上下边界引起条状缺陷。
这些条状缺陷引起显示器亮度的不均匀,特别是对于有机电致发光器件。
PCT国际专利申请No.WO97/45827和美国专利No.6322625公开了通过连续横向固化(SLS)方法将衬底上的非晶硅转变成多晶硅或者在衬底上仅使选择区结晶的技术。
此外,美国专利No.6177391中公开了仅对单晶硅获得TFT特性,由于当通过SLS结晶法使有源沟道方向平行于晶粒生长方向生长时,晶粒边界对载流子方向的阻挡效应被最小化。但是该专利还公开了,大量的晶粒边界起载流子的陷阱作用,并且当有源沟道方向垂直于晶粒生长方向时,TFT特性显著变差。
然而存在以下的情况:使用通常垂直于像素单元区TFT的TFT驱动电路制备有源矩阵显示器件,其中当有源沟道区方向相对于晶体生长方向倾斜30到60度时,显示器的亮度均匀性得到改善。
但是使用这种方法,在通过SLS结晶法形成晶粒之后,仍然存在由于激光能量密度的非均匀性造成的非均匀晶粒的问题。
此外,使用这种方法,不能在整个衬底上实现结晶,因此始终存在未结晶区域,尽管韩国特许公开的NO.2002-93194中介绍了以下方法,其中,形成三角形(“”)激光束图案并且通过沿着宽度方向移动三角形(“”)激光束图案进行结晶。
发明内容
因此,本发明提出一种制造多晶硅薄膜的方法和一种使用多晶硅薄膜制造的设备,其能够显著地避免现有技术的限制和缺点引起的一个或多个问题。
本发明提供一种改善由SLS结晶法制造的多晶硅薄膜均匀性的方法。
本发明提供一种使用由上述方法制造的多晶硅薄膜的设备。
本发明的其他特征在下文的描述中阐明,部分通过所述描述显然可知或者通过实践本发明习得。
本发明公开一种多晶硅薄膜制造方法,其中通过激光使非晶硅结晶,该方法包括:形成具有激光透射区和非激光透射区的掩模;以及基于平行于预定中心轴线的轴线将激光透射区移动一定距离。激光透射区相对激光扫描轴线不对称,并且激光透射区相对预定中心轴线对称。激光透射区和激光非透射区交错设置。预定的中心轴线是x和/或y。
本发明还公开了一种使用多晶硅薄膜的显示器,该多晶硅薄膜通过以下方法制备:形成具有激光透射区和激光非透射区的掩模,基于平行于预定的中心轴线的轴线将激光透射区移动一定距离。预定的中心轴线是x和/或y,激光透射区在激光扫描轴线上不对称,激光透射区在预定的中心轴线上对称,预定的中心轴线是x和/或y。激光透射区和激光非透射区交错设置。
本发明还公开了一种制造多晶硅薄膜用的掩模,其包括激光透射区和激光非透射区,激光透射区相对激光扫描方向轴线不对称,并且激光透射区相对预定的中心轴线对称。预定的中心轴线是x和/或y。
应该认识到,前述整体描述和下文的详细描述是示例和说明用的,目的在于提供对请求保护的发明做出进一步的解释。
附图说明
附图提供对发明的进一步理解并且组成说明书的一部分,其示出了本发明的实施例,并与下文的描述一起解释本发明的原理,附图中:
图1A、图1B、图1C示出了普通的顺序横向固化(SLS)结晶方法;
图2A、图2B、图2C示出了用普通的制造多晶硅薄膜掩模结构来结晶晶粒硅的方法;
图3A、图3B、图3C示出了图2A、图2B、图2C制造多晶硅薄膜的各个阶段;
图4A示出当激光在线形透射图案上照射一次的情形;
图4B示出通过移动掩模图案一确定距离而将激光在线形透射图案上照射两次的情形;
图5A示出当激光在两种不同长度线形透射图案上照射一次的情形;
图5B示出通过移动掩模图案一确定距离而将激光在不同长度线形透射图案上照射两次的情形;
图6A示出当激光在两种不同长度线形透射图案上照射一次、但是透射图案的长度小于第一实施例的透射图案的长度的情形;以及
图6B示出当通过移动掩模图案一确定距离而将激光在不同长度线形透射图案上照射两次的情形。
具体实施方式
下面详细描述本发明的实施例,该实施例的示例在附图中示出。
作为参考,类似参考符号在所有视图中表示对应部件。
图4A和图4B示出根据本发明第一个示例性实施例的掩模图案以及扫描过程。图4A示出激光在线形透射图案上照射一次的情形。图4B示出通过移动掩模图案一确定距离而将激光在线形透射图案上照射两次的情形。
根据图4A,透射图案组具有形成在上下掩模图案中的透射区,透射区相对于x轴互相不对称,该x轴是平行于扫描方向的方向轴,透射区相对于与x轴垂直的y、y’轴互相对称。
掩模图案基于平行于某一中心轴线的另一轴线移动一定距离,这样,在激光在前述掩模图形上照射一次之后,当掩模移动时,透射区和非透射区互换。
如图4B所示,在移动掩模以前的那部分透射区和在移动掩模以后的部分透射区重叠,其中部分透射区被移动形成在非透射区上,同时部分非透射区被移动形成在透射区上。
因此,在区域b上形成和区域a上相同的晶粒,原因在于,移动掩模后,通过在使用激光熔化区域b的晶粒之后结晶熔化的晶粒,使用与照射区域a的激光能量相同的能量使区域b二次结晶,但是,根据图3B所示的激光照射能量偏差,在激光在掩模图形上照射一次的情况下,晶粒在垂直方向上形成得不同。最后,产生如图4A所示的、透射区被移动d-I的效果,其中距离d-I是通过将距离d减去在透射区之间的非透射区的最小宽度I,其中d大于I。
掩模基于y”轴沿着扫描方向轴移动掩模宽度的1/4。
因此,以均匀形成晶粒的方式形成多晶硅薄膜。
虽然图4A示出线形透射区的形状,但是透射区不限于线形形状。
图5A和图5B示出据本发明的第二示例性实施例的平面图的掩模图案和扫描情况。图5A示出当激光在不同长度的三种线形透射图案上照射一次的情况,图5B示出通过将掩模图案移动一定距离而将激光在不同长度线形透射图案上照射两次的情况。
如图5A和图5B所示,根据本发明第二示例性实施例的掩模图案具有如下结构:包括第一线形透射区、第二线形透射区和第三线形透射区,其中第二线形透射区的长度比第一线形透射区的长度短,第三线形透射区的长度比第二线形透射区的长度短。
该掩模图案也可以是如下方式的,其中透射区基于x轴相互不对称,该x轴是平行于扫描线方向的轴线,并且透射区基于与x轴垂直的y、y’轴相互对称。
掩模图案在平行于某一中心轴线的另一轴线上移动一定距离,这样,在激光在前述掩模上照射一次后,移动掩模时,使透射区和非透射区互换。
即,如图5B所示,移动掩模前的部分透射区和移动掩模后的部分透射区重叠,其中部分透射区被移动而形成在非透射区上,同时部分非透射区被移动而形成在透射区上。
因此,在区域b上形成和区域a上相同的晶粒,原因在于,移动掩模后,通过在使用激光熔化区域b的晶粒之后结晶熔化的晶粒,使用与照射区域a的激光能量相同的能量使区域b二次结晶,但是,根据图3B所示的激光照射能量偏差,在激光在掩模图形上照射一次的情况下,晶粒在垂直方向上形成得不同。最后,产生如图5A所示的、透射区被移动d-I的效果。
图6A和图6B是示出根据本发明第三示例性实施例的掩模图案和扫描情况的平面图。图6A示出当激光在两种线形透射图案照射一次的情况,其中所述线形图案具有不同长度并且其长度比第一实施例中的短。图6B示出当通过移动掩模图案一定距离而将激光在不同长度线形透射图案上照射两次的情况。
掩模图案也可以是如下方式的,其中透射区基于x轴相互不对称,该x轴是平行于扫描线方向的轴线,透射区基于与x轴垂直的y、y’轴线相互对称。
掩模图案在平行于某一中心轴线的另一轴线上移动一定距离,这样,当激光在前述掩模上照射一次时,移动掩模,从而使透射区和非透射区互换。
即,如图6B所示,移动掩模前的部分透射区和移动掩模后的部分透射区重叠,其中部分透射区被移动而形成在非透射区上,同时部分非透射区被移动而形成在透射区上。
因此,在区域b上形成和区域a上相同的晶粒,原因在于,移动掩模后,通过在使用激光熔化区域b的晶粒之后结晶熔化的晶粒,使用与照射区域a的激光能量相同的能量使区域b二次结晶,但是,根据图3B所示的激光照射能量偏差,在激光在掩模图形上照射一次的情况下,晶粒在垂直方向上形成得不同。最后,产生如图5A所示的、透射区被移动d-I的效果。
如前所述,通过如本发明示例性实施例所述地设计掩膜图案,可以防止结晶过程中由于激光能量偏差而引起的多晶硅的不均匀结晶。
本发明所用的显示器优选是平板显示器,例如液晶显示器或有机电致发光器件。
如前所述,通过形成掩模图案来克服由于激光偏差而引起的多晶硅不均匀结晶,本发明能够解决显示器的亮度不均匀问题。
显然,在不脱离本发明精神和范围的前提下可以对本发明做出各种修改和变动。因此,本发明覆盖在权利要求书及其等价物的范围内的各种修改和变动。

Claims (18)

1、一种使用激光由非晶硅制造多晶硅的方法,包括:
设置具有激光透射区和非透射区的掩模图案的掩模;以及,
基于与预定中心轴线平行的轴线方向移动掩模,
其中,激光透射区基于激光扫描方向轴线不对称,并且激光透射区基于预定中心轴线方向对称;以及
激光透射区和激光非透射区是交替设置。
2、如权利要求1所述的方法,其特征在于,激光透射区是全等的线形区域。
3、如权利要求1所述的方法,其特征在于,激光透射区包括线形图案的第一激光透射区和线形图案的第二激光透射区,并且第二激光透射区比第一激光透射区短。
4、如权利要求3所述的方法,其特征在于,激光透射区还包括线形图案的第三激光透射区,第三激光透射区比第一激光透射区长。
5、如权利要求1所述的方法,其特征在于,平行于预定中心轴线的轴线位于掩模的中心,并且掩模基于与预定中心轴线平行的轴线移动掩模宽度的1/4。
6、如权利要求1所述的方法,其特征在于,预定中心轴线垂直于激光扫描方向轴。
7、如权利要求1所述的方法,其特征在于,平行于预定中心轴线的轴线垂直于激光扫描轴线方向,并且位于掩模中心。
8、如权利要求1所述的方法,其特征在于,激光透射区具有如下结构:当掩模基于与预定中心轴线平行的轴线移动一定距离时,激光透射区在垂直于激光扫描轴线的方向上部分重叠。
9、如权利要求8所述的方法,其特征在于,在垂直于激光扫描方向轴的方向上,激光透射区的重叠距离比激光透射区的宽度短。
10、如权利要求1所述的方法,其特征在于,激光透射区基于y轴不对称。
11、一种显示器,其使用通过以下工艺制造的多晶硅薄膜:
设置具有激光透射区和非透射区的掩模图案的掩模;和
基于与预定中心轴线平行的轴线移动掩模,
其中,激光透射区基于激光扫描方向轴线不对称,并且激光透射区基于预定中心轴线对称;以及
激光透射区和激光非透射区交替设置。
12、如权利要求11所述的显示器,其特征在于,显示器是有机电致发光器件或者液晶显示器。
13、一种用于制造多晶硅薄膜的掩模,包括:
激光透射区;和
以及激光非透射区,
其中,激光透射区基于激光扫描方向轴线不对称,激光透射区基于预定中心轴线对称,并且激光透射区和激光非透射区交替设置。
14、如权利要求13所述的掩模,其特征在于,激光透射区是全等的线形区域。
15、如权利要求13所述的掩模,其特征在于,激光透射区包括具有线形图案的第一激光透射区和具有线形图案的第二激光透射区,其中第一激光透射区比第二激光透射区长。
16、如权利要求15所述的掩模,其特征在于,激光透射区还包括具有线形图案的第三激光透射区,其中第三激光透射区比第一激光透射区长。
17、如权利要求13所述的掩模,其特征在于,激光透射区具有如下结构:当掩模基于平行于预定中心轴线的轴线移动一定距离时,激光透射区在垂直于激光扫描轴线方向上部分重叠。
18、如权利要求17所述的掩模,其特征在于,在垂直于激光扫描方向轴线的方向上,激光透射区的重叠距离比激光透射区的宽度短。
CNB2004101005988A 2003-10-14 2004-10-14 多晶硅薄膜的制造方法和用多晶硅薄膜制造的显示器件 Active CN100375233C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR71592/2003 2003-10-14
KR71592/03 2003-10-14
KR1020030071592A KR100543007B1 (ko) 2003-10-14 2003-10-14 다결정 실리콘 박막의 제조 방법 및 이를 사용하여 제조된디스플레이 디바이스

Publications (2)

Publication Number Publication Date
CN1617300A true CN1617300A (zh) 2005-05-18
CN100375233C CN100375233C (zh) 2008-03-12

Family

ID=34420666

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004101005988A Active CN100375233C (zh) 2003-10-14 2004-10-14 多晶硅薄膜的制造方法和用多晶硅薄膜制造的显示器件

Country Status (4)

Country Link
US (1) US8486812B2 (zh)
JP (1) JP4849782B2 (zh)
KR (1) KR100543007B1 (zh)
CN (1) CN100375233C (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687328B2 (en) 2005-07-12 2010-03-30 Samsung Mobile Display Co., Ltd. Method of making a polycrystalline thin film, a mask pattern used in the same and a method of making a flat panel display device using the same
CN103537794B (zh) * 2013-10-22 2015-09-30 中山大学 样品做一维精密平动实现二维激光sls晶化的方法
CN107615451A (zh) * 2015-05-19 2018-01-19 株式会社V技术 激光退火方法、激光退火装置以及薄膜晶体管的制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906349B2 (en) * 2003-01-08 2005-06-14 Samsung Electronics Co., Ltd. Polysilicon thin film transistor array panel and manufacturing method thereof
KR100543007B1 (ko) 2003-10-14 2006-01-20 삼성에스디아이 주식회사 다결정 실리콘 박막의 제조 방법 및 이를 사용하여 제조된디스플레이 디바이스
KR100543010B1 (ko) * 2003-10-20 2006-01-20 삼성에스디아이 주식회사 다결정 실리콘 박막의 제조 방법 및 이를 사용하여 제조된디스플레이 디바이스
KR101365185B1 (ko) * 2005-12-16 2014-02-21 삼성디스플레이 주식회사 실리콘 결정화 마스크 및 이를 갖는 실리콘 결정화 장치
JP2008046210A (ja) * 2006-08-11 2008-02-28 Elpida Memory Inc レチクル及びこれを用いた露光方法及び装置、並びにレチクルのパターン作成方法、パターン形成方法及び半導体装置
JP2018107403A (ja) * 2016-12-28 2018-07-05 株式会社ブイ・テクノロジー レーザ照射装置、薄膜トランジスタおよび薄膜トランジスタの製造方法
JP2019036635A (ja) * 2017-08-15 2019-03-07 株式会社ブイ・テクノロジー レーザ照射装置、薄膜トランジスタの製造方法、プログラムおよび投影マスク
FR3106932B1 (fr) * 2020-02-04 2023-10-27 Commissariat Energie Atomique Procede de fabrication d’un substrat structure

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4309225A (en) * 1979-09-13 1982-01-05 Massachusetts Institute Of Technology Method of crystallizing amorphous material with a moving energy beam
JP3204986B2 (ja) * 1996-05-28 2001-09-04 ザ トラスティース オブ コロンビア ユニヴァーシティ イン ザ シティ オブ ニューヨーク 基板上の半導体膜領域の結晶化処理及びこの方法により製造されたデバイス
US6555449B1 (en) * 1996-05-28 2003-04-29 Trustees Of Columbia University In The City Of New York Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidfication
US6177391B1 (en) * 1999-05-27 2001-01-23 Alam Zafar One time use disposable soap and method of making
EP1354341A1 (en) 2001-04-19 2003-10-22 The Trustees Of Columbia University In The City Of New York Method for single-scan, continuous motion sequential lateral solidification
KR100405080B1 (ko) 2001-05-11 2003-11-10 엘지.필립스 엘시디 주식회사 실리콘 결정화방법.
KR100379361B1 (ko) * 2001-05-30 2003-04-07 엘지.필립스 엘시디 주식회사 실리콘막의 결정화 방법
KR100424593B1 (ko) 2001-06-07 2004-03-27 엘지.필립스 엘시디 주식회사 실리콘 결정화방법
TW527732B (en) 2001-08-21 2003-04-11 Samsung Electronics Co Ltd Masks for forming polysilicon and methods for manufacturing thin film transistor using the masks
JP4667682B2 (ja) * 2001-10-16 2011-04-13 ソニー株式会社 半導体装置の製造方法、液晶表示装置の製造方法およびエレクトロルミネッセンス表示装置の製造方法
US6767804B2 (en) * 2001-11-08 2004-07-27 Sharp Laboratories Of America, Inc. 2N mask design and method of sequential lateral solidification
US6660576B2 (en) * 2002-03-11 2003-12-09 Sharp Laboratories Of America, Inc. Substrate and method for producing variable quality substrate material
US6906349B2 (en) * 2003-01-08 2005-06-14 Samsung Electronics Co., Ltd. Polysilicon thin film transistor array panel and manufacturing method thereof
KR100543007B1 (ko) 2003-10-14 2006-01-20 삼성에스디아이 주식회사 다결정 실리콘 박막의 제조 방법 및 이를 사용하여 제조된디스플레이 디바이스

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687328B2 (en) 2005-07-12 2010-03-30 Samsung Mobile Display Co., Ltd. Method of making a polycrystalline thin film, a mask pattern used in the same and a method of making a flat panel display device using the same
CN103537794B (zh) * 2013-10-22 2015-09-30 中山大学 样品做一维精密平动实现二维激光sls晶化的方法
CN107615451A (zh) * 2015-05-19 2018-01-19 株式会社V技术 激光退火方法、激光退火装置以及薄膜晶体管的制造方法

Also Published As

Publication number Publication date
KR100543007B1 (ko) 2006-01-20
KR20050035804A (ko) 2005-04-19
US20050079736A1 (en) 2005-04-14
CN100375233C (zh) 2008-03-12
JP4849782B2 (ja) 2012-01-11
JP2005123573A (ja) 2005-05-12
US8486812B2 (en) 2013-07-16

Similar Documents

Publication Publication Date Title
CN1277155C (zh) 用于连续横向固化的掩模和采用它的结晶方法
CN1240884C (zh) 非晶硅结晶法
CN1239756C (zh) 一种结晶非晶硅的方法
KR100572519B1 (ko) 레이저 결정화 공정용 마스크 및 상기 마스크를 이용한레이저 결정화 공정
CN1638038A (zh) 激光束图案掩模及采用它的结晶方法
CN101184871A (zh) 薄膜的线扫描顺序横向固化
KR100606450B1 (ko) 주기성을 가진 패턴이 형성된 레이저 마스크 및 이를이용한 결정화방법
US7642623B2 (en) Fabrication method for polycrystalline silicon thin film and apparatus using the same
CN1310284C (zh) 薄膜晶体管用非晶硅的结晶方法
KR100631013B1 (ko) 주기성을 가진 패턴이 형성된 레이저 마스크 및 이를이용한 결정화방법
CN1617300A (zh) 多晶硅薄膜的制造方法和用多晶硅薄膜制造的显示器件
CN1683995A (zh) 激光掩模以及使用该激光掩模的结晶方法
CN1574225A (zh) 多晶硅的制作方法和使用多晶硅的开关器件
CN1514469A (zh) 结晶掩模、非晶硅结晶方法及利用其制造阵列基板的方法
CN1897223A (zh) 多晶薄膜的制造方法和掩模图案及显示装置的制造方法
KR100742380B1 (ko) 마스크 패턴, 박막 트랜지스터의 제조 방법 및 이를사용하는 유기 전계 발광 표시 장치의 제조 방법
US7183571B2 (en) Polycrystalline silicon thin film, fabrication method thereof, and thin film transistor without directional dependency on active channels fabricated using the same
CN1637484A (zh) 连续横向结晶装置和使用它结晶硅的方法
KR20040093257A (ko) 다결정 실리콘 박막의 제조 방법 및 이를 사용하여 제조된디스플레이 디바이스
KR20050081231A (ko) 폴리실리콘 박막의 제조 방법 및 이를 사용하여 제조된폴리실리콘을 사용하는 디스플레이 디바이스
TW200933694A (en) A mask used in a sequential lateral solidification process and a solidification method using the mask

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090109

Address after: Gyeonggi Do, South Korea

Patentee after: Samsung Mobile Display Co., Ltd.

Address before: Gyeonggi Do, South Korea

Patentee before: Samsung SDI Co., Ltd.

ASS Succession or assignment of patent right

Owner name: SAMSUNG MOBILE DISPLAY CO., LTD.

Free format text: FORMER OWNER: SAMSUNG SDI CO., LTD.

Effective date: 20090109

ASS Succession or assignment of patent right

Owner name: SAMSUNG DISPLAY CO., LTD.

Free format text: FORMER OWNER: SAMSUNG MOBILE DISPLAY CO., LTD.

Effective date: 20121017

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20121017

Address after: Gyeonggi Do, South Korea

Patentee after: Samsung Display Co., Ltd.

Address before: Gyeonggi Do, South Korea

Patentee before: Samsung Mobile Display Co., Ltd.