CN1577844A - 电源装置 - Google Patents

电源装置 Download PDF

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Publication number
CN1577844A
CN1577844A CNA2004100556964A CN200410055696A CN1577844A CN 1577844 A CN1577844 A CN 1577844A CN A2004100556964 A CNA2004100556964 A CN A2004100556964A CN 200410055696 A CN200410055696 A CN 200410055696A CN 1577844 A CN1577844 A CN 1577844A
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source element
control
supply unit
chip
manufacturing
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CN1324702C (zh
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增井谦次
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Sharp Corp
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Sharp Corp
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Abstract

电源装置1包括通过双极工艺制造的控制IC3和通过MOS工艺制造的电源元件4，并将它们管芯焊接在引脚框架2上，其中它们中的一个的芯片边缘保持与另一个的芯片边缘紧密接触。因此，热量以更高的效率经由这些芯片边缘传导，允许电源元件4中产生的热量快速传导到控制IC3。这避免了MOS半导体易于产生的热诱导破坏。通过MOS工艺制造的电源元件4不需要具有双极PNP晶体管所需的垂直结构，且可以是水平结构，从而电流从芯片上表面的一部分流到另一部分。这可以方便地降低功率损耗。因此，可以在它们芯片的下表面处将电源元件4和控制IC3连接到共用GND电位，并因此可以用诸如Ag糊5的单种类型的管芯焊接糊将它们管芯焊接在一起。这避免了双极半导体易于产生的静电破坏。

Description

电源装置
本非临时申请要求35U.S.C§119(a)下对2004年7月28日日本提交的专利申请No.2003-202301的优先权，在此全文并入以供参考。
发明背景
发明领域
本发明涉及电源装置，它用于稳定地操作TV、VCR、DVD播放器、DVD记录器、个人电脑、其外围设备、各种家用电器等等。
相关技术的描述
如图9所示，在常规电源装置1中，包括PNP晶体管和其它部件的IC15通常集成在单个芯片上，并随后被模制在树脂封装中作为单独装置。
为了减轻通过电源装置1的功率损耗并同时实现稳定的供电，最近市场上推出了一种装置，它具有两个芯片结构，如图10所示，通过双极工艺制造的控制IC16和同样通过双极工艺制造的电源元件17并排设置。
在串联调节器中，其中串联调节器是一种最普通类型的电源装置，通过计算输入和输出电压之间的差随后将结果乘以输出电流就可以确定通过其的功率损耗。因此，通过降低输入和输出电压之间的差可以降低功率损耗。在这种情况中，实现其的有效方法是使用具有垂直结构的PNP结构作为电源元件17。其原因在于，在具有垂直结构的PNP晶体管中，它具有形成于芯片上表面上的集电极和基极并具有形成于芯片的下表面上的发射极，集电极电流从芯片的上表面流到下表面。
但是，尽管具有垂直结构的PNP晶体管在其物理属性中没有固有的发射极-集电极饱和电压，但因此不可能将输入和输出电压之间的差降低到小于发射极-集电极饱和电压。特别是，不能被克服的限制通常认为是约0.3V，虽然它随输出电流的幅度并随PNP晶体管而稍有变化。
因此，进一步降低功率损耗的一种方法被认为是使用MOS工艺制造的电源元件。当MOS工艺制造的电源元件与双极工艺制造的控制IC组合时，与使用双极工艺制造的PNP晶体管的常规实施相比，可以利用MOS半导体的低通态阻抗，以实现低功率损耗。
但是，接合这两种芯片(即通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件)组合成单个封装造成了以下问题：如何避免MOS半导体的热诱导破坏以及如何避免双极半导体的静电破坏。
发明概述
考虑到上述常规经受的困难，根据本发明，电源装置包括通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件，并使控制IC和电源元件模制成单个封装，其中控制IC的芯片边缘保持与电源元件的芯片边缘紧密接触。
采用这种结构，通过双极工艺制造的控制IC的芯片边缘和通过MOS工艺制造的电源元件的芯片边缘保持彼此紧密接触。这使得电源元件产生的热量以更高的效率传导到控制IC。
通过MOS工艺制造的电源元件可以具有水平结构，从而电流从芯片上表面的一部分流到另一部分。因此，控制IC和电源元件可以在它们芯片的下表面处连接到共用GND电位。这允许用管芯焊接糊将通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件一起管芯焊接(die-bonded)在引脚框架上。
适当地，通过双极工艺制造的控制IC的芯片边缘和通过MOS工艺制造的电源元件的芯片边缘是阶梯形状的，或者是一个凸出另一个凹入的楔形。这有助于增加芯片边缘之间的接触面积，从而实现它们之间更紧密的接触。
可以用导电树脂或者用Au线将通过双极工艺制造的控制IC的芯片边缘和通过MOS工艺制造的电源元件的芯片边缘电连接在一起。在使用Au线以避免线路破坏时，Au球需要再次被第一次接合到被第二次接合的Au线上。
通过提供两个或更多通过MOS工艺制造的电源元件，就可以便于设计产生多个输出的电源装置。在通过MOS工艺制造的电源元件中，芯片表面上的Al图案的硬度不足。因此，必须将低应变树脂用作封装材料。
附图概述
图1是示出根据本发明的电源装置实例(四端子串联调节器)的剖视图；
图2是示出通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC的芯片边缘的形状实例的剖视图，其中它们在引脚框架上被管芯焊接；
图3是示出通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC的芯片边缘的形状的另一个实例的剖视图，其中它们在引脚框架上被管芯焊接；
图4是示出通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC的芯片边缘的形状的又一个实例的剖视图，其中它们在引脚框架上被管芯焊接；
图5是示出根据本发明的电源装置的另一个实例(四端子串联调节器)的剖视图；
图6A是剖视图，它示出作为用Au线将通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC电连接在一起的过程中的一个步骤，Au线被第二次接合到被第一次接合的Au球上之前的状态；
图6B是剖视图，它示出作为用Au线将通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC电连接在一起的过程中的一个步骤，Au线被第二接合次到被第一次接合的Au球上之后的状态；
图6C是剖视图，它示出作为用Au线将通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC电连接在一起的过程中的一个步骤，Au球被再次地第一次接合到被第二次接合的Au线上之前的状态；
图6D是剖视图，它示出作为用Au线将通过MOS工艺制造的电源元件和通过双极工艺制造的控制IC电连接在一起的过程中的一个步骤，Au球被再次第一次接合到被第二次接合的Au线上之后的状态；
图7示出在用作调节器时根据本发明的电源装置如何被外部连接的实例；
图8是示出根据本发明的电源装置实例(五端子串联调节器)的剖视图；
图9是示出常规电源装置实例(四端子串联调节器)的剖视图；
图10是示出常规电源装置的另一个实例(四端子串联调节器)的剖视图；
图11示出在用作调节器时常规电源装置如何被外部连接的实例。
具体实施方式
以下将参考附图描述本发明的实施例。图1是示出根据本发明的电源装置(四端子串联调节器)的主要部分的剖视图。如图1所示，电源装置1包括通过双极工艺制造的控制IC3和通过MOS工艺制造的电源元件4，并将它们模制在单个树脂封装11中，其中控制IC3的芯片边缘3a(参见图2)保持与电源元件4的芯片边缘4a(参见图2)紧密接触。在以下描述中，将详细描述该电源装置1的结构。
当作为调节器操作时，电源装置1产生热量，且多数热量由电源元件4产生。电源元件4的过热会破坏其芯片中形成的功率MOS FET。在检测到电源元件4中的异常温度时，控制IC3激活过热保护电路来切断功率MOS FET的栅极电压，从而防止电源元件4的过热。这里，过热保护操作是通过检测从电源元件4传导到控制IC3的热量来实现的，因此必须以这样一种方式设计，即增加它们之间的热传导，从而可以无延迟地启动过热保护操作。
因此，如图2所示，控制IC3的芯片边缘3a和电源元件4的芯片边缘4a形成为阶梯形状，且控制IC3和电源元件4在引脚框架2上被管芯焊接，其中通过芯片边缘3a和4a的彼此啮合而使其保持相互接触。这增加了它们之间的接触面积并实现了它们之间更紧密的接触。结果，热量以更高的效率经由这些芯片边缘3a和4a传导，以便电源元件4产生的热量快速传导到控制IC3。这样，就可以避免MOS半导体易于产生的热诱导破坏。为了实现相同的效果，芯片边缘3a和4a可以被形成为楔状，一个是凸出且另一个凹入，如图3或4所示。
这里，应注意以下几点。当控制IC3已检测到电源元件4中的异常温度时，如果功率MOS FET的栅极电压被立即切断，在切断后大电流立即流过漏极，这可能会导致功率MOS FET的破坏。为了加以避免，控制IC3具有逐步切断栅极电压的功能，从而抑制了漏极电流的增加。较合适地，允许几μs到几十μs的时间以便栅极电压减弱。
在图10所示的常规实例中，为了实现较低的功率损耗，电源元件17由具有垂直结构并通过双极工艺制造的PNP晶体管实现。这有助于获得一种结构，在该结构中电流从芯片表面的一部分流到另一部分。因此，用导电的高熔点焊料18将电源元件17的芯片下表面管芯焊接到引脚框架2。采用这种结构，如图11所示，从第二端子7b获得输出。但是，相对于控制IC16，虽然它被管芯焊接到同一引脚框架2上，但控制IC16的芯片下表面需要与引脚框架2绝缘以防止静电击穿。因此，用不导电的环氧糊19将控制IC16管芯焊接到引脚框架2上。
相反，在通过MOS工艺制造的电源元件4的情况下，电流从漏极流到功率MOS FET的源极，且这里的功率损耗取决于电流流过它时观察到的漏极-源极电阻(通态电阻)。因此，这里，不必采用垂直结构，如常规实例中使用的通过双极PNP晶体管所采用的，并且可以采用水平结构来代替，在该水平结构中，电流从芯片表面的一部分流到另一部分，并由此方便地实现低功率损耗。结果，电源元件4和控制IC3的芯片下表面都可以连接到共用GND电位。因此，如图1所示，可以用诸如Ag糊5的单种的管芯焊接糊将电源元件4和控制IC3管芯焊接于引脚框架2上。这样，就可以避免双极半导体易于产生的静电破坏。
随后，如上所述被管芯焊接在引脚框架2上的控制IC3和电源元件4被电连接在一起。这可以通过使用图1所示的Au线6来实现，或者通过使用图5所示的导电树脂12来实现。通常，导电树脂12是优选的，因为使用Au线易于引起线路破坏，该线路破坏可归因于形成为芯片表面上的导体图案的Al图案和Au线之间接合处产生的金属间化合物。
在使用Au线6的情况中，如图6A到6D所示，在第一次被接合的Au球61顶上接合上第二次被接合的Au线6(参见图6A和6B)，随后在这些第二次被接合的Au线6顶上，再接合上第一次被接合的Au球62(参见图6C和6D)。这有助于加强接合。
图1中，标号7a、7c和7c分别标识第一、第三和第四端子，它们每一个都被设置成与引脚框架2分开，而标号7b标识第二端子，它被形成为与引脚框架2连通。电源元件4的芯片表面通过Au线8和9被电连接到第一和第三端子7a和7c，而控制IC3的芯片表面通过Au线10被电连接到第四端子7d。
除了第一到第四端子7a到7d的顶部，引脚框架2上提供的所有上述组件，都被树脂封住并被模制成单个树脂封装11。这样，可以获得最终产品的电源装置1。这里，为了减轻芯片表面上封住材料的干扰，必须使用低应变树脂作为封装材料。原因在于，如果通过MOS工艺制造的电源元件4被封于普通使用的树脂中，则芯片表面上形成的Al图案倾向于变形，因为其硬度低于常规使用的通过双极工艺制造的PNP晶体管中的对应物。
如图8所示，可以用Ag糊5在引脚框架2上将总共三个芯片管芯焊接在一起。这里，在三个芯片中，两个是通过MOS工艺制造的电源元件(电源元件4和13)的芯片，而一个是控制IC3的芯片。通过使用Au线6等，电源元件4和控制IC3被电连接在一起，且电源元件13和控制IC3被电连接在一起。此外，通过使用Au线8、9、10和14，这些芯片的表面被连接到第一、第三、第四和第五端子7a、7c、7d和7e。随后，所有这些组件都被模制成单个树脂封装11。这样，可以方便地实现接合了单个芯片的控制IC3但具有两个输出端子(第三和第五端子7c和7e)的电源装置1(五端子串联调节器)。以类似的方式，通过增加以MOS工艺制造的电源元件的数量，可以设计多个输出的电源装置。
图7是示出当用作调节器时如何外部连接上述电源装置1(四端子串联调节器)的实例的电路图。第一端子7a用作DC输入端子，并连接到直流电源和一并联的稳定输入电容CIN。将第二端子7b接地。第三端子7c用作DC输出端子，并连接到诸如电子仪器的负载。在第二和第三端子7b和7c之间连接了稳定输出电容C0。第四端子7d用作输出开/关控制输入端子，并连接到TTL或C-MOS标准逻辑电路或者类似物。
通过计算输入电压VIN和输出电压V0之间的差，随后将结果乘以输出电流I0来确定电源装置1的内部功率损耗。因此，为了设计电源装置1以提供较低的功率损耗，必须降低输入和输出电压之间的差。输入和输出电压之间的差取决于电源元件4的芯片中形成的功率MOS FET的漏极-源极通态电阻。
通常，PNP晶体管具有范围从约0.3V到约0.5V的发射极-集电极饱和电压，功率MOS FET具有约0.1Ω的漏极-源极通态电阻，虽然这些可以随漏极电流而改变。因此，当输出电流I0是1A时，将通过双极工艺制造的PNP晶体管用作电源元件的常规电源装置提供范围从约0.3W到约0.5W的内部功率损耗，本发明的电源装置1提供约0.1W的内部功率损耗。
如上所述，本发明的电源装置1允许输入和输出电压之间的差被设置成比常规实施中使用通过双极工艺制造的PNP晶体管时的更小。因此，本发明的电源装置1有助于实现比常规所能实现的更低的功率损耗。
此外，在本发明的电源装置1中，作为使用MOS半导体的一项益处的高响应提供以下优点。首先，可以用极好的瞬变响应应付输出电流I0的高速变化。其次，在将电源装置1用作调节器时，为了稳定目的而连接的输出电容器C0和输入电容器CIN可以被提供比常规所需的电容更低的电容。当这些电容器被提供了较高的电容时，它们的成本变得较高，总体上这不利地影响了调节器的成本。因此，电容器的电容越低，就可以地设计越廉价的电源。
双极半导体具有温度响应，从而温度越高，其电流放大因数(hFE)越高，MOS半导体具有温度响应，从而温度越高，其通态电阻越高，使得漏极电流更难流动。特别是，在常规双芯片电源装置1中，与图10所示的一个相类似，它使用都是通过双极工艺制造的控制IC16和电源元件17，当温度上升时，这两个芯片的hFE都增加。相反，在本发明的电源装置1中，电源元件4和控制IC3针对温度变化相反地响应。
如上所述，根据本发明，电源装置包括通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件，并将它们管芯焊接在引脚框架上，其中它们一个的芯片边缘保持与另一个的芯片边缘紧密接触。因此，热量以更高的效率经由这些芯片边缘传导，允许电源元件中产生的热量快速传导到控制IC。这有助于避免MOS半导体易出现的热诱导破坏。
此外，通过MOS工艺制造的电源元件不需要具有垂直结构，而PNP晶体管(即双极半导体)则需要，因此通过采用水平结构前者有助于方便地实现较低的功率损耗，在该水平结构中电流从芯片表面的一部分流到另一部分。结果，电源元件和控制IC的芯片后表面都可以连接到共用GND电位，因此可以用例如Ag糊的单种类型的管芯焊接糊将电源元件和控制IC一起管芯焊接在引脚框架上。这有助于避免双极半导体易出现的静电破坏。

Claims (9)

1.一种电源装置，其特征在于，包括通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件，其中控制IC和电源元件被模制在单个封装中，其中控制IC的芯片边缘保持与电源元件的芯片边缘的紧密接触。
2.如权利要求1所述的电源装置，其特征在于，用管芯焊接糊将所述通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件一起管芯焊接到引脚框架上。
3.如权利要求1所述的电源装置，其特征在于，所述通过双极工艺制造的控制IC的芯片边缘和通过MOS工艺制造的电源元件的芯片边缘是阶梯形状的。
4.如权利要求1所述的电源装置，其特征在于，所述通过双极工艺制造的控制IC的芯片边缘和通过MOS工艺制造的电源元件的芯片边缘是楔形的，一个凸出而另一个凹入。
5.如权利要求1所述的电源装置，其特征在于，用导电树脂将通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件电连接在一起。
6.如权利要求1所述的电源装置，其特征在于，用Au线将通过双极工艺制造的控制IC和通过MOS工艺制造的电源元件电连接在一起。
7.如权利要求6所述的电源装置，其特征在于，在第二次被接合的诸Au线上再接合上第一次被接合的诸Au球。
8.如权利要求1所述的电源装置，其特征在于，设置了两个或更多通过MOS工艺制造的电源元件。
9.如权利要求1所述的电源装置，其特征在于，所述封装由低应变树脂制成。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103617973A (zh) * 2013-11-08 2014-03-05 张轩 一种高温使用的引线框架

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7635956B2 (en) * 2006-01-06 2009-12-22 Active-Semi, Inc. Primary side constant output voltage controller
JP4858290B2 (ja) * 2006-06-05 2012-01-18 株式会社デンソー 負荷駆動装置
KR100777160B1 (ko) 2006-11-01 2007-11-16 주식회사 케이이씨 휴대폰용 전원 회로 및 이의 반도체 패키지
JP5132407B2 (ja) * 2008-04-25 2013-01-30 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP5341473B2 (ja) * 2008-10-31 2013-11-13 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置およびその製造方法
JP2011165903A (ja) * 2010-02-10 2011-08-25 Rohm Co Ltd 半導体モジュールおよび半導体モジュールの製造方法
JP4985810B2 (ja) * 2010-03-23 2012-07-25 サンケン電気株式会社 半導体装置
US10217723B2 (en) 2016-10-07 2019-02-26 Mediatek Inc. Semiconductor package with improved bandwidth
US11031343B2 (en) * 2019-06-21 2021-06-08 International Business Machines Corporation Fins for enhanced die communication
DE212021000149U1 (de) * 2020-04-27 2022-04-11 Rohm Co., Ltd. Halbleiterbauteil
US20230369185A1 (en) * 2020-10-02 2023-11-16 Rohm Co., Ltd. Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3157362B2 (ja) * 1993-09-03 2001-04-16 株式会社東芝 半導体装置
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
JP4040229B2 (ja) 1999-02-14 2008-01-30 矢崎総業株式会社 交流用スイッチングデバイス
US6137165A (en) * 1999-06-25 2000-10-24 International Rectifier Corp. Hybrid package including a power MOSFET die and a control and protection circuit die with a smaller sense MOSFET
US6252305B1 (en) * 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103617973A (zh) * 2013-11-08 2014-03-05 张轩 一种高温使用的引线框架

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