CN1577826A - 半导体装置及混合集成电路装置 - Google Patents

半导体装置及混合集成电路装置 Download PDF

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CN1577826A
CN1577826A CNA2004100617046A CN200410061704A CN1577826A CN 1577826 A CN1577826 A CN 1577826A CN A2004100617046 A CNA2004100617046 A CN A2004100617046A CN 200410061704 A CN200410061704 A CN 200410061704A CN 1577826 A CN1577826 A CN 1577826A
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integrated circuit
substrate
semiconductor device
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CN100346476C (zh
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落合公
武真人
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Semiconductor Components Industries LLC
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Abstract

一种半导体装置及混合集成电路装置。目前难于有效地使树脂模制的半导体元件产生的热量排放,该半导体元件会因热应力而损坏。在本发明中,具有连结在岛23的通用引线24M等,通用引线24M等的一部分自树脂密封体31露出。露出的通用引线24M等具有连结部30,在固定安装半导体装置32时,通用引线24M等通过号疗5桥接。由此,固定安装在岛23上面的集成电路芯片22产生的热量通过通用引线24M等排放到树脂密封体31的外部。此时,在本发明中,通过增大通用引线24M等的表面积,可进一步提高散热性能。

Description

半导体装置及混合集成电路装置
技术领域
本发明涉及使用具有单独引线及通用引线的引线架的半导体装置,特别是涉及为提高散热效果而在通用引线的外侧部分设置连结部,并用焊料(焊锡等)桥接通用引线的半导体装置。
背景技术
最近,为了对应电子设备的小型化,正在追求半导体装置的高密度化。为此,将把各种电路LSI化的集成电路芯片安装在引线架上,并用树脂密封该引线架上的集成电路芯片。
参照图8~10说明现有半导体装置。
图8是安装有集成电路芯片的现有引线架的平面图。图9是使用该引线架的半导体装置的立体图。图10是将使用该引线架的半导体装置固定安装在印刷线路板上的图。
如图8所示,引线架1具有安装集成电路芯片2的岛3和构成外部电极端子的多个引线4A、4B、4C...、5A、5B、5C...,引线4A等以一定间隔排列为DIP状。
在引线架1的岛3上安装有集成电路芯片2。设在集成电路芯片2上的各电极6A、6B、6C...、7A、7B、7C...和引线4A等由金属细线8A、8B、8C...、9A、9B、9C...连接。
如图9所示,树脂密封体10形成为引线4A等的外侧部分露出外部,完成半导体装置11。
如图10所示,在半导体装置11中,引线4A等的前端部利用焊料(焊锡等)安装在印刷线路板12上的印刷配线14A、14B、14C等上。
专利文献1:特开2001-24001号公报
如上所述,在半导体装置中,由于集成电路芯片逐年大型化,甚至电力电路也被集成化了,故集成电路芯片等产生的热量有可能使集成电路芯片、半导体装置热损坏。因此,必须提高半导体装置的散热性能,但由于集成电路芯片和固定安装该集成电路芯片的岛由树脂模制为一体,故存在不能充分散热的问题。另外,由于引线架的多针化,使引线架变薄,阻碍散热性能。
发明内容
鉴于上述问题,本发明提供一种半导体装置,其包括:岛,其固定安装半导体元件;多个单独引线,其前端部延伸设置到该岛的附近;多个通用引线,其连结在所述岛上;树脂密封体,其用树脂模制所述半导体元件、所述岛、所述单独引线及所述通用引线,在自所述树脂密封体露出的所述通用引线上设有连结部。利用该结构,通过与岛连结的通用引线,可提高树脂密封体向外部的散热性能。
在本发明中,提供一种混合集成电路装置,其包括:导电图案,其至少设于混合集成电路衬底的表面上;半导体元件或无源元件,其固定安装在所述导电图案上;引线,其与所述导电图案连接,并形成输出或输入,延伸设置在外部;树脂密封体,其由利用传递模模制覆盖所述衬底的至少表面的热硬性树脂构成,所述引线在自所述树脂密封体露出的区域具有利用连结部连结的通用引线。利用该结构,即使在由传递模模制混合集成电路衬底的混合集成电路装置中,也可以提高树脂密封体向外部的散热性能。
附图说明
图1是说明用于本发明实施例1的半导体装置的引线架的平面图;
图2是说明本发明实施例1的半导体装置的立体图;
图3是说明将本发明实施例1的半导体装置固定安装在印刷线路板上的状况的立体图;
图4是将本发明实施例1的半导体装置固定安装在印刷线路板上的状况的局部放大立体图;
图5是说明本发明实施例2的混合集成电路衬底的(A)剖面图,(B)平面图;
图6是说明本发明实施例2的混合集成电路装置的(A)剖面图,(B)平面图;
图7是说明本发明实施例2的混合集成电路装置的立体图;
图8是说明用于现有半导体装置的引线架的平面图;’
图9是说明现有半导体装置的立体图;
图10是说明将现有半导体装置固定安装在印刷线路板上的状况的立体图。
具体实施方式
首先参照附图1~4说明实施例1的本发明的半导体装置。图2是说明本实施例的半导体装置的立体图;图3是说明将本实施例的半导体装置固定安装在印刷线路板上的状况的立体图;图4是将本实施例的半导体装置固定安装在印刷线路板上的状况的局部放大立体图;
如图1所示,引线架21包括安装集成电路芯片22的岛23和构成外部电极端子的多个单独引线24A、24B、24C...、25A、25B、25C...以及连结在岛23上的多个通用引线24M、24N、24P、24Q、25M、25N、25P、25Q。
岛23位于引线架21的中央。在岛23的两侧,以一定间隔DIP状排列多个单独引线24A等和通用引线24M等。在通用引线24M等中,一端连结在岛23,另一端作为外侧部向岛23的外侧延伸设置。通用引线24等与岛23的两侧的列的中央邻接排列。单独引线24A等分别以相同数量排列在通用引线24M等的两侧。
在本实施例中,由连结部30连接通用引线24M等的外侧部分。通常通用引线24M等和单独引线24A等引线间由连杆29连结,阻止树脂模制时树脂的泄漏。在本实施例中,在连杆29和通用引线24M等的前端的中间位置设置连结部30。通用引线24M等一端连结在岛23上,故电位为通用电位(接地电位),即使设置连结部30也不会产生使用上的问题。
在上述引线架21的岛23上使用银膏等导电性粘接剂固定安装有集成电路芯片22。设于集成电路芯片22的多个电极26A、26B、26C...、27A、27B、27C...和单独引线24A等由金属细线28连接。接地电位的电极26M、26N...、27M、27N...与通用引线24M等由金属细线28连接。
然后,进行传递模模制,用树脂覆盖引线架21、集成电路芯片22和各引线的内部部分,形成树脂密封体31。另外,连杆29在模制后切断除去,单独引线24A等电气独立。因此,通用引线24M等形成由连结部30连结的状态。
如图2所示,在树脂密封体31的两侧突出的单独引线24A等及通用引线24M等分别弯曲整形,形成鸥翼形。此时,连结部30位于通用引线24M等的垂直部分。
如图3所示,在完成的半导体装置32中,自树脂密封体31露出的单独引线24A等及通用引线24M等利用焊料(焊锡等)固定安装在印刷线路板33的对应印刷配线34A、34B、34C...上。
如图4所示,固定安装时,在由连结部30连结的通用引线24M等中,在弯曲部附着大量导电性粘接剂例如焊料(焊锡等)35。然后通过介由连结部30将焊料(焊锡等)35附着在引线间的空间,对通用引线24M等进行桥接。这利用焊料(焊锡等)35的表面张力实现。在通用引线24M中,引线间由焊料(焊锡等)35充填,作为一个大的引线起作用。
根据该结构,通用引线24M等表面积增大且较厚地形成。因此,集成电路芯片22产生的热量自岛23向由焊料(焊锡等)35桥接的通用引线24M等传递。然后,产生的热量向树脂密封体31的外部散热。
根据实际实验的结果可知,用连结部30连结通用引线24M等的结构,与不设连结部30的现有结构相比,散热效果达到两倍以上。
下面参照图5~图7说明实施例2的本发明的混合集成电路装置。图5(A)是说明本实施例的混合集成电路衬底的剖面图,图5(B)是说明本实施例的混合集成电路衬底的平面图。
如图5(A)所示,混合集成电路衬底41考虑到安装在衬底41上的半导体元件等产生的热量,采用散热性能好的衬底。在本实施例中,就使用铝(以下称A1)衬底41的情况进行说明。另外,虽然在本实施例中使用Al衬底作为衬底41,但不必特别限定。
例如使用印刷线路板、陶瓷衬底、金属衬底等作为衬底41也可以实现本实施例。且作为金属衬底也可使用Cu衬底、Fe衬底、Fe-Ni衬底或AlN(氮化铝)衬底等。
衬底41表面进行阳极氧化,其上在整面上还形成有绝缘性好的例如环氧树脂构成的绝缘树脂42。
然后,在该树脂42上形成由Cu箔构成的导电通路43a。在导电通路43a上通过导电性材料例如焊料(焊锡等)50安装有功率晶体管、小信号晶体管或IC等有源元件45和片状电阻、片状电容等无源元件46。另外,有源元件45等也可用银膏等电连接。在IC等有源元件45面朝上安装的情况下,利用金属细线47连接IC等的电极和导电通路43a。设于衬底41的外周部的外部连接用端子48通过焊料(焊锡等)50等连接由Cu或Fe-Ni等导电性部件构成的外部引线49。
如图5(B)所示,在衬底41上形成有导电通路43a。
通过在衬底41的近旁部位用连杆44连结外部引线49,阻止树脂模制时树脂的漏泄。外部引线49的一部分在连杆44和外部引线49的前端之间具有连结部54,并用作通用引线55A、55B、55C、55D。该通用引线55A等由于利用连结部54连结,故电位为通用电位(接地电位)。
图6(A)是说明本实施例的混合集成电路装置的剖面图,图6(B)是说明本实施例的混合集成电路装置的平面图。
如图6(A)所示,在衬底41整面上形成绝缘树脂42后,在树脂42上形成复杂的电路,通过外部连接用端子48将外部引线49粘接在衬底41上。通过使用热硬性树脂的传递模模制,形成树脂密封体51。热硬性树脂粘性低且硬化温度低于焊料(焊锡等)50的熔点例如183℃。由此,例如直径约40um左右的Al细线不会因传递模模制时热硬性树脂的流入而躺倒、断线或折曲。
在本实施例中,衬底41的冲切面56侧配置于树脂密封体51的背面57侧。也就是说,在衬底41的冲切面56的相对面58侧形成导电通路43a等。在衬底41的冲切面56侧形成冲切衬底41时的曲面59。在传递模模制时,自衬底41的底面充填树脂,此时,利用衬底41的曲面59可流畅地充填树脂。
如图6(B)所示,孔52形成于衬底41的外周部53(参照图5(A))即衬底41上未形成电路等的部分。由于孔52形成于衬底41的外周部53且形成于绝缘树脂42之上,故形成品质、耐湿性方面没有问题的结构。而且,外周部53是为一个个印刷衬底41时确保与电路区域的距离而设置的。因而,该外周部53为静区,将此处有效利用为在传递模模制时固定衬底41的销的抵接区域,故由此具有可有效利用安装区域的优点。
在本实施例中,由于使用导热系数好的衬底作为衬底41,故可将衬底41整体活用作散热器,可防止安装的元件的热量上升。而且,由于产生的热量可通过衬底41散热到外部。故本实施例与基于引线架的半导体装置相比,由于金属衬底41被直接模制,因此散热性能好,可改善电路特性。
图7是说明本实施例的混合集成电路装置的立体图;
如图7所示,自树脂密封体51的单侧突出的外部引线49分别弯曲整形,形成鸥翼状。此时,通用引线55A等也形成鸥翼形状,连结部54位于通用引线55A等的垂直部分。然后,如实施例1的图4所示,外部引线49由焊料(焊锡等)固定安装在印刷线路板的对应印刷配线上。
然后,如实施例1所述,在通用引线55A等中,在引线间的空间通过连结部54附着焊料(焊锡等)50,进行桥接。这一点利用焊料(焊锡等)50的表面张力来实现。在通用引线55A等中,引线间由焊料(焊锡等)50充填,作为一个大的引线起作用。
根据该结构,外部引线49的通用引线55A等表面积增大且形成得较厚。且有源元件45或无源元件46产生的热量自衬底41向由焊料(焊锡等)50桥接的通用引线55A等传递。然后,产生的热量散热到树脂密封体51的外部。
另外,在实施例2中,就自衬底的单侧延伸设置外部引线的情况进行了说明,但不限于这种情况。例如在自衬底的相对的两侧延伸设置外部引线的情况下,也可以提高上述的散热性能。另外,只要在本发明的要旨范围内,即可进行各种变更。
在本发明的半导体装置中,将集成电路芯片固定安装在岛上,利用通用引线、连结部及桥接该通用引线问的焊料可高效地将集成电路芯片产生的热量排出到树脂密封体的外部。根据该结构,可防止集成电路芯片或半导体装置自身热损坏。
在本发明的半导体装置中,即使在引线多针化的情况下或由极薄的金属板构成多针化的情况下,也可以得到由桥接的焊料增大通用引线的宽度的效果。可等效地加厚通用引线的厚度,提高散热性能。
在本发明的半导体装置中,通过将单独引线和通用引线形成鸥翼形状,可在通用引线的弯曲部附着大量的焊料。由此可利用焊料的表面张力,实现在由焊料固定安装通用引线和印刷配线时,容易桥接通用引线之间的结构。
在本发明的混合集成电路装置中,在金属衬底上面形成绝缘树脂。在该树脂上面形成导电图案,固定有源元件或无源元件,覆盖它们形成树脂密封体。有源元件或无源元件产生的热量除通过金属衬底散热外,还可通过自树脂密封体露出的外部引线散热。此时,通过在外部引线中形成通用引线,可进一步提高散热性能。

Claims (8)

1、一种半导体装置,其包括:岛,其固定安装半导体元件;多个单独引线,其前端部延伸设置到该岛的附近;多个通用引线,其连结在所述岛上;树脂密封体,其用树脂模制所述半导体元件、所述岛、所述单独引线及所述通用引线,其特征在于:在自所述树脂密封体露出的所述通用引线上设有连结部。
2、如权利要求1所述的半导体装置,其特征在于:在将所述通用引线利用导电性粘接剂固定安装在配线部时,所述通用引线在所述连结部和所述配线部之间由所述导电性粘接剂桥接。
3、如权利要求1所述的半导体装置,其特征在于:所述通用引线连结在所述岛的两侧。
4、如权利要求1所述的半导体装置,其特征在于:所述通用引线整形为鸥翼形状。
5、一种混合集成电路装置,其包括:导电图案,其至少设于混合集成电路衬底的表面上;半导体元件或无源元件,其固定安装在所述导电图案上;引线,其与所述导电图案连接,并形成输出或输入,延伸设置在外部;树脂密封体,其由利用传递模模制覆盖所述衬底的至少表面的热硬性树脂构成,其特征在于:所述引线在自所述树脂密封体露出的区域具有利用连结部连结的通用引线。
6、如权利要求5所述的混合集成电路装置,其特征在于:在将所述通用引线利用导电性粘接剂固定安装在配线部时,所述通用引线在所述连结部和所述配线部之间由所述导电性粘接剂桥接。
7、如权利要求5所述的混合集成电路装置,其特征在于:所述通用引线整形为鸥翼形状。
8、如权利要求5所述的混合集成电路装置,其特征在于:所述衬底由金属衬底构成,所述衬底自形成所述导电图案的面的相对面冲切,该冲切面配置在所述树脂密封体的背面侧。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100461554C (zh) * 2004-02-12 2009-02-11 雅斯高股份有限公司 分立电子组件和相关装配方法
CN107709226A (zh) * 2015-04-28 2018-02-16 伊文萨思公司 将侧表面触件耦合到电路平台

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101340512B1 (ko) * 2006-12-01 2013-12-12 삼성디스플레이 주식회사 반도체 칩 패키지 및 이를 포함하는 인쇄 회로 기판어셈블리
US8116102B2 (en) * 2007-12-26 2012-02-14 Infineon Technologies Ag Integrated circuit device and method of producing
JP5634033B2 (ja) * 2008-08-29 2014-12-03 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 樹脂封止型半導体装置とその製造方法
DE102010002950A1 (de) * 2010-03-17 2011-09-22 Robert Bosch Gmbh Schaltungsanordnung und zugehöriges steuergerät für ein kraftfahrzeug
DE102010002945A1 (de) * 2010-03-17 2011-09-22 Robert Bosch Gmbh Schaltungsanordnung und zugehöriges steuergerät für ein kraftfahrzeug
JP5755186B2 (ja) * 2012-06-25 2015-07-29 三菱電機株式会社 半導体装置の製造方法および半導体装置
US11437304B2 (en) 2014-11-06 2022-09-06 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9397017B2 (en) 2014-11-06 2016-07-19 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9408301B2 (en) 2014-11-06 2016-08-02 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1195782A (en) * 1981-07-06 1985-10-22 Mikio Nishikawa Lead frame for plastic encapsulated semiconductor device
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
JP2536436B2 (ja) * 1993-11-19 1996-09-18 日本電気株式会社 モ―ルド型半導体装置
US6011694A (en) * 1996-08-01 2000-01-04 Fuji Machinery Mfg. & Electronics Co., Ltd. Ball grid array semiconductor package with solder ball openings in an insulative base
US6159764A (en) * 1997-07-02 2000-12-12 Micron Technology, Inc. Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
US5903050A (en) * 1998-04-30 1999-05-11 Lsi Logic Corporation Semiconductor package having capacitive extension spokes and method for making the same
KR100411206B1 (ko) * 2001-02-19 2003-12-18 삼성전자주식회사 반도체 패키지

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100461554C (zh) * 2004-02-12 2009-02-11 雅斯高股份有限公司 分立电子组件和相关装配方法
CN107709226A (zh) * 2015-04-28 2018-02-16 伊文萨思公司 将侧表面触件耦合到电路平台
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