CN1568537A - 金属氧化物的选择去除 - Google Patents

金属氧化物的选择去除 Download PDF

Info

Publication number
CN1568537A
CN1568537A CNA028145313A CN02814531A CN1568537A CN 1568537 A CN1568537 A CN 1568537A CN A028145313 A CNA028145313 A CN A028145313A CN 02814531 A CN02814531 A CN 02814531A CN 1568537 A CN1568537 A CN 1568537A
Authority
CN
China
Prior art keywords
metal oxide
oxide layer
semiconductor substrate
chemicals
degrees centigrade
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA028145313A
Other languages
English (en)
Other versions
CN1305117C (zh
Inventor
克里斯托弗·C·霍布斯
菲利普·J·托宾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1568537A publication Critical patent/CN1568537A/zh
Application granted granted Critical
Publication of CN1305117C publication Critical patent/CN1305117C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28238Making the insulator with sacrificial oxide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

使用气态HCl加热的组合而并没有rf,去除用作栅介质(22)的金属氧化物。有效地去除了不位于栅极(18)之下的优选为氧化铪的金属氧化物。使用HCl导致没有去除在金属氧化物之下的界面氧化物(25)。去除界面氧化物以消除金属并由另一种界面氧化物层(27)替代界面氧化物。由此只是通过界面氧化物(27)而不通过金属氧化物执行随后的注入步骤。由此,避免了与通过金属氧化物注入有关的问题。

Description

金属氧化物的选择去除
相关申请
本申请涉及以下被转让给受让人的公开专利:
2001年10月9日公开的发明人为Hobbs等、发明名称为“SelectiveRemoval of a Metal Oxide Dielectric(金属氧化物介质的选择去除)”的美国专利6,300,202。
背景技术
在发展用作栅绝缘层的高k介质中,这种高k介质最常见的类型是金属氧化物。这些金属氧化物具有比原有氧化硅栅绝缘体高很多的介电常数。在发展这些金属氧化物过程中,通过这些金属氧化物以注入掺杂源/漏成为了问题。因为金属氧化物吸收并阻止了被注入掺杂剂的进展,由此,通过这些金属氧化物的注入是困难的。这导致不希望的浅源/漏区,而且在PN结中将变得不怎么突变(abrupt)。增加注入能量可获得源/漏所需的深度,但仍减小形成的PN结的突变性。不突变的PN结的缺点在于由较大面积低浓度掺杂引起的增大的掺杂区电阻和较高的漏电(current leakage)。较高的漏电起因于进一步延伸并包围具有缺陷的更大面积的耗尽区。而且,为了与源/漏的接触,该金属氧化物最终必须被去除。
为了克服通过金属氧化物注入的缺陷,试图在执行源/漏注入之前去除金属氧化物。但是,去除该金属氧化物非常难于控制。如果蚀刻金属氧化物持续时间过长,那么将去除了下面的界面氧化物且下面的硅会出现凹坑。由此,需要提供一种去除金属氧化物的技术,其不会导致该硅衬底出现凹坑。
附图说明
通过附图中的实例说明本发明,且不限制本发明,其中相同的标号代表相同的元件,其中:
图1-7示出了按照本发明的优选实施例的部分半导体晶片的连续剖面;和
图8示出了用于执行用在获得如图1-7所示的剖面的部分方法的设备。
本领域技术人员可以理解,为了简化和清晰,在附图中的元件仅是说明性的,其无需按比例示出。例如,在附图中某些元件的尺寸相对于另一些元件可能被放大以有助于提高对本发明实施例的理解。
具体实施方式
在本发明的实施例中,在金属氧化物层上通过流过无水HCl(HCl)实现金属氧化物的选择去除,同时它接收辐照热量。有效地去除金属氧化物的同时保留了在栅极下面的界面氧化层并保护了下面的硅。在没有高频电磁波供给能量的情况下在晶片上流过HCl。在这种情况下,高频意为射频或微波辐射,并且在这里通常表示为“rf”。
图1示出了包括硅衬底12、界面氧化层14、金属氧化层16、栅极18和抗反射涂层(ARC)20的器件结构10。直接位于栅极18之下的区域是获得高耦合度的关键区域和使得界面氧化层14变薄的非常重要的区域。金属氧化物优选为铪氧化物并大约为30埃厚。栅极18可以是任何适当的栅极材料并优选为多晶硅。ARC 20是任何适当的抗反射涂层材料并优选为富硅氮化物。在栅极18下的界面氧化物层14比不在栅极18下的源/漏区中的薄很多。栅极18用作对氧的掩模,由此防止在栅极下区域中界面氧化层14的额外生长。
图2示出了在除了栅极18之下的区域以外的区域中的金属氧化物16去除之后的器件结构10。金属氧化物16的保留部分作为仅在栅极18之下存在的金属氧化物22示出。通过把它放置到例如图8所示的反应室中来选择性去除金属氧化物16。
图8示出了包括反应室24、无水氯化物源28、支撑30、辐照源32和其中存在器件结构10的晶片34的设备26。晶片34被放置在支撑30上并接收来自辐照源32的热量。晶片34接收来自辐射源32的热量的同时,在晶片34上流过HCl。没有rf能量施加到HCl。结果是去除了暴露的金属氧化物16并保留了界面氧化层14。现已发现,对晶片34的有效热量范围是600-800摄氏度。更高温度可能也是有用的,尤其是对非常低的HCl分压(partial pressure)。随着温度增加到温度范围的最高端,趋向更多地去除栅极18下的金属氧化物。这是通常与各向同性蚀刻关联的钻蚀(undercutting)类型。在该温度范围的下端,金属氧化物的去除程度是很低的。已经发现,有效地提供金属氧化物的优良去除率和栅极18下的金属氧化物的最小钻蚀的优良温度是650摄氏度。发现操作的优良范围是625-675摄氏度。在50托(torr)的压力和以每分钟一标准公升(SLM)的流速施加辐照和HCl的组合大约60秒。而且与HCl一起流动的是9SLM的、作为惰性气体工作的氮气(N2)。其它惰性气体也是有效的。
还发现时间、温度、压力和流速的其它组合对于有效去除金属氧化物同时没有显著的钻蚀也是有效的。在实践中,在从辐照源32施加热量之前流过HCl。作为替换,例如通过热板之间的对流或接触来获得热量,替代如图8所示的辐照。辐照加热的优点在于它提供了相对较快的上升时间和下降时间。
如图3示出在去除ARC层20之后的器件结构10。通过干法蚀刻或湿法蚀刻去除ARC 20。干法蚀刻导致暴露的牺牲氧化层14的某种轰击,并甚至可能到达衬底12的硅。通过使用湿法蚀刻避免了这种可能。另一种可能是在选择性去除金属氧化物16之前去除ARC 20。热磷酸对用于由富硅氮化硅构成的ARC层的湿法蚀刻是有效的。
图4示出了把器件结构10短暂湿浸入氢氟酸(HF)之后的器件结构10。HF浸泡的目的是通过去除界面氧化物14保留在栅极18之下的薄界面氧化物层25来完全清除界面氧化物中存在的聚集金属。时间大约为30秒。可以按照HF的浓度调整时间。它应足够长以确保去除界面氧化物层14,还应不长到使衬底12的下面硅变粗糙。不位于栅极18之下区中的界面氧化物层14的厚度在大约15-35埃的范围。在HF浸泡之后,用去离子水漂洗器件结构10,且器件结构10可以暴露到空气中。图5示出了结果,器件结构10具有不位于栅极18之下区中的具有大约8-15埃厚度的界面氧化层27。
图6示出了在两次注入之后的器件结构10。一种注入是公知的含卤素(halo)注入并形成区域40和42。另一种注入是源漏延伸注入并形成源漏区域44和46。区域44和46是与衬底12的导电类型相反的导电类型,而含卤素区40和42的导电类型与衬底12的导电类型相同。衬底12代表P阱或N阱并且可以在绝缘层上,即常见的公知为SOI的衬底。含卤素区40和42用于提高穿通(punchthrough)。
图7示出了在形成侧壁间隔物48和50及重源/漏注入之后的器件结构10。重源/漏注入导致重掺杂接触区52和54。直接邻近于直接位于栅极18之下区的部分区域52和54是相对轻掺杂的。区域54和52的掺杂比区域40和42的掺杂浓度高很多。由此如图7所示的器件结构10是完整的晶体管。
除HCl之外的无水卤化物可以提供同样的结果。例如气态HF可以在相似条件下有效去除金属氧化物。与HCl相比HF的缺点是HF对氧化硅的选择性很低。由此在金属氧化物穿透(penetrate)之后,用HF去除界面氧化物14的速度比用HCl去除界面氧化物的速度快。而且,金属氟化物比金属氯化物的挥发性小,导致对金属氧化物的去除不怎么有效。由此,使用HCl被认为是比使用气态HF更好。其它有效的示例性气态卤化物是HI、HBr、I2、Br2、Cl2和F2。氧化铪具有作为高k介质相对于多晶硅稳定的特定优点。与许多其它高k介质相比,淀积多晶硅时它不怎么与多晶硅反应。
已经发现缺少HCl的rf激活是有利的。发现使用rf的包括氯气的典型等离子体蚀刻会使衬底出现凹坑。凹坑被认为是通过rf供给能量的氯气引起的表面轰击、与化学蚀刻不同的物理蚀刻的结果。缺少rf只提供了金属氧化物的化学去除。本发明的化学去除被认为是通过在气态卤化物(优选HCl)和金属氧化物之间引起反应以产生部分HCl和金属氧化物中金属的副产品来起作用的。而且副产品是挥发性的,由此它易于从反应室并从晶片上被去除。因为凹坑可能导致不均匀的注入掺杂,不均匀的注入掺杂导致电阻增加和/或降低晶体管的其它性能,所以成功避免凹坑是非常有利的。
以上参考特定实施例介绍了好处、其它优点和问题的解决方案。但是,好处、优点、问题的解决方案和可以使得任何好处、优点或解决方案产生或变得更显著的任何元素不应为解释为任一或所有权利要求的关键、所需或必要特征或元素。这里所用的术语“包括”、“包含”(comprises、comprising)或其任何其它变型,意为覆盖非排他性的包含,由此,包括一系列元素的工艺、方法、制品或设备不仅包括那些元素,还包括没有列举表述或这些工艺、方法、制品或设备所固有的其它元素。
权利要求书(按照条约第19条的修改)1.一种用于形成半导体器件的方法,其包括:
提供半导体衬底;
在所述半导体衬底上形成金属氧化物层;
在所述金属氧化物的第一部分上形成构图的栅极;和
通过加热所述半导体衬底并在加热的同时在所述衬底上流过含卤素的化学制剂来去所述除金属氧化物层的第二部分,其中所述金属氧化物层的第二部分邻近所述金属氧化物层的第一部分;
其中,在没有rf激活的反应室中执行去除所述金属氧化物层的第二部分的操作。
2.如权利要求1所述的方法,其中所述含卤素化学制剂还包括氢。
3.如权利要求2所述的方法,其中所述含卤素化学制剂是HCl。
4.如权利要求1所述的方法,其中所述金属氧化物层是氧化铪。
5.如权利要求1所述的方法,其还包括:
在流过所述含卤素化学制剂之前在所述构图栅极上形成构图ARC层;和
在流过所述含卤素化学制剂之后去除所述构图ARC层。
6.如权利要求5所述的方法,其还包括:
在所述金属氧化物层之下形成第一界面氧化层;
在去除所述金属氧化物层的第二部分之后去除所述第一界面氧化层的至少一部分。
7.如权利要求6所述的方法,其中,使用含氢和氟的化学制剂执行去除所述第一界面氧化层的至少一部分。
8.如权利要求7所述的方法,其还包括:在所述半导体衬底上形成第二界面氧化物。
9.如权利要求1所述的方法,其中所述去除步骤的特征还在于,在大约625摄氏度到675摄氏度之间的温度。
10.如权利要求9所述的方法,其中所述去除步骤的特征还在于,在大约50托的压力执行大约60秒且含卤素化学制剂的流速为大约一SLM。
11.如权利要求1所述的方法,其中使用辐照源执行加热。
12.一种去除在半导体衬底上金属氧化物层的方法,其包括:
把半导体衬底放置到反应室中;
加热金属氧化物层;
在没有rf激活的情况下,加热的同时流过含氯的化学制剂,其中所述含氯的化学制剂与部分所述金属氧化物层反应产生副产品,其中所述副产品包括来自所述金属氧化物层的元素;和
从反应室去除所述副产品。
13.一种用于形成半导体器件的方法,其包括:
提供半导体衬底;
在所述半导体衬底上形成包含铪和氧的金属氧化物层;
通过使用辐照加热所述半导体衬底并流过含氢和氯的化学制剂来去除部分所述金属氧化物层;
其中,在没有RF激活的反应室中执行去除所述金属氧化物层的第二部分的操作。
14.如权利要求13所述的方法,其中,加热所述半导体衬底的温度是在大约625摄氏度到675摄氏度之间。
15.如权利要求13所述的方法,其中所述半导体衬底包括硅。
16.如权利要求15所述的方法,其还包括:
在所述金属氧化物层之下形成第一界面氧化物层;
在去除部分所述金属氧化物层之后去除所述第一界面氧化物的至少一部分。
17.如权利要求16所述的方法,其中,使用含氢和氟的化学制剂执行去除所述第一界面氧化层的至少一部分的操作。
18.如权利要求17所述的方法,其还包括在所述半导体衬底上形成第二界面氧化物。
19.一种形成金属氧化物的方法,其包括:
提供半导体衬底;
在所述半导体衬底上形成金属氧化物层;
通过加热所述半导体衬底并流过气态卤化物来去除部分所述金属氧化物层;
其中,在没有RF激活的反应室中执行去除部分所述金属氧化物层的操作。
20.如权利要求19所述的方法,其中所述气态卤化物包括氢。
21.如权利要求20所述的方法,其中所述气态卤化物是HCl。
22.如权利要求20所述的方法,其中所述气态卤化物是HF。
23.如权利要求19所述的方法,其中所述金属氧化物包括铪和氧。
24.如权利要求19的方法,其中,加热所述半导体衬底的温度是在大约625摄氏度到675摄氏度之间。
25.一种从半导体衬底选择性去除金属氧化物层的方法,其中所述金属氧化物层具有暴露部分和在栅极之下的部分,所述方法包括如下步骤:在没有rf激活的情况下,从衬底上流过气态HCl,所述衬底被加热到600到800摄氏度之间。
26.如权利要求25所述的方法,其中所述衬底被加热到625到675摄氏度之间。
27.如权利要求26所述的方法,其中所述金属氧化物是氧化铪。
28.如权利要求27所述的方法,其中,用辐照加热所述衬底。
29.如权利要求28所述的方法,其中所述金属氧化物覆盖在氧化层上面。

Claims (31)

1.一种用于形成半导体器件的方法,其包括:
提供半导体衬底;
在所述半导体衬底上形成金属氧化物层;
在所述金属氧化物的第一部分上形成构图的栅极;和
通过加热所述半导体衬底并在加热的同时在所述衬底上流过含卤素的化学制剂来去所述除金属氧化物层的第二部分,其中所述金属氧化物层的第二部分邻近所述金属氧化物层的第一部分。
2.如权利要求1所述的方法,其中所述含卤素化学制剂还包括氢。
3.如权利要求2所述的方法,其中所述含卤素化学制剂是HCl。
4.如权利要求1所述的方法,其中所述金属氧化物层是氧化铪。
5.如权利要求1所述的方法,其还包括:
在流过所述含卤素化学制剂之前在所述构图栅极上形成构图ARC层;和
在流过所述含卤素化学制剂之后去除所述构图ARC层。
6.如权利要求5所述的方法,其还包括:
在所述金属氧化物层之下形成第一界面氧化层;
在去除所述金属氧化物层的第二部分之后去除所述第一界面氧化层的至少一部分;
7.如权利要求6所述的方法,其中,使用含氢和氟的化学制剂执行去除所述第一界面氧化层的至少一部分。
8.如权利要求7所述的方法,其还包括:在所述半导体衬底上形成第二界面氧化物。
9.如权利要求1所述的方法,其中所述去除步骤的特征还在于,在大约625摄氏度到675摄氏度之间的温度。
10.如权利要求9所述的方法,其中所述去除步骤的特征还在于,在大约50托的压力执行大约60秒且含卤素化学制剂的流速为大约一SLM。
11.如权利要求1所述的方法,其中,在没有rf激活的反应室中执行去除所述金属氧化物层的第二部分的操作。
12.如权利要求1所述的方法,其中使用辐照源执行加热。
13.一种去除在半导体衬底上金属氧化物层的方法,其包括:
把半导体衬底放置到反应室中;
加热金属氧化物层;
加热的同时流过含氯的化学制剂,其中所述含氯的化学制剂与部分所述金属氧化物层反应产生副产品,其中所述副产品包括来自所述金属氧化物层的元素;和
从反应室去除所述副产品。
14.一种用于形成半导体器件的方法,其包括:
提供半导体衬底;
在所述半导体衬底上形成包含铪和氧的金属氧化物层;
通过使用辐照加热所述半导体衬底并流过含氢和氯的化学制剂来去除部分所述金属氧化物层。
15.如权利要求14所述的方法,其中,加热所述半导体衬底的温度是在大约625摄氏度到675摄氏度之间。
16.如权利要求14所述的方法,其中所述半导体衬底包括硅。
17.如权利要求16所述的方法,其还包括:
在所述金属氧化物层之下形成第一界面氧化物层;
在去除部分所述金属氧化物层之后去除所述第一界面氧化物的至少一部分。
18.如权利要求17所述的方法,其中,使用含氢和氟的化学制剂执行去除所述第一界面氧化层的至少一部分的操作。
19.如权利要求18所述的方法,其还包括在所述半导体衬底上形成第二界面氧化物。
20.如权利要求14所述的方法,其中,在没有RF激活的反应室中执行去除所述金属氧化物层的第二部分的操作。
21.一种形成金属氧化物的方法,其包括:
提供半导体衬底;
在所述半导体衬底上形成金属氧化物层;
通过加热所述半导体衬底并流过气态卤化物来去除部分所述金属氧化物层。
22.如权利要求21所述的方法,其中所述气态卤化物包括氢。
23.如权利要求22所述的方法,其中所述气态卤化物是HCl。
24.如权利要求22所述的方法,其中所述气态卤化物是HF。
25.如权利要求21所述的方法,其中所述金属氧化物包括铪和氧。
26.如权利要求21的方法,其中,加热所述半导体衬底的温度是在大约625摄氏度到675摄氏度之间。
27.一种从半导体衬底选择性去除金属氧化物层的方法,其中所述金属氧化物层具有暴露部分和在栅极之下的部分,所述方法包括如下步骤:在没有rf激活的情况下,从衬底上流过气态HCl,所述衬底被加热到600到800摄氏度之间。
28.如权利要求27所述的方法,其中所述衬底被加热到625到675摄氏度之间。
29.如权利要求28所述的方法,其中所述金属氧化物是氧化铪。
30.如权利要求29所述的方法,其中,用辐照加热所述衬底。
31.如权利要求30所述的方法,其中所述金属氧化物覆盖在氧化层上面。
CNB028145313A 2001-07-26 2002-06-11 金属氧化物的选择去除 Expired - Fee Related CN1305117C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/916,023 US6818493B2 (en) 2001-07-26 2001-07-26 Selective metal oxide removal performed in a reaction chamber in the absence of RF activation
US09/916,023 2001-07-26

Publications (2)

Publication Number Publication Date
CN1568537A true CN1568537A (zh) 2005-01-19
CN1305117C CN1305117C (zh) 2007-03-14

Family

ID=25436586

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028145313A Expired - Fee Related CN1305117C (zh) 2001-07-26 2002-06-11 金属氧化物的选择去除

Country Status (7)

Country Link
US (1) US6818493B2 (zh)
EP (1) EP1415333A1 (zh)
JP (1) JP4377686B2 (zh)
KR (1) KR100879233B1 (zh)
CN (1) CN1305117C (zh)
TW (1) TW548729B (zh)
WO (1) WO2003012850A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102176408B (zh) * 2006-06-22 2013-05-08 东京毅力科创株式会社 干式非等离子体处理系统和使用方法
CN103594524A (zh) * 2013-11-25 2014-02-19 杭州士兰集成电路有限公司 肖特基二极管及其制作方法
CN108362988A (zh) * 2018-02-09 2018-08-03 哈尔滨工业大学 一种抑制双极晶体管低剂量率增强效应的方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6451389B1 (en) * 1999-04-17 2002-09-17 Advanced Energy Industries, Inc. Method for deposition of diamond like carbon
US6933235B2 (en) * 2002-11-21 2005-08-23 The Regents Of The University Of North Texas Method for removing contaminants on a substrate
CN1320606C (zh) * 2003-03-04 2007-06-06 台湾积体电路制造股份有限公司 一种栅极介电层与改善其电性的方法
WO2005013374A1 (ja) * 2003-08-05 2005-02-10 Fujitsu Limited 半導体装置および半導体装置の製造方法
US6979622B1 (en) 2004-08-24 2005-12-27 Freescale Semiconductor, Inc. Semiconductor transistor having structural elements of differing materials and method of formation
US20060234436A1 (en) * 2005-04-15 2006-10-19 Tseng Hsing H Method of forming a semiconductor device having a high-k dielectric
US7662253B2 (en) * 2005-09-27 2010-02-16 Lam Research Corporation Apparatus for the removal of a metal oxide from a substrate and methods therefor
US20090253268A1 (en) * 2008-04-03 2009-10-08 Honeywell International, Inc. Post-contact opening etchants for post-contact etch cleans and methods for fabricating the same
US20100109045A1 (en) * 2008-10-30 2010-05-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing stress-engineered layers
US10714486B2 (en) 2018-09-13 2020-07-14 Sandisk Technologies Llc Static random access memory cell employing n-doped PFET gate electrodes and methods of manufacturing the same

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53129971A (en) 1977-04-19 1978-11-13 Matsushita Electric Ind Co Ltd Production of semiconductor device
US4708766A (en) 1986-11-07 1987-11-24 Texas Instruments Incorporated Hydrogen iodide etch of tin oxide
US4834834A (en) * 1987-11-20 1989-05-30 Massachusetts Institute Of Technology Laser photochemical etching using surface halogenation
US5292673A (en) * 1989-08-16 1994-03-08 Hitachi, Ltd Method of manufacturing a semiconductor device
EP0468758B1 (en) * 1990-07-24 1997-03-26 Semiconductor Energy Laboratory Co., Ltd. Method of forming insulating films, capacitances, and semiconductor devices
FR2694131B1 (fr) 1992-07-21 1996-09-27 Balzers Hochvakuum Procede et installation pour la fabrication d'un composant, notamment d'un composant optique, et composant optique ainsi obtenu.
US5300187A (en) 1992-09-03 1994-04-05 Motorola, Inc. Method of removing contaminants
SG43836A1 (en) * 1992-12-11 1997-11-14 Intel Corp A mos transistor having a composite gate electrode and method of fabrication
US5405491A (en) * 1994-03-04 1995-04-11 Motorola Inc. Plasma etching process
US5776356A (en) 1994-07-27 1998-07-07 Sharp Kabushiki Kaisha Method for etching ferroelectric film
KR0141160B1 (ko) * 1995-03-22 1998-06-01 김광호 강유전체 메모리 장치 및 그 제조방법
US5726102A (en) * 1996-06-10 1998-03-10 Vanguard International Semiconductor Corporation Method for controlling etch bias in plasma etch patterning of integrated circuit layers
US6115281A (en) * 1997-06-09 2000-09-05 Telcordia Technologies, Inc. Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors
JPH10340893A (ja) 1997-06-09 1998-12-22 Sony Corp 電子薄膜材料のエッチング方法
US6013553A (en) * 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6020024A (en) * 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
JP2000058515A (ja) * 1997-08-08 2000-02-25 Mitsui Chemicals Inc 金属酸化物/フォトレジスト膜積層体のドライエッチング方法
US6204130B1 (en) * 1997-08-29 2001-03-20 Advanced Micro Devices, Inc. Semiconductor device having reduced polysilicon gate electrode width and method of manufacture thereof
US6165375A (en) * 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
TW365034B (en) * 1997-10-18 1999-07-21 United Microelectronics Corp Manufacturing method for gates
US6004850A (en) 1998-02-23 1999-12-21 Motorola Inc. Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation
US6130103A (en) * 1998-04-17 2000-10-10 Symetrix Corporation Method for fabricating ferroelectric integrated circuits
US6165802A (en) * 1998-04-17 2000-12-26 Symetrix Corporation Method of fabricating ferroelectric integrated circuit using oxygen to inhibit and repair hydrogen degradation
US6222240B1 (en) * 1998-07-22 2001-04-24 Advanced Micro Devices, Inc. Salicide and gate dielectric formed from a single layer of refractory metal
US6171934B1 (en) * 1998-08-31 2001-01-09 Symetrix Corporation Recovery of electronic properties in process-damaged ferroelectrics by voltage-cycling
US6162738A (en) 1998-09-01 2000-12-19 Micron Technology, Inc. Cleaning compositions for high dielectric structures and methods of using same
US6204203B1 (en) * 1998-10-14 2001-03-20 Applied Materials, Inc. Post deposition treatment of dielectric films for interface control
DE19856082C1 (de) 1998-12-04 2000-07-27 Siemens Ag Verfahren zum Strukturieren einer metallhaltigen Schicht
US6037268A (en) 1998-12-29 2000-03-14 Lucent Technologies Inc. Method for etching tantalum oxide
US6242350B1 (en) * 1999-03-18 2001-06-05 Taiwan Semiconductor Manufacturing Company Post gate etch cleaning process for self-aligned gate mosfets
JP2000353804A (ja) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100298637B1 (ko) * 1999-06-29 2001-09-22 김충섭 폴리카보네이트 수지의 제조방법
JP3450758B2 (ja) * 1999-09-29 2003-09-29 株式会社東芝 電界効果トランジスタの製造方法
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6383873B1 (en) * 2000-05-18 2002-05-07 Motorola, Inc. Process for forming a structure
US6300202B1 (en) * 2000-05-18 2001-10-09 Motorola Inc. Selective removal of a metal oxide dielectric
US6403432B1 (en) * 2000-08-15 2002-06-11 Taiwan Semiconductor Manufacturing Company Hardmask for a salicide gate process with trench isolation
JP2002075972A (ja) 2000-09-04 2002-03-15 Hitachi Ltd 半導体装置の製造方法
US6486080B2 (en) * 2000-11-30 2002-11-26 Chartered Semiconductor Manufacturing Ltd. Method to form zirconium oxide and hafnium oxide for high dielectric constant materials
US6495436B2 (en) * 2001-02-09 2002-12-17 Micron Technology, Inc. Formation of metal oxide gate dielectric
US6348386B1 (en) * 2001-04-16 2002-02-19 Motorola, Inc. Method for making a hafnium-based insulating film
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US6465853B1 (en) * 2001-05-08 2002-10-15 Motorola, Inc. Method for making semiconductor device
US6413829B1 (en) * 2001-06-01 2002-07-02 Advanced Micro Devices, Inc. Field effect transistor in SOI technology with schottky-contact extensions

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102176408B (zh) * 2006-06-22 2013-05-08 东京毅力科创株式会社 干式非等离子体处理系统和使用方法
CN103594524A (zh) * 2013-11-25 2014-02-19 杭州士兰集成电路有限公司 肖特基二极管及其制作方法
CN108362988A (zh) * 2018-02-09 2018-08-03 哈尔滨工业大学 一种抑制双极晶体管低剂量率增强效应的方法
CN108362988B (zh) * 2018-02-09 2020-12-29 哈尔滨工业大学 一种抑制双极晶体管低剂量率增强效应的方法

Also Published As

Publication number Publication date
TW548729B (en) 2003-08-21
KR20040018515A (ko) 2004-03-03
WO2003012850B1 (en) 2003-11-20
CN1305117C (zh) 2007-03-14
KR100879233B1 (ko) 2009-01-20
US20030022432A1 (en) 2003-01-30
JP2004537857A (ja) 2004-12-16
JP4377686B2 (ja) 2009-12-02
EP1415333A1 (en) 2004-05-06
US6818493B2 (en) 2004-11-16
WO2003012850A1 (en) 2003-02-13

Similar Documents

Publication Publication Date Title
CN1305117C (zh) 金属氧化物的选择去除
US4994404A (en) Method for forming a lightly-doped drain (LDD) structure in a semiconductor device
KR940005721B1 (ko) Sos 및 soi 장치의 메사 구조를 위한 연부 도핑 프로세스
US5258095A (en) Method for producing a device having an insulator sandwiched between two semiconductor layers
US20050118768A1 (en) Method of forming high voltage metal oxide semiconductor transistor
JP3339038B2 (ja) 自己整合スペーサを有する半導体構造の製造方法
TWI241660B (en) Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing
CN1223464A (zh) 提供双功函数掺杂
US5395774A (en) Methods for forming a transistor having an emitter with enhanced efficiency
JPH0232539A (ja) 半導体装置の製造方法及びエッチング方法
KR100243916B1 (ko) 박막트랜지스터의 제조방법
JPH08167597A (ja) エッチング方法およびエッチング装置
CN1322565C (zh) 包括有薄氧化物内衬的半导体装置及其制法
KR100489588B1 (ko) 탑게이트형박막트랜지스터의제조방법
Lo et al. Thickness Dependence of Charge‐Trapping Properties in Ultrathin Thermal Oxides Prepared by Rapid Thermal Oxidation
KR970005952B1 (ko) 박막트랜지스터의 제조방법
CN108666222B (zh) 半导体结构及其制作方法
EP0379208A2 (en) A method for producing a device having an insulator sandwiched between two semiconductor layers
KR100278913B1 (ko) 반도체소자 제조방법
KR960015955A (ko) 반도체소자의 제조방법
KR100241522B1 (ko) 반도체 소자의 박막 트랜지스터 제조방법
KR100406564B1 (ko) 모스 전계효과 트랜지스터의 제조방법
KR20040059753A (ko) 텅스텐막을 포함하는 게이트전극을 구비한 반도체 소자의제조 방법
KR0161726B1 (ko) 반도체 소자 제조방법
KR100252904B1 (ko) 반도체 소자의 산화막 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Owner name: FREESCALE SEMICONDUCTOR INC.

Free format text: FORMER OWNER: MOTOROLA, INC.

Effective date: 20041224

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20041224

Address after: texas

Applicant after: Fisical Semiconductor Inc.

Address before: Illinois

Applicant before: Motorola Inc.

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: texas

Patentee after: NXP America Co Ltd

Address before: texas

Patentee before: Fisical Semiconductor Inc.

Address after: texas

Patentee after: NXP America Co Ltd

Address before: texas

Patentee before: Fisical Semiconductor Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070314

Termination date: 20190611