CN1547769A - 形成用于衬底的凸起触点的方法 - Google Patents

形成用于衬底的凸起触点的方法 Download PDF

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Publication number
CN1547769A
CN1547769A CNA038004747A CN03800474A CN1547769A CN 1547769 A CN1547769 A CN 1547769A CN A038004747 A CNA038004747 A CN A038004747A CN 03800474 A CN03800474 A CN 03800474A CN 1547769 A CN1547769 A CN 1547769A
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insulator
substrate
conductor
plug
cmp
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CN100361289C (zh
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保罗・费希尔
保罗·费希尔
・博德曼
詹姆斯·博德曼
米利埃
安妮·米利埃
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Intel Corp
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Intel Corp
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Abstract

本发明包括一种方法，该方法包括如下步骤：提供一个第一衬底；形成一个覆盖第一衬底的绝缘体；在绝缘体中形成一个开口；在开口中以及绝缘体上形成一个导体；用第一化学机械抛光工艺除掉绝缘体上的导体，以便留下在开口中的导体；以及用第二化学机械抛光工艺减小绝缘体的厚度，以使在开口中的导体凸出。本发明还包括具有这种凸出导体的结构。

Description

形成用于衬底的凸起触点的方法
技术领域
本发明涉及半导体集成电路制造领域，更具体地说，涉及形成用于衬底的凸起触点的方法。
背景技术
1965年，Gordon Moore首先发现在芯片的单位面积上的晶体管的数量大约每18个月增加一倍。自那时起，半导体工业就设法按计划引进新的设计和工艺，从而在器件密度方面提供由所谓Moore定律所反映的提高。具体地说，在光学和光刻技术方面的重大进步已经减小了能够成功地在芯片或其它衬底上进行图案化的构造(feature)的临界尺寸(CriticalDimension，CD)。同时，在掺杂、沉积以及蚀刻方面的显著改进已经减小了可以精确达到的跨越衬底的厚度、深度以及浓度。
由于器件尺寸接近原子尺寸，在确定衬底上的器件的性能和可靠性方面，基本的物理限制将越来越起到更大的作用。过去，定标(scaling)问题一般已经包括在半导体处理工艺前端的晶体管或者在半导体处理工艺的后端的布线。但是，越来越重要的是使衬底上的晶体管和互连的定标与多个衬底之间的相互连接的定标平衡。
因此，需要一种形成用于衬底之间的相互连接的凸起触点(raisedcontact)的方法以及一种具有这种凸起触点的结构。
附图说明
图1(a)-(g)示出了本发明的形成用于衬底的凸起触点的方法的不同实施例的横截面视图。
图1(g)还示出了本发明的包括一个在衬底上的插栓的结构的横截面视图。
图2示出了本发明的使衬底之间的凸起触点相互连接的方法的实施例的横截面视图。
图2还示出了本发明的包括两个用凸起触点相互连接的衬底的结构的横截面视图。
具体实施方式
在以下的描述中，为了提供对本发明的透彻理解，描述了许多具体细节如具体材料、尺寸和工艺等。但是，本领域技术人员应该理解，可以在没有这些具体细节的情况下实施本发明。在其它情况下，不对众所周知的半导体设备和工艺的具体细节进行描述，以避免使本发明难以理解。
通过重复地进行例如掺杂、沉积、图案化以及蚀刻等单元过程的某种组合，可以在衬底上形成器件。在在芯片或衬底上制作集成电路(integrated circuit，IC)期间，可以在半导体材料中形成晶体管，并且由电绝缘材料将这些晶体管分开。然后，可以用互连系统将这些晶体管连接起来，该互连系统具有被电绝缘材料分开的多个导电材料层。
通过叠放两个或多个衬底，可以得到更高的每单位体积的器件密度。可以用3维互连对衬底进行导线连接。3维互连可以包括衬底上的凸起触点。本发明描述一种形成用于衬底之间的互连的凸起触点的方法。
在图1(g)和图2中示出了按照本发明的结构的某些实施例。
在图1(g)中示出了包括衬底100上的插栓(plug)135的结构1000的实施例。插栓135可以形成一个凸起触点，以便使信号能够输入到与衬底100的下衬层102中的器件的有源区域相连接的焊盘(bond pad)104，或者从焊盘104输出。
图2中示出了按照本发明的，包括两个相互连接的衬底210、220的结构2000的实施例。结构2000包括用于第一衬底210的第一凸起触点211，触点211与用于第二衬底220的第二凸起触点221相互连接。在一个实施例中，凸起触点211使信号能够输入到与衬底210的下层202中的器件的有源区域相连接的焊盘204，或者从焊盘204输出。
在图1(a)-(g)以及图2中示出了按照本发明的，形成用于衬底100的凸起触点的方法的不同实施例。衬底100可以包括具有多个芯片的晶片、或者具有多个模片(die)的芯片、或者具有多个器件的模片。
可以使衬底100与外壳结合为一个整体。在某些情况下可以使用内插器(interposer)。衬底100一般包括下衬层102。下衬层102包括使信号能够输入到器件的有源区域或者从器件的有源区域输出的焊盘104。器件可以是有源的或无源的。焊盘104由导电材料构成，其厚度从2500.0-12000.0埃的范围中选择。导电材料可以包括金属，如铝或铜。
下衬层102可以被由电绝缘材料构成的绝缘体103覆盖，其厚度从2500.0-24000.0埃的范围中选择。可以通过对平行板电结构进行电容测量，确定电绝缘材料的介电常数(k)。电绝缘材料包括k值约为3.9-4.2的二氧化硅。在一个实施例中，可以将非掺杂石英玻璃(Undoped SilicaGlass，USG)用于设计规则大约为250纳米(nm)的器件。可以用于形成绝缘体103的工具包括来自Applied Materials的Ultima XTM系统。
绝缘体103可以起中间级、中间层或电介质的作用，将焊盘104与可能出现在下衬层102的相同或不同级或层中的其它导电材料分开。邻近导线之间的过大的电容可能使在下衬层102中的与这些线相连接的器件的性能下降。当器件包括晶体管时，线间电容可能在晶体管运行期间产生干扰(cross-talk)并且增加电阻-电容(RC)乘积延时，由此降低它们的开关速度。
可以通过使用低k材料作为在导电材料之间的绝缘体103来减小在衬底100的线路中的线间电容。低k指的是低于二氧化硅的k值的k值。对于按照大约180nm的设计规则的器件，可以用氟对二氧化硅进行掺杂，形成k值大约为3.3-3.7的氟化硅酸盐玻璃(Fluorinated Silicate glass，FSG或SiOF)。FSG与二氧化硅具有许多相似的特性，因而工艺整合相对简单直接。
对于按照更小的设计规则的器件来说，FSG的k值不够低，因此必须使用其它低k材料。低k电介质可以包括有机材料、硅酸盐材料或者有机材料与硅酸盐材料的混合物，如有机硅酸盐玻璃(organosilicate glass，OSG)。对于按照大约130nm的设计规则的器件，可以用甲基(-CH3)对二氧化硅进行掺杂，形成k值大约为2.4-3.3的碳掺杂二氧化硅(Carbon-doped Silicon Oxide，CDO或SiOC)。
对于按照大约90nm的设计规则的器件，可以由具有超低k值的低k材料构成绝缘体103。超低k指的是大约小于2.2的k值。对于按照大约70nm到大约50nm的设计规则的器件，可以由k值大约低于1.5的材料构成绝缘体103。具有超低k的材料通常是多孔的并且可以包括气凝胶和干凝胶。在某些情况下，低k或超低k材料可能需要使用阻挡层，以防止扩散、混合或者与其它材料反应。在一个实施例中，可以形成在低k或超低k材料之上的压盖(capping)层，如氮化硅(SiN)或氮氧化硅(SiON)。
可以利用化学气相沉积(CVD)工艺形成绝缘体103。可以利用等离子增强化学气相沉积(PECVD)工艺形成的低k材料包括来自AppliedMaterials的Black DiamondTM(k值大约为2.4-3.1的CDO)、来自Novellus Systems的CORALTM(k值大约为2.4-2.8的CDO)以及来自Trikon Technologies的Flowfill(k值大约为2.5-2.8的CDO)。可以利用PECVD形成的超低k材料包括来自Trikon Technologies的OrionTM(k值大约为2.0-2.2的CDO)。可以用于形成低k或超低k材料的工具包括来自Applied Materials的Producer系统。也可以使用来自Novellus Systems的SEQUEL ExpressTM系统或VECTORTM系统。
或者，可以通过旋压电介质(spin-on dielectric，SOD)形成绝缘体103。在某些情况下，SOD可能需要使用附着层。可以使用旋压工艺形成的来自液体源的低k材料包括来自Dow Chemical的SiLKTM(k值大约为2.65的芳烃聚合物)和来自Honeywell Electronic Materials(HEM)的HOSPTM(k值大约为2.5的混杂有机硅氧烷聚合物或OSG)。可以旋压的超低k材料包括来自HEM的NANOGLASS(k值大约为1.3-2.2的多孔氧化硅)。可以用于形成低k材料或超低k材料的工具包括来自TokyoElectron Ltd.(TEL)的spin track。
通过光刻工艺确定被称为光刻胶101的辐射敏感材料的掩模。首先，将光刻胶101涂在衬底100的绝缘体103上。如图1(a)中的实施例所示，当由标度线(reticle)进行调节时，通过暴露到适当波长和剂量的辐射，在光刻胶101中使构造99图案化，然后通过显影形成掩模。曝光可以在成像工具中进行，如步进器(stepper)或扫描器(scanner)。
然后，通过蚀刻工艺可以将光刻胶101掩模中的构造99转变为在绝缘体103中的开口105。形成开口105的蚀刻工艺可以包括等离子体蚀刻工艺或反应离子蚀刻(RIE)工艺。如图1(b)中的实施例所示，开口105暴露出在下衬层102中的器件的焊盘104的一部分。
开口105可以包括由标度线得到的形状，如通道(via)、沟槽(trench)或者覆盖在通道上的沟槽。开口105可以具有大于1微米(um)的垂直尺寸或深度以及小于0.1um的横向尺寸如宽度。对于蚀刻来说，当开口105具有约6∶1或更大的深宽比(深度∶宽度)时，高方向性是理想的。在一个实施例中，可以使用高密度等离子体，如感应耦合射频(RF)等离子体(ICP)。
可以用气体混合物进行形成开口105的蚀刻。气体混合物可以包括蚀刻气体如CF4，以及聚合气体如CH2F2。蚀刻气体是用于对绝缘体103进行蚀刻的氟的主要来源，而聚合气体使开口105的侧壁钝化，以便提高选择率。可以使用的其它气体包括CHF3和C3F6。绝缘体103的蚀刻速度可以是约每分钟1500.0-12000.0埃。
可以用于形成开口105的工具包括来自Trikon Technologies的OmegaMORITM系统。如果需要，则可以在集成工具中，如来自LamResearch的Exelan系统或者来自Applied Materials的eMaxTM EnTekTMCentura系统，将绝缘体103的蚀刻、对任何下衬阻挡层或蚀刻终止层的清除以及对光刻胶101的剥离顺序执行。
绝缘体103对于光刻胶101掩模的蚀刻选择率大约是2∶1到7∶1。如果绝缘体103对于光刻胶101掩模的蚀刻选择率太低，则可以在绝缘体103与光刻胶101之间包括一个被称为硬掩模的中间掩模。在这种情况下，用第一蚀刻工艺将在光刻胶101中被图案化的第一构造99转变为在硬掩模中的第二构造。然后，第二蚀刻工艺将第二构造从硬掩模转变为在绝缘体103中的开口105。绝缘体103对于硬掩模的蚀刻选择率可能高于20∶1。硬掩模工艺可以包括诸如SiN或SiON等材料。在一个实施例中，可以使用包括两个或多个硬掩模的堆叠(stack)。
如果绝缘体103对于下衬焊盘104的蚀刻选择率太低，则在焊盘104与绝缘体103之间可以包括隐藏蚀刻终止(buried etch stop，BES)层。这个蚀刻终止层可以包括SiN或碳化硅(SiC)。但是，SiN的k值为6.5，这个值相对较高，因此可以使用替代材料，如来自Applied Materials的k值约为4.5-5.0的BLOkTM。如果需要，则可以使用k值更低的蚀刻终止层，以使整体电介质堆叠结构的电容最小。一个例子是来自HEM的k值约为2.6的HOSP BEStTM。
当将某些材料用于晶种层(seed layer)120或导体130时，可能需要阻挡层115来保护绝缘体103以及下衬层102，包括焊盘104。例如，铜的高扩散性以及在铜中存在的中间间隙(mid-gap)状态造成需要阻挡层115。另外，铜可以扩散到绝缘体103或下衬层102中，并且缩短半导体材料如硅的载流子的寿命。
在开口105中以及在绝缘体103上形成阻挡层115。阻挡层115的厚度可以从50.0-600.0埃的范围中选择。阻挡层115应该对开口115的里面和外面提供良好的覆盖。在某些情况下，在开口里面的阻挡层115的厚度可以与在开口外面的阻挡层115的厚度不同。
阻挡层115应该有效地阻挡从晶种层120或导体130到绝缘体103或下衬层102的扩散。为了起到垫层或内衬的作用，阻挡层115应该能够很好地附着到晶种层120、导体130、绝缘体103以及下衬层102(包括焊盘104)上。但是，阻挡层115与晶种层120、导体130、绝缘体103以及下衬层102(包括焊盘104)之间，也应该具有最小的相互作用，如化学或电化学反应。
阻挡层115可以由金属构成，包括难熔金属如钽(Ta)，或者由合金构成，如钛钨合金(TiW)，或者由陶瓷构成，如氮化钽(TaN)、氮化钽硅(TaSiN)、氮化钛(TiN)或者氮化钨(WN)。
在一个实施例中，阻挡层115可以包括附着到下衬绝缘体103的TaN下层和附着到上覆晶种层120的Ta上层。这种双层结构的总厚度大约为150.0-350.0埃。
对于阻挡层115的沉积来说，高方向性是理想的，尤其当开口105的深宽比(深度∶宽度)约为6∶1或更大时。离子化物理气相沉积(I-PVD)技术能够用比其它技术，例如准直溅射(collimation sputtering)或长抛溅射(long-throw sputtering，LTS)，更好的分步覆盖来对材料进行沉积。可以用于I-PVD的工具包括来自Novellus Systems的INOVATM系统、来自Trikon Technologies的Sigma系统以及来自Ulvac Technologies的Entron系统。
在某些情况下，可以利用金属有机化学气相沉积(MOCVD)工艺形成阻挡层115。在MOCVD中使用的前体在开口105的暴露的表面上起反应，而不是在如CVD的气相中起反应，因此，覆盖通常是良好的。可以用于MOCVD的工具包括来自Veeco Instruments的NEXUSTM系统。
或者，当需要100.0埃或更小的厚度时，可以利用原子层沉积(ALD)形成阻挡层115。即使在允许使用大约200.0-400.0摄氏度的低沉积温度时，ALD也能够提供良好的分步覆盖和良好的均匀性。可以用于ALD的工具包括来自Veeco Instruments的NEXUSTM系统或者来自Genus的LYNX2或者LYNX3TM系统。
当要通过电镀形成导体130时，如图1(c)中的实施例所示，首先形成在阻挡层115上的晶种层120。为了起到用于电镀的基(base)的作用，晶种层120必须是导电的并且连续覆盖在阻挡层115上。应该防止晶种层120的附着损失或者与阻挡层115的界面反应。
晶种层120可以包括金属如铜，或者合金。晶种层120的典型厚度从大约20.0-2500.0埃的范围中选择。
晶种层120可以通过I-PVD进行沉积，尤其是当随后要通过电镀形成导体130时。如果需要，可以在真空下，在一个工具中，如来自AppliedMaterials的EnduraElectraTM系统中，顺序沉积阻挡层115和晶种层120。
当随后要通过PVD形成导体130时，对于导体130来说，如果利用CVD形成晶种层120，则可以实现更好的材料性能和表面特性。也可以用ALD或无电电镀形成晶种层120。
如图1(d)中的实施例所示，在晶种层120上形成导体130。导体130包括导电材料。晶种层120和导体130可以由相同的材料或不同的材料构成。导体130应该自下而上填充开口105。当完成填充时，开口105应该没有缺陷如空隙、裂缝或者裂纹。应该防止导体130的附着损失或者与晶种层120的界面反应。
导体130可以包括金属，例如铜，或合金。导体130的典型厚度约为0.2-2.8um。与铝相比，铜的优点包括更高的固有电导率，对电迁移的更低的磁化率以及对高宽比(高度∶宽度)约为3∶1或更大的开口105的填充更好等。与铝相比，铜的缺点包括难以利用RIE工艺进行蚀刻，易被腐蚀以及在硅中的高扩散率等。
导体130可以通过电化学工艺形成，如电镀。对导体130的电镀可以在电镀液或者在包含要进行沉积的材料的离子的溶液中进行。晶种层120起电化学电池的负极的作用。根据需要的厚度和薄膜特性，可以在溶液中利用恒定电流、恒定电压或者可变波形的电流或电压进行电镀。当接通电流时，电镀溶液中的正离子与在晶种层120的表面产生的电子相结合。由此在晶种层120上将离子化学还原为导体130的原子。可以用于电镀的工具包括来自Applied Materials的Electra GuTM系统，来自Novellus Systems的SABRETM Electrofill系统以及来自SEMITOOL的ParagonTM系统。
成功地对导体130进行电镀需要使用各种具有表面活性的添加剂。对电镀溶液的添加剂通常是有机的并且可以包括硫或氮官能团。对高宽比较大的开口105进行恰当的填充需要使电镀溶液中的阻止剂(抑制剂)与加速剂的适当平衡。否则，缺陷如空隙、裂缝或者裂纹等可能在导体130内部形成并且在后面的平坦化期间暴露出来。从衬底到衬底的良好的厚度一致性以及导体130的平滑的表面光洁度也可能需要在电镀溶液中使用平整剂和抛光剂。
根据对诸如pH值、电导率以及在电磁波谱的可见部分的吸收率等参数的监测，可以对电镀溶液中的各种离子如铜、氯化物和氢的浓度进行调节。循环伏安分离法(Cyclic Voltammetric Stripping，CVS)分析可以用于测量电镀溶液中的添加剂的浓度。
在另一个实施例中，有时候可以在不首先形成晶种层120的情况下，利用PVD工艺或者CVD工艺形成导体130。当对高宽比(高度∶宽度)约为6∶1或更大的开口105进行填充时，PVD工艺或者CVD工艺可能特别有利。在某些情况下，也可以使用MOCVD工艺。
在形成导体130期间或之后，可以使用一种处理方法来改变导体130的材料性能或表面特性。对导体130的处理包括在沉积之后的快速热退火(rapid thermal anneal，RTA)工艺，以便改变或者稳定导体130的晶粒大小(grain size)。根据厚度、沉积条件以及退火条件，通过电镀形成的铜可以具有大约0.1-1.0毫米(mm)的晶粒大小。通常，导体130中的晶粒越大，对应的电阻率越低。例如，铜可以具有1.0-4.0微欧厘米的电阻率。
通过对导体130进行平坦化形成插栓135，接着使围绕插栓135的绝缘体103下陷，可以形成用于衬底100的凸起触点。可以优化将磨损(机械力)与溶解(化学或电化学反应)相结合的化学机械抛光(CMP)工艺，以便使不同的材料平坦化或者下陷。
可以将衬底100固定在装配在CMP系统的头部的托架中。可以将一个垫板装配在CMP系统的工作台或台板(platen)上。当头部和台板移动时，垫板可以将一个机械力施加在衬底100上的导体130上。头部的运动和台板的运动可以是旋转的、环形的或直线的。或者，可以使垫板相对于台板运动，如与抛光带一起。可以在垫板上提供浆液(slurry)，以产生与衬底100上的导体130的化学反应。浆液中的研磨剂还可以与垫板一起将机械力施加到衬底100上的导体130上。
通过改变对不同材料的抛光速度，可以对CMP工艺的选择率进行调节。通过改变抛光垫板的性质(如硬度、刚性、磨损性、孔隙率以及凹槽或沟道的布置)、抛光浆液的性质(如化学成分、化学浓度、pH值、研磨剂类型、研磨剂数量以及研磨剂颗粒尺寸分布)以及抛光系统的参数(如托架相对于台板的向下的压力或压强、托架相对于台板的线速度、浆液流速以及台板温度)等，可以优化抛光的选择率。
跨越(across)衬底100，可以用适当的传感器对用于CMP工艺的临界工艺参数，如抛光清除速度以及抛光选择率，进行监控。然后通过用适当的调节器对相关的设备参数进行调节来控制工艺参数。CMP系统可以包括一个控制单元以及一个操作员界面，控制单元包括计算机。当需要时，可以对CMP工艺以及设备实施闭环控制。闭环控制可以包含使用比例、微分或积分等控制方法中的一个或多个的前馈或反馈控制。
对CMP工艺进行在线、设备上、就地以及实时地计量的程度取决于可以接受的所有权成本(cost-of ownership，CoO)的水平。当需要时，可以将计量工具与CMP工具集成在一起。例如，可以使用工具对凹陷和腐蚀的光学结果进行测量，包括来自Nova Measuring Instruments的NovaScan系统或者来自NanoMetrics的NanoSpec系统。
用于CMP的独立工具包括来自Applied Materials的Mirra系统。或者，可以使用集成工具，如来自Applied Materials的Mirra MesaTM或ReflexionTM系统或者来自Lam Research的TeresTM系统。集成工具可以将CMP与相关的工艺步骤结合，如使衬底100干进/干出(dry in/dry out)的预净化和后净化。可以从各种来源，如Rodel和Cabot，得到用于CMP的消耗品，包括垫板和浆液。
按照本发明的一个实施例，可以将第一CMP工艺与第二CMP工艺的组合用于形成用于衬底100的凸起触点。第一CMP工艺进行平坦化，而第二CMP工艺进行下陷操作。
相对于下衬阻挡层115，第一CMP工艺对于导体130具有很高的抛光选择率。由此，如图1(e)中的实施例所示，第一CMP工艺可以去掉跨越衬底100的导体130并且暴露出阻挡层115的上表面108。由于导体130通常较软，因此，阻挡层115可以起到抛光终止层的作用。通过减少跨越衬底100存在的任何大的或不一致的外形，抛光终止层使平坦化得到改善。
可以选择合适的浆液以实现导体130相对于阻挡层115的高抛光选择率。导体130对阻挡层115的抛光选择率的平均值约为50∶1-250∶1。更高的抛光选择率允许使用更薄的阻挡层115。更薄的阻挡层115将使焊盘104与导体130之间的电阻少量增加。
在一个实施例中，浆液可以包括研磨剂，如氧化铝或二氧化硅；氧化剂，如过氧化氢(H2O2)；钝化剂或成膜剂(腐蚀抑制剂)，如苯并三唑(BTA)；以及络合剂，络合剂可以是氨基酸如甘氨酸，或有机酸/盐系统如柠檬酸/柠檬酸钾。
用于对导体130进行平坦化的第一CMP工艺的典型参数包括约为5.0-9.0的浆液pH值、约为每分钟100.0-350.0毫升的浆液流速、约为每分钟15.0-100.0转(rpm)的台板转速、15.0-100.0rpm的托架转速以及约为每平方英寸1.0-7.0磅(psi)的抛光压强。对导体130的清除速度可以大约是每分钟1000.0-14000.0埃。
第一CMP工艺可以包括两个或多个步骤。在一个实施例中，可以利用具有较高清除速度的第一步骤去掉大部分导体130的上部沉积。第一步骤可以是定时抛光或者可以通过就地监控诸如厚度或涡电流的参数对其进行控制。然后，可以利用具有较低清除速度(如大约每分钟1000.0-2500.0埃)的第二步骤清除导体130，在不穿透绝缘体103的情况下，暴露阻挡层115的上表面108。第二步骤可以是定时抛光或终点抛光。在一个实施例中，在检测到阻挡层115的终点之后，第二步骤可以包括过抛光(overpolish)时间或过抛光百分比如15.0％。如果需要，可以在单独的台板上或者在单独的CMP系统上进行每个步骤。
如图1(e)中的实施例所示，去掉了大部分跨越衬底100的导体130并且暴露出阻挡层的上表面108将留下插入或嵌入开口105的插栓135。该插栓包括导体130、晶种层120以及阻挡层115。插栓135的形状受开口105的形状影响。例如，如果开口105是通道，则插栓135可能是一个杆(post)或一个栓(stud)。如果开口105是一个沟槽，则插栓135可能是一条线。
可能由第一CMP工艺引起的不希望的外形变化是插栓135的凹陷。凹陷使(在开口105里面的)插栓135中的导体130的上表面107相对于(在开口105外面的)周围的绝缘体103下降。
对于横向尺寸较大的插栓135，凹陷可能更严重。如图1(e)中的实施例所示，对第一CMP工艺进行适当的优化将产生插栓的第一抛光上表面107，它与已经暴露的阻挡层115的上表面108近似相平或水平对齐。
可能由第一CMP工艺引起的另一个不希望的外形变化是在插栓群或阵列137中的插栓之间的间隔中的材料相对于在远离插栓群或阵列137的场效应区中的材料的腐蚀。腐蚀引起(在群或阵列137中的)插栓之间的间隔相对于(在群或阵列137外的)场效应区中的材料下陷。腐蚀可能导致将插栓之间的间隔中的阻挡层115部分或全部被除掉。在阻挡层115已经被除掉的区域中，腐蚀还可能进一步导致将插栓之间的间隔中的部分下衬绝缘体103被除掉。
对于插栓之间的间隔很小的密集插栓的群或阵列137，腐蚀可能更严重。对第一CMP工艺进行适当的优化将使插栓群或阵列137内的插栓之间的间隔中的材料的清除速度与插栓群或阵列137外的材料的清除速度之间的差异最小。
如图1(g)中的实施例所示，在完成第一CMP工艺之后，利用第二CMP工艺除掉开口105外面的阻挡层115，并且使绝缘体103的暴露部分下陷得低于插栓135的上表面109。在一个实施例中，还可以将阻挡层115从插栓135的部分侧壁处除掉。
图1(g)中还示出了按照本发明的结构1000的实施例。结构1000包括用于衬底100的插栓135。在一个实施例中，插栓135可以形成凸起触点，它使信号能够输入到与衬底100的下衬层102中的器件的有源区域相连接的焊盘104，或从焊盘104输出。
可以选择合适的浆液以便实现阻挡层115和绝缘体103相对于导体130的较高的抛光选择率。绝缘体103对导体130的抛光选择率的平均值约为5∶1或更大。在一个实施例中，浆液可以包括研磨剂如二氧化硅和络合剂。络合剂可以是氢氧化铵(NH4OH)或有机酸/盐系统，如柠檬酸/柠檬酸钾。当需要时，还可以包括杀菌剂。使用相对较软的垫板可以使除掉的导体130最少并且防止产生缺陷。
用于使绝缘体103下陷的第二CMP工艺的典型参数包括约为6.0-12.0的浆液pH值、约为每分钟100.0-350.0毫升的浆液流速、约为5.0-85.0rpm的台板转速、约为5.0-85.0rpm的托架转速以及约为1.0-7.0psi的抛光压强。台板的线速度约为每分钟20.0-350.0英尺。在一个实施例中，浆液pH值约为9.0-11.0，抛光压强约为4.0-6.0psi，台板的线速度约为每分钟20.0-140.0英尺。当由低k材料形成绝缘体103时，可以对第二CMP工艺进行调节，以避免使形成绝缘体103的低k材料破裂或脱层。
在某些情况下，在第二CMP工艺之后可以进行后净化，如在非氧化环境中用有机酸或者有机酸缓冲液进行清洗。其pH值可以从2.0-6.0的范围中选择。
在本发明的另一个实施例中，当利用CMP使导体130平坦化以形成插栓135时，如图1(f)所示的绝缘体103取代了如图1(e)所示的阻挡层115，可以起抛光终止层的作用。然后，可以使绝缘体103直接下陷，以形成用于衬底100的凸起触点。必须优化浆液的化学组成和抛光条件以及参数，以达到理想的抛光选择率和抛光清除速度。
在远离插栓群或阵列137的场效应区中，绝缘体103的下陷速度约为每分钟300.0-2500.0埃。在高度上，绝缘体103的内部上表面110可以与绝缘体103的外部上表面112不同。内部指的是插栓群或阵列137里面的位置。外部指的是插栓群或阵列137外面的位置。在多数情况下，绝缘体103的内部上表面110高于绝缘体103的外部上表面112。
利用第二CMP工艺使绝缘体103下陷可以减小导体130的厚度。在插栓的第一抛光上表面107与插栓135的第二抛光上表面109之间的高度上的差异对应于导体130变薄。除了直到使插栓群或阵列137中的插栓的上表面107平坦化所需要的程度以外，应该避免导体130变薄。
将使绝缘体103下陷与使导体130变薄最小化相结合，使得最后的插栓135凸出在绝缘体103之上。插栓凸出量(relief)122是插栓135的第二抛光上表面109相对于绝缘体103的内部上表面110凸出的量。内部指的是插栓群或阵列137里面的位置。台阶高度124是插栓135的第二抛光上表面109相对于绝缘体103的外部上表面112凸出的量。外部指的是插栓群或阵列137外面的位置。场效应区包括远离插栓群或阵列137的外部位置。氧化凸出量是台阶高度124与插栓凸出量122之间的差异。
插栓凸出量122和台阶高度124可能受到各种因素的影响，包括局部图案密度(在每个插栓群或阵列137中的插栓之间的间隔)和总体图案密度(跨越衬底100的不同的插栓群或阵列137之间的间隔)。通常，较窄的插栓135和插栓135之间的较窄的间隔使导体130的变薄减小并且产生较小的插栓凸出量122。
插栓凸出量122和台阶高度124可以通过原子力显微镜(atomic forcemicroscope，AFM)或者高分辨率表面光度仪(high-resolutionprofilometer，HRP)测量并可视化。可以使用工具，如来自Veeco Instruments的DimensionTM。
插栓凸出量122的标称值可以从300.0-3200.0埃的范围中选择，而台阶高度124的标称值可以从400.0-5700.0埃的范围中选择。在本发明的一个实施例中，插栓凸出量122约为700.0-2200.0埃，跨越衬底100的范围小于8.0％；而台阶高度124约为1100.0-3800.0埃，跨越衬底100的范围小于12.0％。
在多数情况下，对插栓凸出量122的控制应该比台阶高度124更严格。通常，台阶高度124应该不大于绝缘体103的原始厚度的50％。由此，使氧化凸出量(插栓凸出量122与台阶高度124之间的差异)最小化，就有可能用更薄的绝缘体103实现理想的插栓凸出量122。
在完成了衬底100上的CMP工艺之后，可以进行缺陷检查。可以使用工具，如来自KLA-Tencor的AIT系统。当需要时，可以使用扫描电子显微镜(SEM)对具体缺陷进行表征和识别。可以使用的工具包括来自Applied Materials的SEMVisionTM系统。通过后处理软件可以提供自动缺陷分类(automated defect classification，ADC)。
在进行CMP之后发现的缺陷可能不是由CMP工艺直接引起的。相反，某些缺陷可能来自于前面的工艺，例如在形成绝缘体103、开口105、阻挡层115、晶种层120或者导体130期间。
在完成第二CMP工艺之后，可以用凸出插栓形成用于衬底的凸起触点。例如，如图2所示，可以将用于第一衬底210的第一凸起触点211与用于第二衬底220的第二凸起触点221相互连接。
图2中还示出了按照本发明的结构2000的实施例。结构2000包括用于第一衬底210的第一凸起触点211，它与用于第二衬底220的第二凸起触点221相互连接。在一个实施例中，凸起触点211使信号能够输入到与衬底210的下衬层202中的器件的有源区域相连接的焊盘204，或者从焊盘204输出。
外形变化可能引起两个或多个衬底210、220的凸起触点211、221之间的相互连接恶化。这种不希望的外形变化可能是由凹陷、腐蚀或者导体130变薄引起的。由凹陷和腐蚀引起的外形变化后果可以利用AFM或者HRP进行测量并可视化。可以使用工具，如来自Veeco Instruments的DimensionTM系统。也可以对表面粗糙以及暴露的缺陷如残渣、划痕和空隙等外形变化后果进行测量。
跨越衬底100的插栓凸出量122和台阶高度124的标称值和一致性可能受腐蚀影响。通过在插栓群或阵列137的外面添加假插栓(dummyplug)，可以使腐蚀最小。在尺寸、形状或布局上，假插栓可以与(在凸起触点211、221中的)功能插栓不同。在一个实施例中，假插栓比(在凸起触点211、221中的)功能插栓更宽，因此可以通过下陷有意地使假插栓的高度减小。
可以有意地将假插栓群或阵列137插入场效应区中的某些位置，以便对跨越衬底100的绝缘体103的下陷进行控制。假插栓的位置取决于各种参数，包括衬底100的尺寸(如长度、宽度、厚度)、衬底100的平整度、衬底100的同面性以及(在凸起触点211、221中的)功能插栓的位置。
在第一实施例中，假插栓与(在凸起触点211、221中的)功能插栓仅被包括在衬底100的最后层(顶层)中。在第二实施例中，假插栓与衬底100的一个或多个下衬层中的其它结构和构造连接，以产生理想的外形。在第三实施例中，可以将包括在两个或多个层中的假插栓垂直叠放。可以将假插栓接地(否则将处于悬浮状态)，以防止下衬层102中的器件在运行期间的寄生电容。
为了提供对本发明的透彻理解，以上已经对许多实施例和很多细节进行了描述。本领域技术人员应该明白，在一个实施例中的许多特性同样可以应用于其它实施例。本领域技术人员应该具有对这里所描述的那些具体材料、工艺、尺寸和浓度等进行各种等价物替换的能力。还应该理解对本发明的详细描述是说明性的而非限制性的，其中，应该由所附的权利要求对本发明的范围加以限定。
由此，我们已经描述了形成用于衬底之间的相互连接的凸起触点的方法以及具有这种凸起触点的结构。

Claims (18)

1.一种方法，包括：
提供第一衬底；
在所述第一衬底之上形成绝缘体；
在所述绝缘体中形成开口；
在所述绝缘体之上以及所述开口中形成导体；
用第一化学机械抛光工艺除掉在所述绝缘体之上的所述导体，以便留下在所述开口中的所述导体；以及
用第二化学机械抛光工艺减小所述绝缘体的厚度，以使在所述开口中的所述导体凸出。
2.如权利要求1所述的方法，其中，所述绝缘体包括二氧化硅。
3.如权利要求1所述的方法，其中，所述绝缘体包括低k材料。
4.如权利要求1所述的方法，其中，所述绝缘体包括超低k材料。
5.如权利要求1所述的方法，其中，所述导体包括铜。
6.一种方法，包括：
在第一衬底上提供焊盘；
在所述焊盘之上形成电介质；
在所述电介质中形成通道以暴露所述焊盘；
在所述电介质之上形成金属以填充所述通道；
用第一化学机械抛光工艺除掉在所述电介质之上的所述金属，以在所述通道中形成插栓；以及
用第二化学机械抛光工艺使所述电介质下陷，以便从所述插栓形成第一凸起触点。
7.如权利要求6所述的方法，还包括：
在形成所述通道之后且在形成所述金属之前形成阻挡层；以及
在除掉所述金属之后且在使所述电介质下陷之前除掉在所述电介质之上的所述阻挡层。
8.如权利要求7所述的方法，其中，所述第一化学机械抛光工艺包括第一步骤，用于除掉在所述绝缘体之上的所述导体的大部分覆盖层。
9.如权利要求8所述的方法，其中，所述第一步骤可以是定时抛光或者可以通过就地监控一个诸如厚度或涡电流之类的参数对其进行控制。
10.如权利要求8所述的方法，其中，所述第一化学机械抛光工艺还包括第二步骤，用于清除所述导体以暴露所述阻挡层。
11.如权利要求10所述的方法，其中，所述第二步骤可以是定时抛光或者是终点抛光。
12.如权利要求7所述的方法，还包括：
在形成所述阻挡层之后且在形成所述金属之前形成晶种层。
13.如权利要求12所述的方法，还包括：
使用电镀法在所述晶种层之上形成所述金属。
14.如权利要求6所述的方法，其中，所述第二化学机械抛光工艺包括：
约为每平方英寸4.0-6.0磅的抛光压强。
15.如权利要求14所述的方法，其中，所述第二化学机械抛光工艺包括：
约为每分钟20.0-140.0英尺的台板线速度。
16.一种方法，包括：
提供第一衬底；
在所述第一衬底之上形成电介质；
在所述电介质中形成通道以暴露所述第一衬底；
在所述电介质之上形成金属以填充所述通道；
用第一化学机械抛光工艺除掉在所述电介质之上的所述金属，以便在所述通道中形成插栓；
用第二化学机械抛光工艺使所述电介质下陷，以便从所述插栓形成第一凸起触点；以及
将所述第一凸起触点与在第二衬底上的第二凸起触点相互连接。
17.如权利要求16所述的方法，其中，使所述电介质下陷产生一个大约700.0-2200.0埃的插栓凸出量。
18.如权利要求16所述的方法，其中，使所述电介质下陷产生一个大约1100.0-3800.0埃的台阶高度。
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CN105428328A (zh) * 2014-09-19 2016-03-23 矽品精密工业股份有限公司 半导体结构及其制法

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CN100361289C (zh) 2008-01-09
WO2004001814A2 (en) 2003-12-31
TWI240297B (en) 2005-09-21
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EP1438744B1 (en) 2014-01-29
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