CN1543604B - 带有片上后台调试系统的数据处理系统和相关方法 - Google Patents
带有片上后台调试系统的数据处理系统和相关方法 Download PDFInfo
- Publication number
- CN1543604B CN1543604B CN018227937A CN01822793A CN1543604B CN 1543604 B CN1543604 B CN 1543604B CN 018227937 A CN018227937 A CN 018227937A CN 01822793 A CN01822793 A CN 01822793A CN 1543604 B CN1543604 B CN 1543604B
- Authority
- CN
- China
- Prior art keywords
- background
- data processing
- clock unit
- debug
- processing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/788,816 | 2001-02-21 | ||
| US09/788,816 US6823224B2 (en) | 2001-02-21 | 2001-02-21 | Data processing system having an on-chip background debug system and method therefor |
| PCT/US2001/049157 WO2002069146A2 (en) | 2001-02-21 | 2001-12-18 | Data processing system having an on-chip background debug system and method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1543604A CN1543604A (zh) | 2004-11-03 |
| CN1543604B true CN1543604B (zh) | 2012-05-30 |
Family
ID=25145644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN018227937A Expired - Fee Related CN1543604B (zh) | 2001-02-21 | 2001-12-18 | 带有片上后台调试系统的数据处理系统和相关方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6823224B2 (enExample) |
| EP (1) | EP1423789A2 (enExample) |
| JP (1) | JP4145146B2 (enExample) |
| KR (1) | KR100819720B1 (enExample) |
| CN (1) | CN1543604B (enExample) |
| AU (1) | AU2002227439A1 (enExample) |
| TW (1) | TW533350B (enExample) |
| WO (1) | WO2002069146A2 (enExample) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7065481B2 (en) * | 1999-11-30 | 2006-06-20 | Synplicity, Inc. | Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer |
| US7072818B1 (en) | 1999-11-30 | 2006-07-04 | Synplicity, Inc. | Method and system for debugging an electronic system |
| US7240303B1 (en) | 1999-11-30 | 2007-07-03 | Synplicity, Inc. | Hardware/software co-debugging in a hardware description language |
| US7222315B2 (en) | 2000-11-28 | 2007-05-22 | Synplicity, Inc. | Hardware-based HDL code coverage and design analysis |
| US7827510B1 (en) | 2002-06-07 | 2010-11-02 | Synopsys, Inc. | Enhanced hardware debugging with embedded FPGAS in a hardware description language |
| US7003698B2 (en) * | 2002-06-29 | 2006-02-21 | Intel Corporation | Method and apparatus for transport of debug events between computer system components |
| US6895530B2 (en) * | 2003-01-24 | 2005-05-17 | Freescale Semiconductor, Inc. | Method and apparatus for controlling a data processing system during debug |
| US7210059B2 (en) | 2003-08-19 | 2007-04-24 | Micron Technology, Inc. | System and method for on-board diagnostics of memory modules |
| US7310752B2 (en) | 2003-09-12 | 2007-12-18 | Micron Technology, Inc. | System and method for on-board timing margin testing of memory modules |
| US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
| US7216196B2 (en) * | 2003-12-29 | 2007-05-08 | Micron Technology, Inc. | Memory hub and method for memory system performance monitoring |
| JP4409349B2 (ja) * | 2004-04-27 | 2010-02-03 | Okiセミコンダクタ株式会社 | デバッグ回路およびデバッグ制御方法 |
| US7216259B2 (en) | 2004-04-28 | 2007-05-08 | Via Telecom Co., Ltd. | Increment power saving in battery powered wireless system with software configuration |
| US7310748B2 (en) | 2004-06-04 | 2007-12-18 | Micron Technology, Inc. | Memory hub tester interface and method for use thereof |
| US20060075124A1 (en) * | 2004-10-01 | 2006-04-06 | Michael Joseph Dougherty | Automatic activation and deactivation of wireless network adapter |
| US20060161818A1 (en) * | 2005-01-14 | 2006-07-20 | Ivo Tousek | On-chip hardware debug support units utilizing multiple asynchronous clocks |
| US7550991B2 (en) | 2005-07-15 | 2009-06-23 | Tabula, Inc. | Configurable IC with trace buffer and/or logic analyzer functionality |
| US7375550B1 (en) * | 2005-07-15 | 2008-05-20 | Tabula, Inc. | Configurable IC with packet switch configuration network |
| US8069425B2 (en) | 2007-06-27 | 2011-11-29 | Tabula, Inc. | Translating a user design in a configurable IC for debugging the user design |
| US7839162B2 (en) | 2007-06-27 | 2010-11-23 | Tabula, Inc. | Configurable IC with deskewing circuits |
| US8412990B2 (en) | 2007-06-27 | 2013-04-02 | Tabula, Inc. | Dynamically tracking data values in a configurable IC |
| US7652498B2 (en) | 2007-06-27 | 2010-01-26 | Tabula, Inc. | Integrated circuit with delay selecting input selection circuitry |
| WO2009039462A1 (en) | 2007-09-19 | 2009-03-26 | Tabula, Inc. | Method and system for reporting on a primary circuit structure of an integrated circuit (ic) using a secondary circuit structure of the ic |
| US8525548B2 (en) * | 2008-08-04 | 2013-09-03 | Tabula, Inc. | Trigger circuits and event counters for an IC |
| US8165253B2 (en) * | 2008-08-28 | 2012-04-24 | Agere Systems Inc. | Methods and apparatus for serializer/deserializer transmitter synchronization |
| US8072234B2 (en) | 2009-09-21 | 2011-12-06 | Tabula, Inc. | Micro-granular delay testing of configurable ICs |
| CN101876928B (zh) * | 2009-11-13 | 2012-07-25 | 北京全路通信信号研究设计院有限公司 | 一种二乘二取二系统的同步方法和设备 |
| JP5467891B2 (ja) | 2010-02-19 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 情報処理装置、デバッグ装置、デバッグ方法 |
| KR101992234B1 (ko) | 2012-05-22 | 2019-06-24 | 삼성전자주식회사 | 디버깅 회로를 위한 클럭 제어 회로를 구비하는 집적 회로 및 이를 포함하는 시스템-온-칩 |
| US20150012903A1 (en) | 2013-07-04 | 2015-01-08 | Tabula, Inc. | Non-intrusive monitoring and control of integrated circuits |
| CN104679617B (zh) * | 2013-11-27 | 2019-01-04 | 展讯通信(上海)有限公司 | 一种调试系统 |
| US9684578B2 (en) | 2014-10-30 | 2017-06-20 | Qualcomm Incorporated | Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems |
| TWI628531B (zh) * | 2017-05-31 | 2018-07-01 | 北京集創北方科技股份有限公司 | Clock control circuit and controller |
| US20250109930A1 (en) | 2023-10-03 | 2025-04-03 | Louisiana-Pacific Corporation | Foam depth inspection gauge |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5361392A (en) * | 1988-11-10 | 1994-11-01 | Motorola, Inc. | Digital computing system with low power mode and special bus cycle therefor |
| US5434804A (en) * | 1993-12-29 | 1995-07-18 | Intel Corporation | Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal |
| US5677849A (en) * | 1993-11-08 | 1997-10-14 | Cirrus Logic, Inc. | Selective low power clocking apparatus and method |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3781803A (en) * | 1972-04-10 | 1973-12-25 | Bendix Corp | Collision avoidance system ground station synchronization |
| US5218704A (en) * | 1989-10-30 | 1993-06-08 | Texas Instruments | Real-time power conservation for portable computers |
| EP0745290A4 (en) * | 1994-02-17 | 1999-07-14 | Micrilor Inc | WIRELESS LOCAL NETWORK WITH HIGH DATA RATE |
| JP3497315B2 (ja) | 1996-01-17 | 2004-02-16 | 株式会社リコー | シリアルインターフェースを用いた通信方式 |
| US5838692A (en) * | 1996-11-14 | 1998-11-17 | Hewlett-Packard Company | System and method for extracting realtime debug signals from an integrated circuit |
| US6154856A (en) * | 1997-04-08 | 2000-11-28 | Advanced Micro Devices, Inc. | Debug interface including state machines for timing synchronization and communication |
| US6389557B1 (en) * | 1998-09-16 | 2002-05-14 | Advanced Micro Devices, Inc. | Freezing mechanism for debugging |
| JP2000155701A (ja) * | 1998-11-18 | 2000-06-06 | Mitsubishi Electric Corp | デバッグ回路 |
| US6173386B1 (en) * | 1998-12-14 | 2001-01-09 | Cisco Technology, Inc. | Parallel processor with debug capability |
| US6442725B1 (en) * | 1999-02-18 | 2002-08-27 | Agilent Technologies, Inc. | System and method for intelligent analysis probe |
| US6151487A (en) * | 1999-08-31 | 2000-11-21 | Hughes Electronics Corporation | Demodulation structure for fast fading cellular channels |
-
2001
- 2001-02-21 US US09/788,816 patent/US6823224B2/en not_active Expired - Lifetime
- 2001-12-18 JP JP2002568201A patent/JP4145146B2/ja not_active Expired - Fee Related
- 2001-12-18 WO PCT/US2001/049157 patent/WO2002069146A2/en not_active Ceased
- 2001-12-18 CN CN018227937A patent/CN1543604B/zh not_active Expired - Fee Related
- 2001-12-18 EP EP01996290A patent/EP1423789A2/en not_active Withdrawn
- 2001-12-18 AU AU2002227439A patent/AU2002227439A1/en not_active Abandoned
- 2001-12-18 KR KR1020037010937A patent/KR100819720B1/ko not_active Expired - Fee Related
- 2001-12-20 TW TW090131692A patent/TW533350B/zh not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5361392A (en) * | 1988-11-10 | 1994-11-01 | Motorola, Inc. | Digital computing system with low power mode and special bus cycle therefor |
| US5677849A (en) * | 1993-11-08 | 1997-10-14 | Cirrus Logic, Inc. | Selective low power clocking apparatus and method |
| US5434804A (en) * | 1993-12-29 | 1995-07-18 | Intel Corporation | Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1423789A2 (en) | 2004-06-02 |
| JP2005508531A (ja) | 2005-03-31 |
| TW533350B (en) | 2003-05-21 |
| KR100819720B1 (ko) | 2008-04-07 |
| US20020116081A1 (en) | 2002-08-22 |
| KR20030075202A (ko) | 2003-09-22 |
| US6823224B2 (en) | 2004-11-23 |
| WO2002069146A3 (en) | 2004-04-08 |
| WO2002069146A2 (en) | 2002-09-06 |
| AU2002227439A1 (en) | 2002-09-12 |
| CN1543604A (zh) | 2004-11-03 |
| JP4145146B2 (ja) | 2008-09-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: FISICAL SEMICONDUCTOR INC. Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: FREESCALE SEMICONDUCTOR, Inc. Address before: Texas in the United States Patentee before: FreeScale Semiconductor |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20191218 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |