KR100819720B1 - 온 칩 백그라운드 디버그 시스템 및 그 방법을 갖는데이터 처리 시스템 - Google Patents

온 칩 백그라운드 디버그 시스템 및 그 방법을 갖는데이터 처리 시스템 Download PDF

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KR100819720B1
KR100819720B1 KR1020037010937A KR20037010937A KR100819720B1 KR 100819720 B1 KR100819720 B1 KR 100819720B1 KR 1020037010937 A KR1020037010937 A KR 1020037010937A KR 20037010937 A KR20037010937 A KR 20037010937A KR 100819720 B1 KR100819720 B1 KR 100819720B1
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South Korea
Prior art keywords
data processing
background debug
processing system
clock unit
synchronization
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Korean (ko)
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KR20030075202A (ko
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우드마이클씨
베커조지이
시빅트러스제임스엠
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프리스케일 세미컨덕터, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
KR1020037010937A 2001-02-21 2001-12-18 온 칩 백그라운드 디버그 시스템 및 그 방법을 갖는데이터 처리 시스템 Expired - Fee Related KR100819720B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/788,816 2001-02-21
US09/788,816 US6823224B2 (en) 2001-02-21 2001-02-21 Data processing system having an on-chip background debug system and method therefor
PCT/US2001/049157 WO2002069146A2 (en) 2001-02-21 2001-12-18 Data processing system having an on-chip background debug system and method therefor

Publications (2)

Publication Number Publication Date
KR20030075202A KR20030075202A (ko) 2003-09-22
KR100819720B1 true KR100819720B1 (ko) 2008-04-07

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KR1020037010937A Expired - Fee Related KR100819720B1 (ko) 2001-02-21 2001-12-18 온 칩 백그라운드 디버그 시스템 및 그 방법을 갖는데이터 처리 시스템

Country Status (8)

Country Link
US (1) US6823224B2 (enExample)
EP (1) EP1423789A2 (enExample)
JP (1) JP4145146B2 (enExample)
KR (1) KR100819720B1 (enExample)
CN (1) CN1543604B (enExample)
AU (1) AU2002227439A1 (enExample)
TW (1) TW533350B (enExample)
WO (1) WO2002069146A2 (enExample)

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US7240303B1 (en) 1999-11-30 2007-07-03 Synplicity, Inc. Hardware/software co-debugging in a hardware description language
US7222315B2 (en) 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US7003698B2 (en) * 2002-06-29 2006-02-21 Intel Corporation Method and apparatus for transport of debug events between computer system components
US6895530B2 (en) * 2003-01-24 2005-05-17 Freescale Semiconductor, Inc. Method and apparatus for controlling a data processing system during debug
US7210059B2 (en) 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7310752B2 (en) 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7216196B2 (en) * 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
JP4409349B2 (ja) * 2004-04-27 2010-02-03 Ｏｋｉセミコンダクタ株式会社 デバッグ回路およびデバッグ制御方法
US7216259B2 (en) 2004-04-28 2007-05-08 Via Telecom Co., Ltd. Increment power saving in battery powered wireless system with software configuration
US7310748B2 (en) 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
US20060075124A1 (en) * 2004-10-01 2006-04-06 Michael Joseph Dougherty Automatic activation and deactivation of wireless network adapter
US20060161818A1 (en) * 2005-01-14 2006-07-20 Ivo Tousek On-chip hardware debug support units utilizing multiple asynchronous clocks
US7550991B2 (en) 2005-07-15 2009-06-23 Tabula, Inc. Configurable IC with trace buffer and/or logic analyzer functionality
US7375550B1 (en) * 2005-07-15 2008-05-20 Tabula, Inc. Configurable IC with packet switch configuration network
US8069425B2 (en) 2007-06-27 2011-11-29 Tabula, Inc. Translating a user design in a configurable IC for debugging the user design
US7839162B2 (en) 2007-06-27 2010-11-23 Tabula, Inc. Configurable IC with deskewing circuits
US8412990B2 (en) 2007-06-27 2013-04-02 Tabula, Inc. Dynamically tracking data values in a configurable IC
US7652498B2 (en) 2007-06-27 2010-01-26 Tabula, Inc. Integrated circuit with delay selecting input selection circuitry
WO2009039462A1 (en) 2007-09-19 2009-03-26 Tabula, Inc. Method and system for reporting on a primary circuit structure of an integrated circuit (ic) using a secondary circuit structure of the ic
US8525548B2 (en) * 2008-08-04 2013-09-03 Tabula, Inc. Trigger circuits and event counters for an IC
US8165253B2 (en) * 2008-08-28 2012-04-24 Agere Systems Inc. Methods and apparatus for serializer/deserializer transmitter synchronization
US8072234B2 (en) 2009-09-21 2011-12-06 Tabula, Inc. Micro-granular delay testing of configurable ICs
CN101876928B (zh) * 2009-11-13 2012-07-25 北京全路通信信号研究设计院有限公司 一种二乘二取二系统的同步方法和设备
JP5467891B2 (ja) 2010-02-19 2014-04-09 ルネサスエレクトロニクス株式会社 情報処理装置、デバッグ装置、デバッグ方法
KR101992234B1 (ko) 2012-05-22 2019-06-24 삼성전자주식회사 디버깅 회로를 위한 클럭 제어 회로를 구비하는 집적 회로 및 이를 포함하는 시스템-온-칩
US20150012903A1 (en) 2013-07-04 2015-01-08 Tabula, Inc. Non-intrusive monitoring and control of integrated circuits
CN104679617B (zh) * 2013-11-27 2019-01-04 展讯通信（上海）有限公司 一种调试系统
US9684578B2 (en) 2014-10-30 2017-06-20 Qualcomm Incorporated Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems
TWI628531B (zh) * 2017-05-31 2018-07-01 北京集創北方科技股份有限公司 Clock control circuit and controller
US20250109930A1 (en) 2023-10-03 2025-04-03 Louisiana-Pacific Corporation Foam depth inspection gauge

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US5434804A (en) 1993-12-29 1995-07-18 Intel Corporation Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal
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Also Published As

Publication number Publication date
EP1423789A2 (en) 2004-06-02
JP2005508531A (ja) 2005-03-31
CN1543604B (zh) 2012-05-30
TW533350B (en) 2003-05-21
US20020116081A1 (en) 2002-08-22
KR20030075202A (ko) 2003-09-22
US6823224B2 (en) 2004-11-23
WO2002069146A3 (en) 2004-04-08
WO2002069146A2 (en) 2002-09-06
AU2002227439A1 (en) 2002-09-12
CN1543604A (zh) 2004-11-03
JP4145146B2 (ja) 2008-09-03

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