CN1534741A - 金属氧化膜的形成方法 - Google Patents

金属氧化膜的形成方法 Download PDF

Info

Publication number
CN1534741A
CN1534741A CNA2004100313924A CN200410031392A CN1534741A CN 1534741 A CN1534741 A CN 1534741A CN A2004100313924 A CNA2004100313924 A CN A2004100313924A CN 200410031392 A CN200410031392 A CN 200410031392A CN 1534741 A CN1534741 A CN 1534741A
Authority
CN
China
Prior art keywords
film
metal
oxide
metal oxide
capacitor insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100313924A
Other languages
English (en)
Other versions
CN100364067C (zh
Inventor
С��һ��
小柳贤一
佐久间浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Publication of CN1534741A publication Critical patent/CN1534741A/zh
Application granted granted Critical
Publication of CN100364067C publication Critical patent/CN100364067C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/405Oxides of refractory metals or yttrium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/3141Deposition using atomic layer deposition techniques [ALD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31637Deposition of Tantalum oxides, e.g. Ta2O5
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种形成电容绝缘膜的方法,包括的步骤是:通过供给包括金属而不含氧的金属源,在底膜上沉积由金属构成的单原子膜,采用CVD技术沉积包含所述金属的金属氧化膜。这种方法能够高生产量地提供具有更好的膜特性的金属氧化膜。

Description

金属氧化膜的形成方法
技术领域
本发明涉及金属氧化膜的形成方法,特别是涉及高生产量地形成具有良好的台阶覆盖性和膜质的金属氧化膜的金属氧化膜的形成方法。
背景技术
随着近几年DRAM的高集成化,电容元件的微型化也在推进。作为电容绝缘膜,一般采用氮化硅膜,通过结构复杂化、表面积增加来解决电容不足的问题。可是,微型化和表面积的增加具有折衷的关系,利用氮化硅膜作为电容绝缘膜的局限性在于,不能期望电容元件的静电电容大幅度增加。因此,人们一直在寻求高介电材料作为DRAM用的电容绝缘膜,特别是氧化钽膜,一直以来就被看好,正在被广泛地研究。这是因为氮化硅膜的相对介电常数为7左右,而氧化钽膜的相对介电常数为25以上,电容可望增加3倍以上。
以前,采用CVD(化学气相沉积)法来形成电容绝缘膜。在CVD法中,在反应室内设有使电容绝缘膜生长的衬底,使衬底温度保持规定的值,并同时供给金属化合物气体和O2气体,使其在衬底上进行反应而生长为电容绝缘膜。例如,在形成由氧化钽膜构成的电容绝缘膜时,同时供给作为金属源的Ta(OC2H5)5气体和O2气体。CVD法简易且能够进行高速的电容绝缘膜的成膜。
但是,在CVD法中,存在底膜构造复杂以及膜厚的均匀性恶化的问题。例如在电容元件中,为了使静电电容增加,一般在具有复杂的台阶构造的底膜上形成电容绝缘膜。在这种底膜上,如果一边提高反应速度一边进行CVD生长,膜厚的均匀性就会变差,在底膜的台阶部分,膜厚的不均匀就会变得明显。即,台阶覆盖性降低。此外,如果为回避这一点,一边降低反应速度一边进行CVD生长的话,虽然提高了膜厚的均匀性,但是增加了除去杂质的难度,因而膜中的杂质浓度就很高,于是膜的密度下降,从而导致膜质降低。
此外,如果在用CVD法使电容绝缘膜生长时,如果底膜与电容绝缘膜的材质有很大不同,培育时间就不可避免。即,在形成电容绝缘膜时,首先在底膜上形成分散的核,然后电容绝缘膜在形成的核的周围生长。因此,在核的附近区域和其它区域之间,形成的电容绝缘膜的膜厚变得不均匀,使前述的台阶覆盖性更加降低,成为缺陷的原因。如果缩短孕育时间,虽然能够达到均匀的膜厚,但在这种情况下的问题是底膜的材质受到限制。
针对上述问题,专利文献1提出采用单原子层生长(ALD:AtomicLayer Deposition)法:在形成由氧化钽膜等高介电常数(高k)电介质构成的电容绝缘膜时,通过每次一原子层(一分子层)来逐次进行成膜,从而形成所期望的膜。图7是表示根据专利文献1中记载的方法、由氧化钽膜构成的电容绝缘膜的形成步骤的流程图。
根据专利文献1,在形成氧化钽膜时,在反应室内设置硅衬底,把衬底温度设定在300℃左右,首先,把H2O气体等氧化性气体供给到反应室,对硅衬底的表面进行氧化(步骤A1)。这样,OH基就与硅衬底表面进行结合。这时,因为OH基与硅衬底表面的键进行化学键合,所以即使供给过剩的H2O气体,也只形成一分子层的OH基。此后,把N2气体供给到反应室,把未反应的H2O气体从反应室清除(步骤A2),接着,进行真空抽吸(步骤A3)。
其次,把TaCl5气体供给到反应室(步骤A4)。这样,与硅衬底表面结合的OH基的H原子和TaCl5气体的TaCl4基进行置换,在硅衬底表面形成与O原子结合的单层的TaCl4层。接着,把N2气体供给到反应室,把未反应的TaCl5气体从反应室清除(步骤A5),进行真空抽吸(步骤A6)。
接着,把H2O气体供给到反应室(步骤A7)。这样,硅衬底表面的TaCl4基中的Cl被H2O气体的OH基置换。此后,把N2气体供给到反应室,把未反应的H2O气体从反应室清除(步骤A8),进行真空抽吸(步骤A9)。
在步骤A4及步骤A7中,分别利用在硅衬底表面的置换反应使其生长,因此可以把步骤A4至步骤A9作为一个循环,使一分子层的氧化钽膜生长。于是,反复进行该循环,直到氧化钽膜达到期望的膜厚,这样就能够形成由氧化钽(Ta2O5)膜构成的电容绝缘膜。
专利文献1:特开2002-164348号公报
如上所述,采用ALD法形成电容绝缘膜时,由于可以在硅衬底上按每一分子层来使氧化钽膜生长,不需要象CVD法那样形成核,因此能够形成膜厚均匀、具有良好的台阶覆盖性及膜质的电容绝缘膜。
但是,根据ALD法,由于使氧化钽膜按每一分子层生长,因而存在生长中要花费许多时间的问题。例如在形成5nm的氧化钽膜时,把步骤A4至步骤A9作为一个循环,一个循环需要1分钟左右的生长时间,总计就需要50分钟左右的时间。在这里,如果缩短步骤A4至步骤A9的各循环的时间的话,就会产生以下的问题。
即,在步骤A4中如果TaCl5气体(金属化合物气体)的供给时间不足的话,就不能均匀地形成单层的TaCl4层,所形成的氧化钽层的膜厚及膜质就不均匀,同时,膜密度降低,其电特性恶化。此外,在步骤A7中如果H2O气体(氧化性气体)的供给时间不足的话,单层的TaCl4层中杂质的消除和表面的氧化处理就不能充分进行,形成的氧化钽膜的膜质及电特性就会恶化。
因此,由ALD法形成质量良好的电容绝缘膜,与由CVD法形成同样膜厚的电容绝缘膜所需时间(2分钟左右)相比,需要非常长的时间。因此,由ALD法形成电容绝缘膜的方法,生产量低,不实用。
此外,由ALD法形成电容绝缘膜时,存在以下问题:必须在每一分子层生长中交替供给TaCl5气体(金属化合物气体)和H2O气体(氧化性气体),接着,供给N2气体等惰性气体,把残余气体清除,进行真空抽吸,因此,必须使阀门多次动作,操作繁杂。
本发明的目的是提供一种解决上述问题点、高生产量地形成具有良好的台阶覆盖性和膜质的金属氧化膜的金属氧化膜形成方法。
发明内容
鉴于上述情况,本发明的目的是解决上述问题,提供一种在半导体器件的生产中以高生产量形成具有良好的台阶覆盖性和膜质的金属氧化膜的方法。
本发明提供一种形成半导体器件的方法,包括以下步骤:
在底膜上沉积包含一种金属的单原子膜,采用的金属源包含所述金属且不含氧;采用CVD技术在所述单原子膜上沉积包含所述金属的氧化物的金属氧化膜。
根据本发明的方法,沉积在所述底膜上的所述单原子膜使得在金属氧化膜的沉积步骤中能够以高生产量获得具有良好的膜特性的金属氧化膜。
下面参照附图进行说明,将会使本发明的上述以及其它目的、特点以及优点更加清楚。
附图说明
图1(a)~(c)是分别表示第1实施例的电容元件的各制造工序阶段的剖面图。
图2是表示第1实施例的形成电容绝缘膜所用的装置的俯视图。
图3是表示第1实施例的电容绝缘膜的形成方法的流程图。
图4(a)~(d)是分别表示第1实施例的、形成电容绝缘膜的各阶段的化学反应的剖面示意图。
图5是表示根据第1实施例的电容绝缘膜的形成方法所形成的电容绝缘膜的随时间绝缘击穿(TDDB)试验结果的图表。
图6是表示第3实施例的电容绝缘膜的形成方法的流程图。
图7是表示采用专利文献1记载的ALD法的电容绝缘膜的形成步骤的流程图。
具体实施方式
以下,参照附图,根据本发明的实施例对本发明进行更加详细地说明。
第1实施例
本实施例是把本发明应用于由氧化钽膜构成的电容绝缘膜的形成方法的实施方式的一例,图1(a)~(c)是表示其结构的剖面图。在本实施例中,作为形成电容绝缘膜的前阶段的工序,进行到形成电容绝缘膜的底膜的工序为止。该前工序如下进行。首先,如图1(a)所示,在硅衬底11上形成由氧化硅膜构成的第1层间绝缘膜12。其次,形成贯通第1层间绝缘膜12、到达硅衬底11的接触孔13a,然后,用掺磷多晶硅埋入接触孔13a,形成接触芯柱13。
接着,如图1(b)所示,在第1层间绝缘膜12及接触芯柱13上面,形成由氧化硅膜构成的第2层间绝缘膜14。接着,形成贯通第2层间绝缘膜14、到达第1层间绝缘膜12及接触芯柱13的节点孔15a。
接着,在形成了节点孔15a的第2层间绝缘膜14上面,形成作为下部电极的、由掺磷多晶硅构成的HSG(Hemi Spherical Grain,半球颗粒)层15。接着,采用RTN(Rapid Thermal Nitrization,快速热氮化)法,对HSG层15的表面进行氮化,形成作为底膜的氮化硅膜16。
接着,转向电容绝缘膜的形成。图2是表示进行电容绝缘膜的形成的装置的俯视图。同图中,第1反应室22是能够采用ALD法成膜等的室,第2反应室23是能够采用CVD法成膜等的室。此外,转移室24是用于使形成电容绝缘膜的晶片(衬底)21进行移动的室,设有使晶片(衬底)21在第1反应室22和第2反应室23之间进行移动的机器手25。通常时保持为真空状态。另外,同图中,对电容绝缘膜以外的形成所需的装置未图示。
图3是表示本实施例的电容绝缘膜的形成方法的流程图。首先,把RTN处理后的晶片21移到第1反应室22,使衬底温度保持在300℃,且使第1反应室22内的气压保持在400Pa,同时持续10秒钟供给流量50 SCCM的H2O气体(步骤S1)。这样,如图4(a)所示,OH基与氮化硅膜16的表面结合。接着,以流量2 SLM供给N2气体,如图4(b)所示,把未反应的H2O气体从第1反应室22清除(步骤S2)。接着,进行10秒钟真空抽吸(步骤S3)。
接着,把TaCl5气体以流量50 SCCM、持续10秒钟供给到第1反应室22(步骤S4)。这样,如图4(c)所示,与氮化硅膜表面结合的OH基中的H原子和TaCl5气体的TaCl4基置换,在氮化硅膜16的表面形成由与O原子结合的单层(一分子层)TaCl4基构成的籽晶层。如此形成的籽晶层,与用ALD法成膜的情况相同,具有均匀的膜厚及良好的膜质。接着,以流量2 SLM供给N2气体,如图4(d)所示,把未反应的TaCl5气体从第1反应室22清除(步骤S5)。接着,进行10秒钟真空抽吸(步骤S6)。
接着,使晶片21经由转移室24移动到第2反应室23,采用CVD法,使衬底温度保持在430℃,第2反应室23内的压力保持在400Pa,同时,把流量200mg/min的Ta(OC2H5)5气体和流量1.5 SLM的O2气体同时供给到第2反应室23(步骤S7)。这样,衬底表面的TaCl4基的Cl原子和O2分子置换,形成TaO2层。再在它之上进行氧化钽膜的体层的生长,就能够形成如图1(C)所示的由氧化钽膜构成的电容绝缘膜17。
在这种情况下,由于用CVD法形成的氧化钽层与其籽晶层的材质相同,因此不形成核就能够进行沉积。例如,通过供给4分钟左右的气体,能够获得膜厚10nm左右的氧化钽膜。而且,通过在电容绝缘膜17上面形成作为上部电极的TiN膜18等,就能够形成电容元件19。
在本实施例的电容绝缘膜的形成方法中,为了在具有相同材质的籽晶层上使氧化钽膜的体层生长,不必如现有的CVD法那样在底膜上形成分散的核,就能够形成具有良好的台阶覆盖性及膜质的电容绝缘膜。这样,只有籽晶层的形成是采用与ALD法同样的方法,在此后体层的生长中则采用CVD法使其生长,因而就实现了能够以高生产量形成电容绝缘膜的电容绝缘膜形成方法。
另外,在本实施例中,从步骤S1到步骤S6在第1反应室22中进行,步骤S7在第2反应室23中进行,而在从步骤S1到步骤S6与步骤S7的成膜温度(衬底温度)差小的情况下,可以在一个反应室中连续进行从步骤S1到步骤S7的工序。例如,在温度差为40℃以下的情况下,使衬底温度变化的时间也短,因此,即使在一个反应室中连续进行也能够维持大的生产量。
图5是表示采用本实施例的电容绝缘膜的形成方法、CVD法以及ALD法分别形成的由氧化钽膜构成的电容绝缘膜的随时间绝缘击穿(TDDB:Time Dependent Dielectric Breakdown)试验的结果的图表。同图中,纵轴表示威布尔(Weibull)分布,横轴表示绝缘击穿发生的时间(秒),分别为约40个样本的绝缘击穿时间按威布尔分布的情况。试验中,所有的样本都是在电容绝缘膜的膜厚为10nm、环境温度85℃、对电容绝缘膜的应力电压为4.6V的条件下进行的。
根据同图,采用本实施例的电容绝缘膜的形成方法形成的电容绝缘膜,与采用CVD法形成的电容绝缘膜比较,绝缘性大幅度提高,而且显示出与采用ALD法所形成的电容绝缘膜大体上相同的、良好的绝缘性。
在ALD法中,在电容绝缘膜的生长时,为了缩短所需时间,就必须缩短一分子层生长的每一个循环的时间,而实际上存在不能充分确保形成良好的电容绝缘膜的时间的情况。但是,在本实施例中,电容绝缘膜整体的形成时间少,因此,具有能够获得籽晶层形成的充分时间的优点。于是,通过在良好的籽晶层上形成体层,就能够获得良好的电容绝缘膜。
第2实施例
本实施例是把本发明应用于形成由氧化钽膜构成的电容绝缘膜的实施方式的一例,除了在第1实施例的步骤S1中,在同样的条件下,供给活性氧气以取代H2O气体之外,与前述的第1实施例相同。
在本实施例中,通过在步骤S1中供给活性氧气,氧通过氧化与氮化硅膜16的表面结合。于是,通过在步骤S4中供给TaCl5气体,与氮化硅膜16的表面结合的氧TaCl5气体的TaCl4基相结合,从而在氮化硅膜16的表面形成由与O原子结合的单层TaCl4基构成的籽晶层。因此,在本实施例中,与第1实施例相同,使氧化钽膜的体层在具有相同材质的籽晶层上生长,从而不在底膜上形成分散的核就能够获得与第1实施例同样的效果。
第3实施例
本实施例是把本发明应用于形成由氧化钽膜构成的电容绝缘膜的实施方式的一例,图6是表示本实施例的电容绝缘膜的形成方法的流程图。本实施例的电容绝缘膜的形成方法,除了在第1实施例的步骤S6之后重复进行与步骤S1~步骤S3同样的工序,即步骤S1′~步骤S3′之外,与第1实施例相同。
即,在本实施例中,在步骤S6之后,以与步骤S1同样的条件供给H2O气体。这样,TaCl4基中的Cl原子被OH基置换(步骤S1′)。接着,以与步骤S2同样的条件供给N2气体,从第1反应室22中除去残存的H2O气体及在步骤S1′中被置换出来的Cl原子(HCl气体)(步骤S2')。接着,以与步骤S3相同的条件进行真空抽吸(步骤S3′)。
根据本实施例,通过在步骤S6之后进行步骤S1′至步骤S3',在步骤S1'中,用OH基置换与Ta原子结合的Cl原子,并且在步骤S2及步骤S3'中,把置换出来的Cl原子(HCl气体)从第1反应室22完全排出之后,再转移到步骤S7中,因此,抑制了由Cl原子造成的杂质混在电容绝缘膜中的情况,能够形成具有更加良好的膜质的电容绝缘膜。
另外,在第1实施例~第3实施例中,采用TaCl5作为金属源,而也可以采用TaF5、Ta(N(C2H5)2)3等作为金属源。还可以通过采用Al、Ti、Hf以及Nb各自的金属化合物作为金属源,分别形成由氧化铝、氧化钛、氧化铪以及氧化铌构成的金属氧化膜。例如,可以通过采用Al(CH3)3作为金属源来形成氧化铝;通过采用TiCl4、Ti(N(CH3)2)4作为金属源来形成氧化钛;通过采用Hf(N(CH3)2)4、Hf(N(C2H5)(CH3))4、Hf(N(C2H5)2)4作为金属源来形成氧化铪;通过采用NbCl5、NbF5、Nb(N(C2H5)2)3作为金属源来形成氧化铌。
在第1实施例~第3实施例中,采用H2O气体或活性氧作为氧化性气体,而也可以采用O2、臭氧、N2O作为氧化性气体。或者,也可以用氢氟酸进行氢氟酸处理。还有,在第1实施例~第3实施例中,在采用RTN法形成的氮化硅膜上形成金属氧化膜,而也可以在例如硅衬底、多晶硅膜、或金属膜上采用与上述实施例相同的形成方法来形成金属氧化膜。
以上根据优选的实施例对本发明进行了说明,而本发明的金属氧化膜的形成方法,不只限定于上述实施例的构成,根据上述实施例的构成进行各种修正及变更的金属氧化膜的形成方法也包含在本发明的范围中。

Claims (13)

1.一种形成半导体器件的方法,包括以下步骤:
在底膜上沉积包含一种金属的单原子膜,采用的金属源包含所述金属的化合物,并且不含氧;和
采用CVD技术在所述单原子膜上沉积包含所述金属的氧化物的金属氧化膜。
2.根据权利要求1所述的方法,还包括:在所述单原子膜沉积步骤之前向所述底膜表面供给氧化性气体的步骤。
3.根据权利要求2所述的方法,其中所述氧化性气体包括加热后的H2O。
4.根据权利要求2所述的方法,其中所述氧化性气体包括从包含O2、活性氧、臭氧和N2O的组中选取的至少一种气体。
5.根据权利要求1所述的方法,还包括:在所述单原子膜沉积步骤之前向所述底膜表面供给氢氟酸的步骤。
6.根据权利要求1所述的方法,其中所述金属源包括从包含TaCl5、TaF5以及Ta(N(C2H5)2)3的组中选取的至少一种所述化合物,且所述金属氧化膜为氧化钽。
7.根据权利要求1所述的方法,其中所述金属源包括Al(CH3)3,且所述金属氧化物为氧化铝。
8.根据权利要求1所述的方法,其中所述金属源包括TiCl4或者Ti(N(CH3)2)4,且所述金属氧化物为氧化钛。
9.根据权利要求1所述的方法,其中所述金属源包括从包含Hf(N(CH3)2)4、Hf(N(C2H5)(CH3))4以及Hf(N(C2H5)2)4的组中选取的至少一种化合物,且所述金属氧化物为氧化铪。
10.根据权利要求1所述的方法,其中所述金属源包括从包含NbCl5、NbF5以及Nb(N(C2H5)2)3的组中选取的至少一种化合物,且所述金属氧化物为氧化铌。
11.根据权利要求1所述的方法,还包括:在所述单原子膜沉积步骤与所述金属氧化膜沉积步骤之间,向所述单原子膜表面供给氧化性气体的步骤。
12.根据权利要求1所述的方法,其中所述底膜为硅衬底、多晶硅膜、氮化硅膜或金属膜。
13.根据权利要求1所述的方法,还包括在所述金属氧化膜上形成导电膜的步骤,其中所述步骤用于形成电容,该电容包括:所述底膜作为下部电极、所述金属氧化膜作为电容绝缘膜、以及所述导电膜作为上部电极。
CNB2004100313924A 2003-03-27 2004-03-26 金属氧化膜的形成方法 Expired - Fee Related CN100364067C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP087577/2003 2003-03-27
JP2003087577A JP4009550B2 (ja) 2003-03-27 2003-03-27 金属酸化膜の形成方法

Publications (2)

Publication Number Publication Date
CN1534741A true CN1534741A (zh) 2004-10-06
CN100364067C CN100364067C (zh) 2008-01-23

Family

ID=32985166

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100313924A Expired - Fee Related CN100364067C (zh) 2003-03-27 2004-03-26 金属氧化膜的形成方法

Country Status (5)

Country Link
US (2) US7256144B2 (zh)
JP (1) JP4009550B2 (zh)
CN (1) CN100364067C (zh)
DE (1) DE102004016162A1 (zh)
TW (1) TWI242812B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113169069A (zh) * 2019-01-11 2021-07-23 株式会社国际电气 半导体器件的制造方法、衬底处理装置及程序

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7494927B2 (en) 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
US6551893B1 (en) * 2001-11-27 2003-04-22 Micron Technology, Inc. Atomic layer deposition of capacitor dielectric
US7476618B2 (en) * 2004-10-26 2009-01-13 Asm Japan K.K. Selective formation of metal layers in an integrated circuit
US7666773B2 (en) 2005-03-15 2010-02-23 Asm International N.V. Selective deposition of noble metal thin films
US8025922B2 (en) 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US20080171436A1 (en) * 2007-01-11 2008-07-17 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film
KR101544198B1 (ko) 2007-10-17 2015-08-12 한국에이에스엠지니텍 주식회사 루테늄 막 형성 방법
US7655564B2 (en) 2007-12-12 2010-02-02 Asm Japan, K.K. Method for forming Ta-Ru liner layer for Cu wiring
US7799674B2 (en) 2008-02-19 2010-09-21 Asm Japan K.K. Ruthenium alloy film for copper interconnects
US8084104B2 (en) 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
US8133555B2 (en) 2008-10-14 2012-03-13 Asm Japan K.K. Method for forming metal film by ALD using beta-diketone metal complex
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
JP2010183069A (ja) * 2009-01-07 2010-08-19 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置
US8329569B2 (en) 2009-07-31 2012-12-11 Asm America, Inc. Deposition of ruthenium or ruthenium dioxide
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
JP5882075B2 (ja) 2012-02-06 2016-03-09 東京エレクトロン株式会社 キャパシタの製造方法、キャパシタ、およびそれに用いられる誘電体膜の形成方法
WO2015140933A1 (ja) * 2014-03-18 2015-09-24 株式会社日立国際電気 半導体装置の製造方法、基板処理装置及び記録媒体
JP6361327B2 (ja) 2014-07-02 2018-07-25 セイコーエプソン株式会社 電気光学装置、及び電子機器
JP6347544B2 (ja) * 2014-07-09 2018-06-27 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
KR102064316B1 (ko) 2016-12-29 2020-01-09 주식회사 엘지화학 부타디엔 제조방법

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI118158B (sv) * 1999-10-15 2007-07-31 Asm Int Förfarande för modifiering av utgångsämneskemikalierna i en ALD-prosess
US6342277B1 (en) * 1996-08-16 2002-01-29 Licensee For Microelectronics: Asm America, Inc. Sequential chemical vapor deposition
US6270568B1 (en) * 1999-07-15 2001-08-07 Motorola, Inc. Method for fabricating a semiconductor structure with reduced leakage current density
KR100497142B1 (ko) * 1999-11-09 2005-06-29 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
US6780704B1 (en) * 1999-12-03 2004-08-24 Asm International Nv Conformal thin films over textured capacitor electrodes
KR100705926B1 (ko) * 1999-12-22 2007-04-11 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
EP1266054B1 (en) * 2000-03-07 2006-12-20 Asm International N.V. Graded thin films
US6592942B1 (en) * 2000-07-07 2003-07-15 Asm International N.V. Method for vapour deposition of a film onto a substrate
US6458416B1 (en) * 2000-07-19 2002-10-01 Micron Technology, Inc. Deposition methods
JP4727085B2 (ja) * 2000-08-11 2011-07-20 東京エレクトロン株式会社 基板処理装置および処理方法
KR100814980B1 (ko) * 2000-09-28 2008-03-18 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 산화물, 규산염 및 인산염의 증기를 이용한 석출
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
EP1205574A2 (en) * 2000-11-13 2002-05-15 Applied Materials, Inc. Atomic layer deposition of Ta205 and high-K dielectrics
US6355561B1 (en) * 2000-11-21 2002-03-12 Micron Technology, Inc. ALD method to improve surface coverage
JP2002222934A (ja) * 2001-01-29 2002-08-09 Nec Corp 半導体装置およびその製造方法
US6908639B2 (en) * 2001-04-02 2005-06-21 Micron Technology, Inc. Mixed composition interface layer and method of forming
US20030064153A1 (en) * 2001-10-01 2003-04-03 Rajendra Solanki Method of depositing a metallic film on a substrate
US7220312B2 (en) * 2002-03-13 2007-05-22 Micron Technology, Inc. Methods for treating semiconductor substrates
US7589029B2 (en) * 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US6858547B2 (en) * 2002-06-14 2005-02-22 Applied Materials, Inc. System and method for forming a gate dielectric
TW200408015A (en) * 2002-08-18 2004-05-16 Asml Us Inc Atomic layer deposition of high K metal silicates
US7553686B2 (en) * 2002-12-17 2009-06-30 The Regents Of The University Of Colorado, A Body Corporate Al2O3 atomic layer deposition to enhance the deposition of hydrophobic or hydrophilic coatings on micro-electromechanical devices
US6930060B2 (en) * 2003-06-18 2005-08-16 International Business Machines Corporation Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric
US7168800B2 (en) * 2003-07-17 2007-01-30 Brother Kogyo Kabushiki Kaisha Inkjet recording apparatus and ink cartridge

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113169069A (zh) * 2019-01-11 2021-07-23 株式会社国际电气 半导体器件的制造方法、衬底处理装置及程序
TWI764068B (zh) * 2019-01-11 2022-05-11 日商國際電氣股份有限公司 半導體裝置之製造方法、基板處理方法、基板處理裝置及程式
CN113169069B (zh) * 2019-01-11 2024-03-22 株式会社国际电气 半导体器件的制造方法、衬底处理方法、衬底处理装置及记录介质

Also Published As

Publication number Publication date
JP4009550B2 (ja) 2007-11-14
JP2004296814A (ja) 2004-10-21
US20040192036A1 (en) 2004-09-30
TW200425344A (en) 2004-11-16
US7741173B2 (en) 2010-06-22
TWI242812B (en) 2005-11-01
CN100364067C (zh) 2008-01-23
US20070205452A1 (en) 2007-09-06
US7256144B2 (en) 2007-08-14
DE102004016162A1 (de) 2004-11-11

Similar Documents

Publication Publication Date Title
CN100364067C (zh) 金属氧化膜的形成方法
US6420230B1 (en) Capacitor fabrication methods and capacitor constructions
KR100705926B1 (ko) 반도체 소자의 캐패시터 제조방법
US7446053B2 (en) Capacitor with nano-composite dielectric layer and method for fabricating the same
US7825043B2 (en) Method for fabricating capacitor in semiconductor device
US7735206B2 (en) Method for forming a capacitor dielectric and method for manufacturing capacitor using the capacitor dielectric
US20020024080A1 (en) Capacitor fabrication methods and capacitor constructions
US20020094632A1 (en) Capacitor fabrication methods and capacitor constructions
KR20010063450A (ko) 반도체 소자의 캐패시터 제조방법
US20080050884A1 (en) Process for manufacturing semiconductor device
CN1469439A (zh) 介电层的沉积方法
US20040166628A1 (en) Methods and apparatus for forming dielectric structures in integrated circuits
JP2003100908A (ja) 高誘電膜を備えた半導体素子及びその製造方法
CN1531032A (zh) 高介电常数氧化物膜的制造法、含该膜的电容器及制造法
KR20030043380A (ko) 반도체 소자의 캐패시터 제조방법
US7838438B2 (en) Dielectric layer, method of manufacturing the dielectric layer and method of manufacturing capacitor using the same
US20040087081A1 (en) Capacitor fabrication methods and capacitor structures including niobium oxide
CN1163965C (zh) 半导体存储器件的电容器及其制造方法
CN1280392A (zh) 半导体存储元件的电容器及其制造方法
KR20030051224A (ko) 고유전율 게이트 산화막상의 강유전체 박막의mocvd용 시드층 프로세스
JP2001203339A (ja) 半導体素子のキャパシタ製造方法
KR100716642B1 (ko) 캐패시터의 유전막 및 그의 제조방법
KR20070106289A (ko) 이트륨티타늄산화막을 구비한 반도체소자의 캐패시터 및 그제조 방법
KR20050067577A (ko) 혼합유전막의 제조 방법
KR100382370B1 (ko) 어닐링장치의 서셉터 전처리방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: PS4 LASCO CO., LTD.

Free format text: FORMER OWNER: NIHITATSU MEMORY CO., LTD.

Effective date: 20130828

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20130828

Address after: Luxemburg Luxemburg

Patentee after: ELPIDA MEMORY INC.

Address before: Tokyo, Japan

Patentee before: Nihitatsu Memory Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080123

Termination date: 20150326

EXPY Termination of patent right or utility model