CN1507056A - 半导体器件结构及其制造方法 - Google Patents

半导体器件结构及其制造方法 Download PDF

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CN1507056A
CN1507056A CNA03154035XA CN03154035A CN1507056A CN 1507056 A CN1507056 A CN 1507056A CN A03154035X A CNA03154035X A CN A03154035XA CN 03154035 A CN03154035 A CN 03154035A CN 1507056 A CN1507056 A CN 1507056A
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布鲁斯・B・多里斯
布鲁斯·B·多里斯
・B・查克拉瓦蒂
阿什马·B·查克拉瓦蒂
K・钱
凯文·K·钱
・A・尤里阿特
丹尼尔·A·尤里阿特
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GlobalFoundries Inc
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Abstract

一种半导体器件结构，包括衬底、淀积在衬底上的介质层、淀积在介质层上的第一和第二叠层。第一叠层包括淀积在介质层上的第一硅层、淀积在第一硅层上的锗化硅层、淀积在锗化硅层上的第二硅层以及淀积在第二硅层上的第三硅层。第二叠层包括淀积在介质层上的第一硅层以及淀积在第一硅层上的第二硅层。可供选择地，锗化硅层包括硼。

Description

半导体器件结构及其制造方法
技术领域
本发明涉及CMOS器件，并且更具体地说，涉及形成在同一衬底上的高性能NFET和PFET器件。
背景技术
高性能逻辑电路中的性能增益取决于增加开态电流而不减少关态电流。由于器件尺寸被改变比例时，更难取得性能增益。缩放比例的一个具体方面包括降低栅极氧化物的物理厚度。对于给定的栅极电压，穿过栅极氧化物建立电场。如果栅极氧化物减少，那么对于同一栅极电压，电场的大小增加。在PFET器件的情况下，负电压施加到栅极上用于接通器件。当器件处在接通状态时，沟道相对于它的多数载流子类型变为反相。随着在沟道中的负电荷增加，栅极变为耗尽其多数载流子。一般地这被称为栅极耗尽效应并作为栅极氧化物的有效增厚。这种效应对于薄膜栅极氧化物是特别显著的。从而，对于高性能器件，栅极耗尽是一个问题。
研究人员建议在栅极材料上使用SiGe以降低栅极耗尽效应。使用SiGe的主要好处是硼的固态溶解性在多晶SiGe中比在多晶Si中高。已经提出SiGe栅极叠层(stacks)的使用提高了PFET器件的性能。然而，用SiGe栅极叠层使NFET器件性能下降。例如，参看2001年8月23日公开的、由Marion等人申请的美国申请公开文件2001/0015922A1：“Semiconductor Devicewith an Integrated CMOS Circuit with MOS Transistors HavingSilicon-Germanium(Si1-xGex)Gate Electrodes，and Method of ManufacturingSame”，这里将其全文作参照引用。同样参看，由Sagnes申请的、于1999年12月7日公开的美国专利5,998,289：“Process for Obtaining a TransistorHaving a Silicon-Germanium Gate”，这里将其全文作参照引用。
本发明人认为进一步改进具有PFET器件的栅极材料SiGe的PFET和NFET器件结构是可行的。
发明内容
本发明的一个主要目的是提供具有改进PFET器件而不降低淀积在同一衬底上的NFET器件性能的半导体器件结构。
本发明的又一目的是提供上述半导体器件结构的制造方法。
本发明利用具有选择性多晶SiGe淀积工艺的新颖集成设计来解决NFET性能下降的问题。本发明通过提高PFET性能而不降低NFET性能实现了对于CMOS器件的性能改进。本发明针对在同一衬底上制造具有SiGe或Ge层的PFET器件并制造仅具有多晶硅的NFET器件的工艺。为了更进一步改进PFET性能，SiGe或Ge层可以用硼原位(in-situ)掺杂。本发明设计使用选择性生长工艺取得最终的器件结构。本发明还包括得到的半导体NFET和PFET器件结构。
根据本发明，一种半导体器件结构包括：
衬底；
淀积在衬底上的介质层；
淀积在介质层上的第一和第二叠层(stacks)；
第一叠层包括淀积在介质层上的第一硅层、淀积在第一硅层上的锗化硅层、淀积在锗化硅层上的第二硅层以及淀积在第二硅层上的第三硅层；
第二叠层包括淀积在介质层上的第一硅层以及淀积在第一硅层上的第二硅层。
当接下来的详细描述混合下面的附图进行时，本发明的更多的和另外的目的将变得更容易明白。
附图说明
图1-13是根据本发明的方法步骤以及所得到的中间和最终结构的侧面示意图。
具体实施方式
将在下文中描述本发明的优选方式，而不仅仅达到对于本领域的技术人员制作、使用和理解本发明的必要的程度。对于现有源极/漏极掺杂、各种杂质注入等的具体内容，下面不再详细地讨论，但是本领域技术人员将很容易地理解以形成完整功能的PFET和NFET器件。
现在参考附图，提供Si衬底1(图1)。
衬底1是绝缘体基外延硅晶片或是现有体型Si晶片或衬底。
使用现有隔离方法在晶片上构图有源区(未示出)并且使预计的PFET区同预计的NFET区隔离(点和虚线示意的)。隔离方法包括，例如，浅沟槽隔离(STI)、或硅LOCOS方法的局部隔离的任何变形，均为本领域所公知并能理解。
在形成隔离后，可实行本领域所公知的牺牲氧化工序，用于除去在先前工艺期间可能产生的任何污染或损害。
如果阱注入被用于调整阈值电压，那么牺牲氧化层(未示出)可用作掩蔽屏(screen)以防止在阱注入(未示出)期间产生沟槽。在使用阱注入的工艺集成流程中，现有光刻工艺被用于阻挡具有光刻胶的晶片的选择区域，使得没被光刻胶阻挡的区域被注入。用不同的掩模可重复该步骤，以便能制造需要不同阱注入的器件。
接下来用干或湿化学反应除去牺牲氧化层。例如，稀释的氢氟酸混合液被用于除去牺牲氧化层。
在除去牺牲氧化层后，具有大约0.8nm到大约8.0nm厚度的栅极介质层2按现有例如硅衬底的热氧化工艺形成在衬底1上。正如在高性能逻辑器件的技术领域中所常见的，典型地形成栅极氧化物2以便混合相当数量的氮，用于降低漏电流并增加栅极介质材料的介电常数。可以混合氮的公知的工艺技术包括，但不限于，继硅衬底热氧化之后的氮原子的离子注入以及SiO2的等离子氮化。从而，栅极介质层是热SiO2、氮化的SiO2或氧氮化物(oxynitride)。可选择地，栅极介质层是高K材料例如TaO5、HfO2，或者任何其它的栅极介质材料。
现在和下文参考图2-13，接下来非晶硅或多晶硅的薄层3淀积在整个晶片结构上方。该层具有厚度范围从大约1nm到大约8nm的大致均匀厚度(高度)T，并且通过多种现有技术的任何一种淀积，例如低压化学气相淀积(LPCVD)、等离子体增强化学气相淀积(PECVD)、快速加热化学气相淀积(RTCVD)。
接着，介质材料4淀积在整个晶片结构上方，介质材料4例如是SiN、SiO2、或SiON等。介质膜4具有厚度范围从大约5nm到大约70nm的大致均匀厚度并且通过本领域所公知的任何方法淀积。例如，膜4通过LPCVD、PECVD、RTCVD淀积。在一个实施例中，膜4是四乙氧基硅烷(TEOS)并且通过化学气相淀积方法淀积。
此后，现有光刻技术用于构图预定的NFET区。如图4所示，光刻胶掩模5用于保护预定的NFET区的介质膜4不被除去。
在本发明方法的这点上(图5)，公知的干法或湿法刻蚀工艺用于从预定的PFET区除去介质膜4。由于NFET区被光刻胶掩模5掩蔽住，因此这是可能的。如果层4是SiO2时，例如氢氟酸溶液用于除去介质膜4。干法蚀刻例如本领域公知的C4F8化学反应也可以用于选择性蚀刻SiO2层4。如果层4是SiN介质膜，那么包括丙三醇和氢氟酸或热磷酸蚀刻的湿法蚀刻用于膜除去步骤。可选择地，包括CHF3和CF4化学反应的干法、等离子蚀刻用于除去SiN膜4。
如图6所示，当除去介质膜4之后，用包括湿溶剂的工艺或公知的干O2等离子工艺除去光刻胶掩模5。
在本发明的方法中，接下来的步骤(图7)是选择性锗化硅(SiGe)生长。选择性锗化硅生长是现有的并且使用超高真空性能的快速热化学气相淀积反应器(未示出)或低压化学气相淀积反应器进行。首先，在超高真空环境下完成预清洁处理以从生长的表面除去污染物。这种处理可包括在850℃下高温退火约三分钟。可选择地，将晶片引入到超高真空反应室之前，进行湿出位(ex-situ)预清洁。湿预清洁包括，例如，稀释氢氟酸蘸浸以除去生长表面的污染物。美国专利No.5,242,847中和/或由Zhong等人发表的名称为“Selective Low-pressure Chemical Vapor Deposition of Si1-xGex Alloysin a Rapid Thermal Processor Using Dichlorosilane and Germane”(AppliedPhysics Letters，Vol.57，No.20，1990年11月12日，第2092-2094页)中描述了选择性锗化硅生长工艺，这里引入两者的公开内容作为参考。正如这些参考文件所描述地，在工艺压强为2.5Torr、温度范围为500-800℃、使用从0.025到1.00的GeH4∶SiH2Cl2比率范围的氢气载体气体中的GeH4和SiH2Cl2气体用于在相对于SiO2的多晶硅上选择性淀积锗化硅。如美国专利No.5,242,847和/或由Sanganeria等人发表的题目为“In-situ Boron DopedPolysilicon SiXGe1-X”(发表在电子材料期刊上，第21卷，No.1，第61-64页，1994年)中所描述的，可将硼混合到选择性SiGe薄膜中，这里将两者引入作为参考。正如这些参考文件所描述的，GeH4和B2H6可预先分别地与氢气混和到稀释物7.8％和40ppm，和具有10-12.5sccm范围内的流速的SiH2Cl2气体和5sccm流速的GeH4，以产生具有30％锗浓度和每立方厘米1020-1021硼原子的硼浓度的膜。膜6的厚度是基本上均匀的并且在大约o.2到大约50nm的范围内。
在本发明方法中，可选择步骤可以用于在选择性SiGe层6的顶部选择性生长本征硅层7。例如，在Si1-XGeX中的X接近于零的情况下，使用如前面所描述地同一工艺条件来生长层7。HCl气体也可引入到CVD反应器中，用于提高相对于覆盖NFET区的介质膜的硅生长的选择性。气体混合物SiH2Cl2∶HCl的优选比率是3.5∶1到4.75∶1以取得良好的选择性。如图8所示，层7的厚度是基本上均匀的并且在大约o.2到大约50nm的范围内。
接着，从预定的NFET区除去介质膜4。例如，如果层4是SiO2时，氢氟酸溶液用于除去介质膜4。本领域公知的由C4F8化学反应构成的干法蚀刻也可以用于选择性蚀刻SiO2层。如果层4是SiN介质膜，那么包括丙三醇和氢氟酸或热磷酸蚀刻的湿法蚀刻可用于除去膜4的工序。如图9所示，可选择地，包括CHF3和CF4化学反应的干法、等离子蚀刻可用于除去SiN膜4。
在发明工艺中的这个步骤，使用现有方法在整个晶片结构的上方淀积具有20nm到200nm范围内的基本上均匀的厚度的非晶硅或多晶硅膜8。用低压CVD、RTCVD、PECVD或任何其它合适的淀积技术淀积膜8。在某些情况下，在淀积膜8之前，可使用干原位(in-situ)清洁或湿出位(ex-situ)清洁。如图10所示。
因为取决于层3和层6的膜厚度的选择，可能存在某些不期望的形貌(未示出)，在接下来使用的光刻步骤之前，可以使用化学机械抛光(CMP)工艺以消除该形貌。
现在使用现有工艺步骤系列(图12的框图A)，用于完成栅极电极的构图，从而产生如图11所示的半导体器件结构。首先一低温SiO2(未示出)被淀积用作硬掩模。可以用化学气相淀积技术淀积该膜。接着，在该结构上进行本领域所公知的深紫外线光刻工艺，首先施加抗反射涂层，然后施加感光光刻胶材料。此后，使用掩模曝光光刻胶后，光刻胶图像被显影。然后选择性使用该光刻胶图像以阻挡不被栅极叠层蚀刻的区域。在高晶片偏置的条件下使用非选择性等离子蚀刻可刻蚀抗反射涂层和硬掩模。在抗反射涂层和硬掩模蚀刻后，用O2灰化工艺或溶剂剥离除去光刻胶和抗反射涂层。接着，使用硬掩模(未示出)来定义栅极电极。具有溴化氢的干等离子蚀刻可以用来蚀刻对于硬掩模选择性的多晶Si和多晶SiGe区。通过使用氢氟酸化学反应的湿法刻蚀除去硬掩模。在工艺流程的这点上，如图11所示意的，出现用于预定的PFET区的栅极电极3、6、7、8和用于预定的NFET区的栅极电极3、8。PFET的层3、6、7的优选大致均匀厚度大约(±10)是2nm、5nm和7nm，而NFET的层3、8的优选大致均匀厚度大约是2nm和8nm。
现在进行最终的现有工艺步骤以完成包括PFET器件和NFET器件的器件结构(图13)，例如：栅极再氧化10，NFET扩展11和卤素注入12、间隔壁形成13、PFET扩展14和卤素注入15、源极-漏极间隔壁形成16、NFET源极-漏极注入17、PFET源极-漏极注入18、活化退火、硅化物19、阻挡氮化物淀积20、预-金属介质淀积21、用于源极-漏极22和栅极触点23的光刻、接触蚀刻、衬垫和金属淀积、随后的CMP与包括低K材料应用和蚀刻的现有线(BEOL)工艺的后端、以及衬垫和金属布线材料例如Cu的现有技术的淀积。上述提及的注入和扩展按照现有方法提供到衬底1中。在图13中也示出隔离9。
现在已经显示并描述了本发明的优选实施例，本领域技术人员很容易理解，在不脱离如所附权利要求书限定的精神和范围的情况下，可以做出各种变化和修改。

Claims (14)

1、一种半导体器件结构，包括：
衬底；
淀积在该衬底上的介质层；
淀积在该介质层上的第一和第二叠层；
该第一叠层包括淀积在该介质层上的第一硅层、淀积在该第一硅层上的锗化硅层、淀积在该锗化硅层上的第二硅层以及淀积在该第二硅层上的第三硅层；
该第二叠层包括淀积在该介质层上的第一硅层以及淀积在该第一硅层上的第二硅层。
2、根据权利要求1的结构，其中该第一叠层的第一硅层包括多晶硅，该第二叠层的第一硅层包括多晶硅。
3、根据权利要求1的结构，其中该第一叠层的第一硅层包括非晶硅，该第二叠层的第一硅层包括非晶硅。
4、根据权利要求1的结构，其中该衬底是绝缘体基外延硅衬底。
5、根据权利要求1的结构，其中该锗化硅层具有大约0.1％到大约100％范围内的锗浓度。
6、根据权利要求1的结构，其中该锗化硅层包括硼。
7、根据权利要求1的结构，其中该锗化硅层具有大约5nm的大致均匀厚度。
8、一种半导体器件结构，包括：
淀积在衬底上的NFET器件和PFET器件，该PFET器件包括第一栅极叠层，该NFET器件包括第二栅极叠层，其中该第一栅极叠层包括锗化硅层以及该第二栅极叠层主要由硅和介质层组成。
9、根据权利要求7的结构，其中该锗化硅层包括硼。
10、根据权利要求8的结构，其中该第一栅极叠层主要由硅和锗化硅层组成，以及其中该第二栅极叠层主要由硅层组成。
11、根据权利要求10的结构，其中该锗化硅层包括硼。
12、一种半导体器件的制造方法，包括：
提供第一衬底；
提供第一介质层到该衬底上；
提供第一多晶硅层到该第一介质层上；
提供第二介质层到该第一多晶硅层上；
提供一掩模覆盖该第二介质层的一个区域；
除去该第二介质层的另一区域；
除去该掩模；
提供锗化硅层到该第一多晶硅层的第一区域上；
提供硅层到该锗化硅层上；
除去该第二介质层；
提供第二多晶硅层到该硅层上和到该第一多晶硅层上，并且然后构图所得到的结构，用于在该第一介质层上形成邻近第二叠层的第一叠层，只有该第一叠层包括该锗化硅层的一部分。
13、根据权利要求12的方法，其中提供锗化硅层的所述步骤包括选择性地生长该锗化硅层。
14、根据权利要求12的方法，其中提供锗化硅层的所述步骤包括选择性地生长该锗化硅层并将硼混合到该锗化硅层中。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110858539A (zh) * 2018-08-24 2020-03-03 美光科技公司 包含第一及第二区的层压件的半导体结构及形成半导体结构的方法

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7223676B2 (en) * 2002-06-05 2007-05-29 Applied Materials, Inc. Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer
US20070042580A1 (en) * 2000-08-10 2007-02-22 Amir Al-Bayati Ion implanted insulator material with reduced dielectric constant
US7294563B2 (en) * 2000-08-10 2007-11-13 Applied Materials, Inc. Semiconductor on insulator vertical transistor fabrication and doping process
US6939434B2 (en) * 2000-08-11 2005-09-06 Applied Materials, Inc. Externally excited torroidal plasma source with magnetic control of ion distribution
US7166524B2 (en) * 2000-08-11 2007-01-23 Applied Materials, Inc. Method for ion implanting insulator material to reduce dielectric constant
US7479456B2 (en) * 2004-08-26 2009-01-20 Applied Materials, Inc. Gasless high voltage high contact force wafer contact-cooling electrostatic chuck
US7037813B2 (en) * 2000-08-11 2006-05-02 Applied Materials, Inc. Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage
US7303982B2 (en) * 2000-08-11 2007-12-04 Applied Materials, Inc. Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage
US7288491B2 (en) * 2000-08-11 2007-10-30 Applied Materials, Inc. Plasma immersion ion implantation process
US20050230047A1 (en) * 2000-08-11 2005-10-20 Applied Materials, Inc. Plasma immersion ion implantation apparatus
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US7465478B2 (en) * 2000-08-11 2008-12-16 Applied Materials, Inc. Plasma immersion ion implantation process
US7320734B2 (en) * 2000-08-11 2008-01-22 Applied Materials, Inc. Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage
US7094670B2 (en) * 2000-08-11 2006-08-22 Applied Materials, Inc. Plasma immersion ion implantation process
US20050211171A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Chemical vapor deposition plasma reactor having an ion shower grid
US7695590B2 (en) * 2004-03-26 2010-04-13 Applied Materials, Inc. Chemical vapor deposition plasma reactor having plural ion shower grids
KR100564629B1 (ko) * 2004-07-06 2006-03-28 삼성전자주식회사 이이피롬 소자 및 그 제조 방법
US8058156B2 (en) * 2004-07-20 2011-11-15 Applied Materials, Inc. Plasma immersion ion implantation reactor having multiple ion shower grids
US7767561B2 (en) * 2004-07-20 2010-08-03 Applied Materials, Inc. Plasma immersion ion implantation reactor having an ion shower grid
US7172947B2 (en) * 2004-08-31 2007-02-06 Micron Technology, Inc High dielectric constant transition metal oxide materials
US20060060920A1 (en) * 2004-09-17 2006-03-23 Applied Materials, Inc. Poly-silicon-germanium gate stack and method for forming the same
US7666464B2 (en) * 2004-10-23 2010-02-23 Applied Materials, Inc. RF measurement feedback control and diagnostics for a plasma immersion ion implantation reactor
US20060260545A1 (en) * 2005-05-17 2006-11-23 Kartik Ramaswamy Low temperature absorption layer deposition and high speed optical annealing system
US7312162B2 (en) * 2005-05-17 2007-12-25 Applied Materials, Inc. Low temperature plasma deposition process for carbon layer deposition
US7422775B2 (en) * 2005-05-17 2008-09-09 Applied Materials, Inc. Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing
US7312148B2 (en) * 2005-08-08 2007-12-25 Applied Materials, Inc. Copper barrier reflow process employing high speed optical annealing
US7323401B2 (en) * 2005-08-08 2008-01-29 Applied Materials, Inc. Semiconductor substrate process using a low temperature deposited carbon-containing hard mask
US7429532B2 (en) * 2005-08-08 2008-09-30 Applied Materials, Inc. Semiconductor substrate process using an optically writable carbon-containing mask
US7335611B2 (en) * 2005-08-08 2008-02-26 Applied Materials, Inc. Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer
US7612421B2 (en) * 2005-10-11 2009-11-03 Atmel Corporation Electronic device with dopant diffusion barrier and tunable work function and methods of making same
US20090087967A1 (en) * 2005-11-14 2009-04-02 Todd Michael A Precursors and processes for low temperature selective epitaxial growth
US7691698B2 (en) 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US20070235759A1 (en) * 2006-04-11 2007-10-11 International Business Machines Corporation CMOS process with Si gates for nFETs and SiGe gates for pFETs
CN101583736A (zh) * 2007-01-19 2009-11-18 应用材料股份有限公司 浸没式等离子体室
US7790541B2 (en) * 2007-12-04 2010-09-07 International Business Machines Corporation Method and structure for forming multiple self-aligned gate stacks for logic devices
US7892932B2 (en) 2008-03-25 2011-02-22 International Business Machines Corporation Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
KR101699414B1 (ko) 2015-10-15 2017-01-24 서울시립대학교 산학협력단 이온트랩 기반의 양자역학적 인공 시각 시스템 및 연산 방법
TWI695477B (zh) 2016-07-07 2020-06-01 聯華電子股份有限公司 半導體結構及其製作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242848A (en) * 1990-01-22 1993-09-07 Silicon Storage Technology, Inc. Self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device
US5162246A (en) * 1990-04-27 1992-11-10 North Carolina State University Selective germanium deposition on silicon and resulting structures
US5241193A (en) * 1992-05-19 1993-08-31 Motorola, Inc. Semiconductor device having a thin-film transistor and process
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
US5242847A (en) * 1992-07-27 1993-09-07 North Carolina State University At Raleigh Selective deposition of doped silion-germanium alloy on semiconductor substrate
JP2740087B2 (ja) * 1992-08-15 1998-04-15 株式会社東芝 半導体集積回路装置の製造方法
FR2765394B1 (fr) * 1997-06-25 1999-09-24 France Telecom Procede d'obtention d'un transistor a grille en silicium-germanium
US5952701A (en) * 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US6200866B1 (en) * 1998-02-23 2001-03-13 Sharp Laboratories Of America, Inc. Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET
US6180499B1 (en) * 1998-09-29 2001-01-30 Advanced Micro Devices, Inc. Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby
US6274913B1 (en) * 1998-10-05 2001-08-14 Intel Corporation Shielded channel transistor structure with embedded source/drain junctions
US6451644B1 (en) * 1998-11-06 2002-09-17 Advanced Micro Devices, Inc. Method of providing a gate conductor with high dopant activation
US6252283B1 (en) * 1999-01-22 2001-06-26 Advanced Micro Devices, Inc. CMOS transistor design for shared N+/P+ electrode with enhanced device performance
US6281559B1 (en) * 1999-03-03 2001-08-28 Advanced Micro Devices, Inc. Gate stack structure for variable threshold voltage
US6133084A (en) * 1999-05-25 2000-10-17 United Microelectronics Corp. Method of fabricating static random access memory
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
KR20010110769A (ko) 2000-02-17 2001-12-13 롤페스 요하네스 게라투스 알베르투스 반도체 디바이스 및 그 제조 방법
JP4056195B2 (ja) 2000-03-30 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110858539A (zh) * 2018-08-24 2020-03-03 美光科技公司 包含第一及第二区的层压件的半导体结构及形成半导体结构的方法

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