CN1488167A - 用于集成电路平面化的粘性保护覆盖层 - Google Patents

用于集成电路平面化的粘性保护覆盖层 Download PDF

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CN1488167A
CN1488167A CNA028040171A CN02804017A CN1488167A CN 1488167 A CN1488167 A CN 1488167A CN A028040171 A CNA028040171 A CN A028040171A CN 02804017 A CN02804017 A CN 02804017A CN 1488167 A CN1488167 A CN 1488167A
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S���¿˺ռ�
S·穆克赫吉
D·德贝尔
J·莱维尔特
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Honeywell International Inc
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Abstract

本发明涉及在制造集成电路中典型遇到的表面平面化，特别是在镶嵌和双镶嵌互连中遇到的铜导体和Ta/TaN阻挡层的表面平面化。本发明描述了用于Cu/Ta/TaN互连的平面化方法，典型利用趋向位于较低表面形貌的区域中的粘性覆盖层，保护所述较低区域免受化学和机械作用组合的腐蚀。在一些实施例中，粘性覆盖层包含阻止从与粘性层接触的表面区域中去除铜的物质。这些物质可用是在其它添加剂中铜离子基本饱和的溶液，由此阻止了互连铜溶解进入保护覆盖层中。在本发明的一些实施例中，粘性覆盖层可以在腐蚀剂引入晶片表面之前添加，或者腐蚀剂和粘性覆盖层可以基本上同时典型地是在平面化过程中随晶片旋转引入。

Description

用于集成电路平面化的粘性保护覆盖层
技术领域
本发明涉及在制作集成电路期间的表面平面化并涉及阻止凹陷的表面区域腐蚀的粘性保护覆盖层。更具体的，本发明涉及铜表面和钽/氮化钽阻挡层的平面化，并涉及助于平面化和减少碟形化(dishing)的粘性覆盖层的使用，碟形化通常在大的铜镶嵌和双镶嵌特征的平面化中发生。
背景技术
增加集成电路(“IC”)的性能通常要求增加晶片上的元件密度和提高该IC执行其功能的速度。增加元件密度通常需要减少晶片上的导电槽和通孔(互连)的尺寸。然而，减少电流运输导体的横截面积会增加同一导电材料的电阻，使得电路特性变坏以及增加互连的放热。目前的IC技术通常使用钨(W)和铝(Al)互连和/或包含这些材料的合金。在Al和W这两者金属和它们的典型合金有足够应用在目前的器件中的电导率，但是下几代的IC优选使用更高电导率的材料。铜(Cu)属于首选的材料。
尽管Cu和当前的IC互连材料相比具有更高电导率的优点，但它也有几个不利因素。Cu是非常容易扩散的污染物质，容易且广泛扩散穿过通常在IC制造中使用的其它材料，这样做会严重损害IC的性能。钽(Ta)和氮化钽(TaN)已经被确定作为可以在Cu淀积之前淀积的有前途的阻挡材料或“衬垫(liner)”，由此阻止Cu扩散进入周围的材料。Shyam P.Murarka，Igor V.Verner和Ronald J.Gutmann在Copper-Fundamental Mechanisms for MicroelectronicApplications，(John Wiley，2000)给出了对铜IC互连和其它微电子技术的最新评论。
平面化在多层IC的制造中是必需的步骤，提供一个能够用现代IC元件所要求的精确度被构图和腐蚀的平坦、光滑表面。常规平面化技术是本领域里已知的CMP(化学机械平面化)，并在教科书(例如，Chemical Mechanical planarization of MicroelectronicMaterials，Joseph M.Steigerwald，Shyam P.Murarka和RonaldJ.Gutman，1997)中有所描述。CMP利用与晶片机械接触的抛光垫，借助在抛光垫和晶片之间插入的研磨料浆对晶片平面化。抛光垫相对于晶片的相对移动(典型的是旋转)导致了经过机械研磨和化学腐蚀的晶片抛光，化学腐蚀是由在腐蚀溶液中的适宜的反应化学物质引起的。同样已经提出了非接触平面化，其中在晶片上不会发生有效的机械研磨，通过化学效应进行平面化。一种这样的非接触平面化技术利用旋转晶片和适宜的腐蚀化学物质(“旋转-腐蚀平面化”)，并且在申请09/356,487中得到描述(在这里作为参考引入)。有关非接触平面化的一些特点已经在下面的文章中报道：J.Levert，S.Mukherjee和D.DeBear＂Spin-Etch Planarization Process for CopperDamascene Interconnects＂in Proceedings of SEMI TechnologySymposium 99，Dec.1-3，1999，pp.4-73 to 4-82。也可见J.Levert，S.Mukher jee，D.DeBear和M.Fury＂A Novel Spin-EtchPlanarization Process for Dual-Damascene CopperInterconnects＂在Electrochemical Society Conference，1999年10月，p.162ff。以及参阅Shyama P.Mukherjee，Joseph A.Levert和Donald S.DeBear，＂Planarization of CopperDamascene Interconnects by Spin-Etch Process：A ChemicalApproach，＂MRS Spring Meeting，San Francisco，California，2000年四月27，其包括了前面引用的所有参考。
其它的铜平面化工艺包括Moslehi(WO99/14800)和Cantolini及合作者  描述的电化学或电抛光技术(J.Electrochem.Soc.Vol.141，No.9，pp.2503-2510，1994年九月和WO 92/07118)。
本发明涉及用于在制造IC过程中平面化Cu/Ta/TaN层的改进方法。本领域的普通技术人员都明白，本发明可以结合旋转腐蚀平面化、常规CMP或其它平面化技术使用。
发明内容
本发明涉及在集成电路制造中通常遇到的表面平面化，特别是，在镶嵌和双镶嵌互连中遇到的铜导体和Ta/TaN阻挡层表面的平面化。为了能在我们的讨论中详细说明，我们考虑了大电流的技术意义的铜表面和Ta/TaN阻挡层平面化的例子。这里公开的本发明申请对于其它系统的平面化对本领域的普通技术人员来讲是很清楚的。
在淀积铜层后，通过平面化工艺去除铜层上表面中的表面形貌(surface topography)，产生与周围的电介质共面的基本平面的导体。“碟形化(Dishing)”是指在位于电介质表面的平面下面的铜互连中形成凹形区域的趋势。在大量的互连平面化中最常提及的问题是碟形化。
本发明描述了用于Cu/Ta/TaN互连的平面化方法，通常利用趋向留在较低表面形貌的区域中的粘性覆盖层，保护所述较低区域免受化学和机械作用组合的腐蚀。同时，表面形貌中高出的较少被保护的区域优先被去除。在一些实施例中，粘性覆盖层包括阻止从接触粘性层的表面区域中去除铜的物质。这种物质可以是基本饱和的铜离子溶液，由此阻止互连铜分解进入保护的覆盖层中。在粘性覆盖层中也可以包括禁止或钝化铜表面免于溶解的其它物质，其中包括喹啉或苯并三唑等。在本发明的一些实施例中，粘性覆盖层可以在对晶片表面引入腐蚀剂之前添加，或者腐蚀剂和粘性覆盖层可以基本同时引入，典型的是在平面化期间晶片旋转时。一个实施例涉及在制造集成电路互连中的金属表面平面化的方法，包括在所述金属表面上引入保护液体和将所述保护液体横过金属表面分散，和在所述金属表面上引入腐蚀溶液，在此所述保护液体的粘度超过所述腐蚀溶液的粘度，从而阻止腐蚀由所述保护层占据的所述表面区域中的所述表面和腐蚀所述金属表面至平坦。
附图说明
这里的附图是示意性的，没有按比例画出。
图1：在平面化之前的典型镶嵌和双镶嵌互连的示意性的剖面图。
图2：在理想的平面化工艺之后的典型镶嵌和双镶嵌互连的示意性的剖面图。
图3：典型镶嵌和双镶嵌互连的示意性的剖面图：(A)在平面化之前，(B)对于理想的平面化工艺在去除场铜并且露出场阻挡层之后，(C)对于理想平面化工艺在完全平面化之后，(D)在常规(非理想)平面化工艺后的完全平面化之后。
图4：在平面化之前，具有包括涂敷粘性覆盖层的表面形貌的典型镶嵌和双镶嵌互连的示意性的剖面图，(A)完全覆盖，(B)部分覆盖。
图5：在平面化之前，具有包括完全覆盖表面的粘性覆盖层的表面形貌的典型镶嵌和双镶嵌互连的示意性的剖面图。
具体实施方式
在下面的描述和附图中，相同的标号用于标示相同的元件。这里的附图是示意性的，没有按比例画出。
镶嵌和双镶嵌工艺的多种变化在本领域中是公知的。例如，见Copper-Fundamental Mechanisms for MicroelectronicApplications(supra)，pp.265-311和其中引用的文献，(这里作为参考文献引入)。这里表达的镶嵌和双镶嵌的例子仅是举例说明用的，目的并不是限制本发明的范围或应用。
图1是在平面化之前的典型镶嵌金属互连结构(“互连”)的剖面图。通常通过光刻法、等离子体刻蚀以及其它技术对绝缘电介质层1(通常称为“层间电介质”或ILD)进行构图。通常在图形化的电介质上淀积阻挡层2，之后淀积导体3。典型的阻挡层通常是钽/氮化钽2(“Ta/TaN”)，用来和铜导体3一起使用。为了在我们的讨论中更加具体，我们描述了关于具有Ta/TaN阻挡层的铜互连的平面化的特殊例子，但目的并不是要限制本发明的范围。对其它系统的修改或扩展对本领域的普通技术人员是显而易见的并包括在其范围中。
实践中，淀积金属层3的典型方法(电淀积(electrodeposition)，CVD，PVD等)不能精确填充特征到边缘或者形成与电介质共面的导体表面。因此，在图1中示出了通用方法，其中导体3填充了互连特征，例如通孔和槽5，并且在通向在整个电介质表面上的金属层的特征之间涂覆平的“场”区4。典型的，涂覆工艺产生铜层的非平面表面形貌，这是因为在下面的被涂覆的ILD特征的尺寸变化。表面结构如8，9和10所示。随后的处理使得铜材料和阻挡层被去除，以便形成与电介质1的表面理想共面的互连表面，适于在其它处理步骤中进一步淀积材料和图形化。图2示出了平面化的理想结果，其中所有铜和阻挡层材料从场区4中去除，并且铜导体3的上表面是平的且与ILD1的上表面齐平。
图3是在图形化、淀积阻挡层和在特征内和场区上淀积金属层之后的典型双镶嵌特征。通孔6、槽7被阻挡层2覆盖，并且用铜3填充，典型产生了反映下面的槽和通孔结构的表面形貌20。
在镶嵌或双镶嵌互连的平面化过程中的第一步骤是去除在场和特征区上的金属，暴露场区内的阻挡层。理想的，场金属以平面方式被去除，直至该特征中的金属上表面与周围的场共面。图3B说明的一个实施例示出了实现场金属去除直到与场阻挡层2共面。一些金属去除过程是以与阻挡层不同的方式去除金属的，导致在图3B所示的场区上露出的阻挡层。一些金属去除过程是使用阻挡层作为“腐蚀停止”，其指示铜场平面化步骤的终点。典型的，不去除阻挡层(或以低于铜层的去除速率许多的速率去除阻挡层)的铜去除工艺在阻挡层被暴露时将会有效终止在场区上。然而，当阻挡层被暴露时，除非快速去除腐蚀剂，否则腐蚀将会在铜特征中继续下去，导致在特征内的铜的上表面内产生凹形结构(“碟形化”)。减少或避免碟形化是本发明的目的之一。
图3B示出，在露出阻挡层之后，通过与去除足够的金属一同进行的随后的平面化以保持填充金属的特征和电介质共面，典型去除阻挡层，如图3C所示。如果平面化过程在去除阻挡材料和铜中基本获得1∶1的选择比，则从图3A至3C的直接平面化可以在一个步骤中完成。
通过产生类似图1，2，3B和3C所示结构的过程来建立镶嵌和双镶嵌互连，是在实践中很少能实现的理想化。铜镶嵌和双镶嵌互连的实际平面化涉及了几方面的挑战，其中本发明首要关心的两个方面是表面形貌和碟形化。
表面形貌
图1是可能在图形化的电介质(典型具有插入在铜3和电介质1之间的阻挡层2)上淀积铜时出现的一种缺陷类型的示意性(并没有按比例)的剖面图。铜可趋于近似共形电镀或淀积，趋于在铜层的表面内再现位于下面的形貌的较大特征。因此，较大特征的凹陷特性，典型的槽，在铜表面中可显示为凹陷的表面形貌9和10。然而，包括通孔的更小特征可以示为一些表面形貌8。铜表面的这种不均匀结构将在平面化处理中被去除，表明该平面化优选不是材料的共形去除。也就是说，铜的去除工艺必须优先从不均匀结构的高出区域中去除材料以便获得平面化。常规的CMP除了化学去除材料外还包括使用机械力。机械力在突出更靠近抛光垫的邻近处的表面高出部分上趋向于更大，导致在高出部分上以更高的速率去除材料。非接触化学腐蚀需要其它模式，借此优先去除高出的形貌特征，产生平面化。在旋转腐蚀平面化方面的最新研究利用扩散受控反应、平衡的氧化还原反应、自电镀微耦合(self-galvanic microcouple)和/或控制腐蚀的添加剂以便获得平面性，如在09/356,487中描述的那样，它在这里作为参考引入。因此，在获得铜互连的有效平面化中遇到的一个挑战就是在去除金属的同时有效地使表面形貌光滑。
碟形化
图3A是在平面化之前的包括槽和通孔的典型双镶嵌互连结构的剖面图。由类似共形的电镀得到的表面形貌8、9和10也可以在双镶嵌互连中出现。通过将焦点放在碟形化上，我们忽略该附加效应以便简化我们的描述。总的来说，碟形化和表面形貌都将会出现，在设计一个有效、实际的平面化工序时需要同时考虑这两者的效应。
完美的平面化去除铜直到特征7的上表面与在场区上的阻挡层的上表面共面。理想的平面化将以与铜层相同的速率去除阻挡层2，即，基本上1比1的选择比。因此，一步平面化可被用来在一单一的处理步骤中去除铜层和阻挡层。对于其中表面形貌不影响平面化以及一旦阻挡层被去除并且出现与ILD1共面就停止腐蚀的工艺，理想结果正如图3C所示。然而，实践中这个理想的状态并不能经常得到。图3A的互连的传统平面化可以去除在特征的内部区域的铜，产生一个类似碟形的几何形状，如图3D中的11所示。碟形化是去除场区铜4和场区上面的阻挡层2的普遍不希望的副作用。
然而，阻挡层典型是Ta/TaN，并且需要有相当大腐蚀性的腐蚀剂才能去除它。可以使用二步平面化处理，其中第一组腐蚀剂去除铜，其它的腐蚀剂去除阻挡层。如果将这样的腐蚀剂用于没有保护的Cu表面，则使用这样的腐蚀剂经常导致铜的去除速率更快。如11所示的碟形化是不期望的结果。应该注意，碟形化对于大的特征，超过约10微米的典型特征尺寸10，是更加严重的问题。现代的集成电路技术希望平面化的特征尺寸等于50微米或大于50微米，使得碟形化成为严重的实际问题。
如果平面化利用二步处理进行，去除铜之后去除阻挡材料，则需要考虑几个因素。在第一步骤中使用的化学物质应该能够有选择地化学抛光或去除铜。在这个例子中，进行平面化的整个表面上的铜去除的均匀性对于避免碟形化是很重要的。如果铜区域的一部分去除了铜(至阻挡层或与阻挡层共面)，而其它地方没有除掉，当从没有清除掉铜的区域去除残留的铜时，在去除铜的区域中将预期出现铜的碟形化。因此，碟形化有两个总的原因：1)在第一去除步骤中的铜去除的非均匀性；2)大特征的优先腐蚀或抛光速率高于小特征。
本发明提供了数个实施例用于铜镶嵌或双镶嵌互连的平面化，其减小或消除碟形化的问题。另外，本发明的数个实施例能够对具有从类似共形的电镀(图1)获得的表面形貌的铜表面平面化。不同的实施例在不同的处理环境中提供了不同的优点。
粘性保护覆盖层
非均匀金属表面(例如，图1)的平面化需要优先腐蚀表面高出的部分。本发明的一些实施例以优先饱和有钝化金属、铜或其它化学抑制性的化合物的粘性液体覆盖层的形式使用保护或钝化覆盖层。在这里使用的“保护液体”是指在表面上的覆盖层有助于保护或阻碍被这样覆盖的表面区的腐蚀。一个实施例说明了粘性液体，图4B中的示意性的13。粘性液体13淀积在表面上(通常通过旋转，在表面12上分散)，并趋向于聚集在凹陷的区域中，如图4B中的13所示，并且有基本平的上表面。趋于集中在较低表面区域中的粘性液体的存在阻碍了对有这样提供的覆盖层的表面部分的腐蚀，保护较低区域免受腐蚀剂的侵袭，同时借助将禁止层插入在非常接近金属表面之处(典型插入非氧化剂)阻碍了金属的去除。这种禁止层的一个实施例是饱和有钝化金属或铜离子、或是已知在存在腐蚀剂的情况下禁止铜去除的其它物质的粘性层。
总的来说，粘性液体将在该粘性液体和腐蚀试剂之间形成一个梯度而没有明显界限。然而，选择保护层有大于(或基本大于)腐蚀剂的粘度仍然将导致粘性液体优先集中在较低表面区域内，并且减缓金属去除的速率。粘性覆盖层的使用结合非接触平面化有效实施，非接触平面化可以是例如旋转腐蚀平面化，如专利申请09/356,487中所描述的，其中和粘性保护液体相比，晶片的旋转产生了更容易分散腐蚀剂的离心力。
在用于保护铜互连表面的本发明的一些实施例中，准备饱和有铜离子的粘性溶液，典型的是与包含磷酸的腐蚀剂一起使用的磷酸铜的形式。在本发明的实践中，一个常规选择将使用其中铜盐被溶解的磷酸溶液，典型的是磷酸铜、硝酸铜、醋酸铜或铜醇盐(copperalkoxide)等。这样的溶液可以有大约1.75的密度和缺少氧化剂。这种粘性溶液通常是旋转淀积在表面上并且优先减缓在较低表面区域中的腐蚀。具有磷酸铜(或适合其它腐蚀剂的其它铜盐)的覆盖层饱和度阻碍在平面化中铜从表面的进一步的溶解。
本发明的一些实施例通常在晶片旋转时，同时在晶片上引入保护液体和腐蚀剂。图5示意性所示的材料配置是最终结果。液体层14包含处于混合或分散状态的腐蚀剂和粘性液体。更粘的液体，典型更大密度将会因此趋向集中在液体层14的较低区域，和在凹陷的区域中。因此，同时引入腐蚀剂和保护液体导致保护液体优先集中在凹陷的表面区域中，在那里需要保护液体。
用于去除铜的典型腐蚀剂溶液如下面所示，其中％表示完全浓缩的试剂的体积％：
二元试剂：
I.  硝酸：1％-20％，优选3％-10％
    磷酸：余下的溶液
三元试剂
I.  硝酸：1％-20％，优选3％-10％
    硫酸：20％-50％
    磷酸：余下的溶液
II. 硝酸：10％
    醋酸：40％
    磷酸：50％
III.硝酸：6％
    醋酸：24％
    磷酸：70％在上述腐蚀剂混合物中，过氧化氢可以被用来全部或部分替代硝酸。
腐蚀之后，从晶片表面清洗残留的腐蚀试剂、保护液体、腐蚀的副产物，以准备淀积材料的附加层。腐蚀后清洗是本领域公知的，参考文献中的Steigerwald等人的supra pp.289-305中有所描述。
添加剂
在本发明的一些实施例中，铜的去除导致了阻挡层露出和覆盖层去除，产生如图3B所示的结构。此时，去除阻挡层2同时保持铜层的平面性即避免碟形化是必需的。阻挡层Ta/TaN的去除通常需要相当强的侵蚀性的化学腐蚀剂，例如氢氟酸，氟化铵，溴化铵等。这种侵蚀性的腐蚀剂可以腐蚀铜，或以快于阻挡层的速率腐蚀铜，产生碟形化。因此，和阻挡层相比，铜的选择性保护在本发明的这些实施例中是很有用的。
避免碟形化的一种途径是在腐蚀溶液中引入选择性的添加剂，其有选择地吸附在铜上。选择这种被吸附的物质以保护铜免受进一步地腐蚀，同时允许继续去除阻挡层。添加剂(典型的是有机化合物)吸附在高的表面能的位置处，它在电镀领域中是公知为“抑制物”或“抑制剂”趋于阻碍铜在吸附位置上淀积。对于阻止铜溶解起着相似的作用。这样的添加剂必须与腐蚀剂是相容的(即，在存在腐蚀剂时不被破坏或致使无效)。典型的添加剂包括磺酸型添加剂、乙二醇或能够与典型的腐蚀液(例如磷酸)相容的其它添加剂。
这里描述的平面化技术可以通过给铜并给电解质腐蚀剂溶液施加外部电压进行强化，由此对这里描述的化学和机械平面化效应添加了电化学效应。
这里描述的腐蚀过程产生了用于在制造IC中平面化Cu/Ta/TaN层的改进方法。提高了最终IC的性能和/或提高了工艺的生产量。
已经详细描述了本发明，本领域的技术人员都理解，给予的当前的公开内容，在不脱离这里描述的创造性原理的精神范围的情况下，可以对本发明进行修改。因此，本发明的范围不限于这里描述和举例的具体和优选实施例。

Claims (10)

1.一种在制造集成电路互连中平面化金属表面的方法，包括：
a)在所述金属表面上引入保护液体；和
b)横过所述金属表面分散所述保护液体；和
c)在所述金属表面上引入腐蚀溶液，在此所述保护液体的粘度超过所述腐蚀溶液的粘度，由此阻碍了在由所述保护层占据的所述表面区域内的所述表面的腐蚀；和
d)腐蚀所述金属表面至平坦。
2.根据权利要求1的方法，其中所述保护液体缺乏能够腐蚀所述金属表面的氧化剂。
3.根据权利要求2的方法，其中将所述保护液体引入到所述金属表面上的所述步骤是在足够量下以对所述金属表面的凹陷区域提供优先的保护。
4.根据权利要求3的方法，其中所述保护液体包含在其中溶解的包括所述金属表面的金属的离子的饱和量。
5.根据权利要求4的方法，其中所述金属是铜。
6.根据权利要求5的方法，其中所述保护液体是包含其中溶解饱和量铜离子的磷酸。
7.根据权利要求1的方法，其中所述保护液体和所述腐蚀溶液被基本上同时引入到所述金属表面上。
8.一种用于集成电路的前体，包括
a)绝缘电介质层；和
b)阻挡层；和
c)导体；和
d)保护液体；和
e)腐蚀液体，在此所述保护液体的粘度超过所述腐蚀液体的粘度。
9.根据权利要求8的前体，其中所述阻挡层是钽/氮化钽。
10.根据权利要求8的前体，其中所述导体是铜。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106971974A (zh) * 2016-01-14 2017-07-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN114752938A (zh) * 2022-04-07 2022-07-15 中国科学院赣江创新研究院 一种完整去除Nb3Sn超导线稳定层和阻挡层的方法
WO2023024869A1 (zh) * 2021-08-23 2023-03-02 上海芯物科技有限公司 一种半导体表面平坦化的方法及制得的半导体和用途

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610190B2 (en) * 2000-11-03 2003-08-26 Nutool, Inc. Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate
US6534116B2 (en) * 2000-08-10 2003-03-18 Nutool, Inc. Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
US6497800B1 (en) * 2000-03-17 2002-12-24 Nutool Inc. Device providing electrical contact to the surface of a semiconductor workpiece during metal plating
US6413388B1 (en) * 2000-02-23 2002-07-02 Nutool Inc. Pad designs and structures for a versatile materials processing apparatus
US6902659B2 (en) * 1998-12-01 2005-06-07 Asm Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6251235B1 (en) 1999-03-30 2001-06-26 Nutool, Inc. Apparatus for forming an electrical contact with a semiconductor substrate
US6940721B2 (en) * 2000-02-25 2005-09-06 Richard F. Hill Thermal interface structure for placement between a microelectronic component package and heat sink
US6852208B2 (en) 2000-03-17 2005-02-08 Nutool, Inc. Method and apparatus for full surface electrotreating of a wafer
US6921551B2 (en) 2000-08-10 2005-07-26 Asm Nutool, Inc. Plating method and apparatus for controlling deposition on predetermined portions of a workpiece
US7754061B2 (en) * 2000-08-10 2010-07-13 Novellus Systems, Inc. Method for controlling conductor deposition on predetermined portions of a wafer
US7153410B2 (en) * 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces
US7094131B2 (en) * 2000-08-30 2006-08-22 Micron Technology, Inc. Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material
US7129160B2 (en) 2002-08-29 2006-10-31 Micron Technology, Inc. Method for simultaneously removing multiple conductive materials from microelectronic substrates
US7078308B2 (en) 2002-08-29 2006-07-18 Micron Technology, Inc. Method and apparatus for removing adjacent conductive and nonconductive materials of a microelectronic substrate
US7112121B2 (en) * 2000-08-30 2006-09-26 Micron Technology, Inc. Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate
US7192335B2 (en) * 2002-08-29 2007-03-20 Micron Technology, Inc. Method and apparatus for chemically, mechanically, and/or electrolytically removing material from microelectronic substrates
US7134934B2 (en) * 2000-08-30 2006-11-14 Micron Technology, Inc. Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium
US7153195B2 (en) * 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for selectively removing conductive material from a microelectronic substrate
US7160176B2 (en) * 2000-08-30 2007-01-09 Micron Technology, Inc. Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate
US7220166B2 (en) * 2000-08-30 2007-05-22 Micron Technology, Inc. Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate
US20040170753A1 (en) * 2000-12-18 2004-09-02 Basol Bulent M. Electrochemical mechanical processing using low temperature process environment
US7172497B2 (en) * 2001-01-05 2007-02-06 Asm Nutool, Inc. Fabrication of semiconductor interconnect structures
US6783589B2 (en) * 2001-01-19 2004-08-31 Chevron U.S.A. Inc. Diamondoid-containing materials in microelectronics
US20040253809A1 (en) * 2001-08-18 2004-12-16 Yao Xiang Yu Forming a semiconductor structure using a combination of planarizing methods and electropolishing
AU2002365226A1 (en) * 2001-11-07 2003-09-02 Dow Global Technologies Inc. Planarized microelectronic substrates
US20040016962A1 (en) * 2002-04-30 2004-01-29 Hideki Okumura Semiconductor device
US6949389B2 (en) * 2002-05-02 2005-09-27 Osram Opto Semiconductors Gmbh Encapsulation for organic light emitting diodes devices
KR100559041B1 (ko) * 2002-07-11 2006-03-10 매그나칩 반도체 유한회사 반도체 소자의 구리 배선 형성 방법
KR100477365B1 (ko) * 2002-09-27 2005-03-22 주식회사 대우일렉트로닉스 원자힘 현미경의 팁 보호막 형성 방법
EP1562742A4 (en) * 2002-10-31 2008-08-06 Georgia Tech Res Inst MICROSTRUCTURES AND MANUFACTURING METHOD THEREFOR
US7140374B2 (en) * 2003-03-14 2006-11-28 Lam Research Corporation System, method and apparatus for self-cleaning dry etch
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US7009281B2 (en) * 2003-03-14 2006-03-07 Lam Corporation Small volume process chamber with hot inner surfaces
US7078344B2 (en) * 2003-03-14 2006-07-18 Lam Research Corporation Stress free etch processing in combination with a dynamic liquid meniscus
US7232766B2 (en) * 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US6821899B2 (en) * 2003-03-14 2004-11-23 Lam Research Corporation System, method and apparatus for improved local dual-damascene planarization
DK1620568T3 (da) * 2003-04-24 2009-03-30 Afshin Ahmadian Analyse til allelspecifik mutationspåvisning
US6777807B1 (en) * 2003-05-29 2004-08-17 Lsi Logic Corporation Interconnect integration
JP4499390B2 (ja) * 2003-09-09 2010-07-07 パナソニック株式会社 半導体装置及びその製造方法
US7112122B2 (en) * 2003-09-17 2006-09-26 Micron Technology, Inc. Methods and apparatus for removing conductive material from a microelectronic substrate
US6936534B2 (en) * 2003-09-17 2005-08-30 Micron Technology, Inc. Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization
US7064057B2 (en) * 2003-11-21 2006-06-20 Asm Nutool, Inc. Method and apparatus for localized material removal by electrochemical polishing
US7153777B2 (en) 2004-02-20 2006-12-26 Micron Technology, Inc. Methods and apparatuses for electrochemical-mechanical polishing
DE102004014676B4 (de) * 2004-03-25 2009-05-14 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltungsanordnung mit Hilfsvertiefung, insbesondere mit Ausrichtmarken, und integrierte Schaltungsanordnung
US7307013B2 (en) * 2004-06-30 2007-12-11 Sandisk 3D Llc Nonselective unpatterned etchback to expose buried patterned features
US7566391B2 (en) 2004-09-01 2009-07-28 Micron Technology, Inc. Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media
US20060183321A1 (en) * 2004-09-27 2006-08-17 Basol Bulent M Method for reduction of gap fill defects
KR100620712B1 (ko) * 2004-12-24 2006-09-13 동부일렉트로닉스 주식회사 디싱 현상을 회복하는 방법
US7538434B2 (en) * 2005-03-08 2009-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Copper interconnection with conductive polymer layer and method of forming the same
US7550070B2 (en) * 2006-02-03 2009-06-23 Novellus Systems, Inc. Electrode and pad assembly for processing conductive layers
EP1839695A1 (en) * 2006-03-31 2007-10-03 Debiotech S.A. Medical liquid injection device
KR100793916B1 (ko) * 2006-04-05 2008-01-15 삼성전기주식회사 인쇄회로기판 내장형 커패시터의 제조방법
US7585760B2 (en) * 2006-06-23 2009-09-08 Intel Corporation Method for forming planarizing copper in a low-k dielectric
US20070298607A1 (en) * 2006-06-23 2007-12-27 Andryushchenko Tatyana N Method for copper damascence fill for forming an interconnect
US8500985B2 (en) 2006-07-21 2013-08-06 Novellus Systems, Inc. Photoresist-free metal deposition
US7732329B2 (en) * 2006-08-30 2010-06-08 Ipgrip, Llc Method and apparatus for workpiece surface modification for selective material deposition
DE102007009902A1 (de) * 2007-02-28 2008-09-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Reduzieren von Ungleichmäßigkeiten während des chemisch-mechanischen Polierens von überschüssigem Metall in einer Metallisierungsebene von Mikrostrukturbauelementen
US9443763B2 (en) * 2013-09-12 2016-09-13 Micron Technology, Inc. Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process
US9343408B2 (en) * 2013-11-08 2016-05-17 Intermolecular, Inc. Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/H2SO4 solution
US10870799B2 (en) * 2017-08-25 2020-12-22 Versum Materials Us, Llc Etching solution for selectively removing tantalum nitride over titanium nitride during manufacture of a semiconductor device
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
JP2020088069A (ja) * 2018-11-20 2020-06-04 凸版印刷株式会社 半導体パッケージ基板およびその製造方法
US11508617B2 (en) 2019-10-24 2022-11-22 Applied Materials, Inc. Method of forming interconnect for semiconductor device
US11257677B2 (en) * 2020-01-24 2022-02-22 Applied Materials, Inc. Methods and devices for subtractive self-alignment

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01108746A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置の製造方法
EP0428383A1 (en) * 1989-11-13 1991-05-22 Shikoku Chemicals Corporation Process for surface treatment of copper and copper alloy
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US5486234A (en) * 1993-07-16 1996-01-23 The United States Of America As Represented By The United States Department Of Energy Removal of field and embedded metal by spin spray etching
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US5766379A (en) * 1995-06-07 1998-06-16 The Research Foundation Of State University Of New York Passivated copper conductive layers for microelectronic applications and methods of manufacturing same
US5744399A (en) * 1995-11-13 1998-04-28 Lsi Logic Corporation Process for forming low dielectric constant layers using fullerenes
US6387805B2 (en) * 1997-05-08 2002-05-14 Applied Materials, Inc. Copper alloy seed layer for copper metallization
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6351039B1 (en) * 1997-05-28 2002-02-26 Texas Instruments Incorporated Integrated circuit dielectric and method
US6280644B1 (en) * 1998-06-05 2001-08-28 Agere Systems Guardian Corp. Method of planarizing a surface on an integrated circuit
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
US6150269A (en) * 1998-09-11 2000-11-21 Chartered Semiconductor Manufacturing Company, Ltd. Copper interconnect patterning
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
US6159842A (en) * 1999-01-11 2000-12-12 Taiwan Semiconductor Manufacturing Company Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
TW400619B (en) * 1999-03-05 2000-08-01 United Microelectronics Corp The manufacture method of dual damascene structure
US6083822A (en) * 1999-08-12 2000-07-04 Industrial Technology Research Institute Fabrication process for copper structures
US6080656A (en) * 1999-09-01 2000-06-27 Taiwan Semiconductor Manufacturing Company Method for forming a self-aligned copper structure with improved planarity
US6146991A (en) 1999-09-03 2000-11-14 Taiwan Semiconductor Manufacturing Company Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer
US6096649A (en) * 1999-10-25 2000-08-01 Taiwan Semiconductor Manufacturing Company Top metal and passivation procedures for copper damascene structures
US6265321B1 (en) * 2000-04-17 2001-07-24 Chartered Semiconductor Manufacturing Ltd. Air bridge process for forming air gaps
US6352921B1 (en) * 2000-07-19 2002-03-05 Chartered Semiconductor Manufacturing Ltd. Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
US6358842B1 (en) * 2000-08-07 2002-03-19 Chartered Semiconductor Manufacturing Ltd. Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
US6417093B1 (en) * 2000-10-31 2002-07-09 Lsi Logic Corporation Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106971974A (zh) * 2016-01-14 2017-07-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
WO2023024869A1 (zh) * 2021-08-23 2023-03-02 上海芯物科技有限公司 一种半导体表面平坦化的方法及制得的半导体和用途
CN114752938A (zh) * 2022-04-07 2022-07-15 中国科学院赣江创新研究院 一种完整去除Nb3Sn超导线稳定层和阻挡层的方法

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