CN1458681A - 在半导体组件上形成铜线的方法 - Google Patents

在半导体组件上形成铜线的方法 Download PDF

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CN1458681A
CN1458681A CN03101493A CN03101493A CN1458681A CN 1458681 A CN1458681 A CN 1458681A CN 03101493 A CN03101493 A CN 03101493A CN 03101493 A CN03101493 A CN 03101493A CN 1458681 A CN1458681 A CN 1458681A
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copper
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李秉周
金贤龙
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SK Hynix Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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Abstract

本发明提供一种能够防止铜的自然氧化的在半导体组件上形成铜线的方法。本发明的在半导体组件上形成铜线的方法包括下列步骤:于一半导体基板上形成一具有通孔与沟槽的绝缘膜图样;通过用铜填充通孔与沟槽而形成一铜线;顺序地在铜线与绝缘膜图样上形成一覆盖层(capping layer)与一保护层;通过选择性地去除覆盖层与保护层而露出铜线;以及,在铜线上形成一氧化防止层。依照本发明的在半导体组件上形成铜线的方法,有下列优点:铜的自然氧化可借着在铜线脚位上选择性的沉积铝而得到避免,因此在高温中测试其可靠度时,可得到稳定的评价结果;而且,因为铝比铜的接触阻抗低,所以在其电气特性的测试中,可得到令人信赖的测试结果。

Description

在半导体组件上形成铜线的方法
技术领域
本发明涉及一种在半导体组件上形成铜线(copper wire)的方法,特别是涉及一种防止铜的自然氧化的在半导体组件上形成铜线的方法。
背景技术
最近,半导体组件(semiconductor devices)变得更一体化,且其制程(processing)技艺也相对的有所改进,因此,提出了使用铜(Cu),取代传统技艺中的铝(Al),形成一配线(wire)的技艺,以改进组件的特性,例如操作速度、电阻、组件金属之间的寄生电容(parasitic capacitance)等。而且,代替传统技艺中所使用的由氧化物所制成的绝缘膜,使用了低介电常数(lowdielectric constant)的物质制成的绝缘膜,这被视为制备用于下一代半导体组件的配线的方法中的重要事件。
然而,使用铜与低介电常数材料的配线制造方法会发生因为铜的不良蚀刻特性所导致的问题。因此,取代传统的方法,例如在美国专利第5,635,423号所揭示的镶嵌方法(Damascene process)即被认为可适合于制造铜线。
根据现有技术,制备用于半导体组件的铜线的方法,兹参照图1A至图1E说明于下。
首先,如图1A所示,在一半导体基板10上顺序地形成一第一绝缘膜12、一蚀刻停止层(etching-interruption layer)14、与一第二绝缘层16。
其次,如图1B所示,在第二绝缘膜16上形成一宽度为d1的第一感光图样(photoresist pattern)18。然后,使用第一感光图样18作为光罩(mask)而进行蚀刻以选择性地去除第二绝缘膜16,直到蚀刻停止层14被曝露出来。如此,形成一第二绝缘膜图样16a。
接着,如图1C所示,第一感光图样18被去除,而在第二绝缘膜图样16a之上形成一宽度为d2(大于d1)的第二感光图样20。
然后,如图1D所示,使用第二感光图样20作为光罩,进行蚀刻程序,以选择性地去除蚀刻停止层14与第一绝缘膜12,通过该过程,亦即,二重镶嵌制程(Double Damascene Process),在基板10之上形成一宽度为d1的通孔(via hole)22,以及一宽度为d2的槽沟孔(trench hole)24。
最后,如图1E所示,以铜填充通孔22与槽沟孔24,以完成一铜线26。
然而,上述依照传统技艺的在半导体组件上形成铜线的方法,有以下的问题:
铜线相比于传统的铝合金(Al-0.5%Cu)配线有许多优点,其代表性的例子是电阻低与可靠度高。然而,铜线也有缺点:就是,铜的自然氧化。这种铜的自然氧化现象具有会导致铜线自身的可靠度降低,甚至会产生在包装期间使得结合特性(bonding property)劣化的问题。因此,需要采取适当的措施以避免具有铜线的半导体组件长时间在室温或较高的温度下使用而发生铜的自然氧化。
发明内容
因此,本发明旨在解决上述发生于传统技艺中的问题,故本发明的一个目的是提供一种在半导体组件上形成铜线的方法,其通过选择性的将铝沉积于铜线脚位(pad)的表面上而防止铜的自然氧化的发生。
为了达成上述目的,本发明所提供的在半导体组件上形成铜线的方法包括了下列步骤:在一半导体基板上形成一具有通孔(vias)与沟槽(trenches)的绝缘膜图样(insulation film pattern);通过用铜填充通孔与沟槽而形成一铜线;顺序地在铜线与绝缘膜图样上形成一覆盖层(capping layer)与一保护层(protective layer);通过选择性地去除覆盖层与保护层而露出铜线;以及,在铜配在线形成一氧化防止层(oxidation-prevention layer)。
依照本发明,通过选择性地将铝沉积于铜线上,防止铜的自然氧化。
本发明上述目的以及其它目的、优点、特征,参照下列依附图所作的优选具体实施例的说明将更为明白。
附图说明
图1A至图1E是现有技术中,在半导体组件上形成铜线的方法技术的制程截面图。
图2A至图2E是说明本发明的在半导体组件上形成铜线的方法的各个制程的截面图。
具体实施方式
下文中,参照附图,对本发明优选实施方案进行了描述。在下列说明和附图中,相同的符号表示相同或相似的部件,因此省略了相同或相似部件的重复描述。
图2A至图2E是说明本发明的在半导体组件上形成铜线的方法的各个制程的截面图。
首先,如图2A所示,在半导体基板100上形成包括通孔A与沟槽B的绝缘膜图样110(亦即,二重镶嵌图样)。在有些情况下,可于半导体基板100与绝缘膜图样110之间形成另外的铜线,然而,在本发明的实施例中假定没有这样的另外的铜线。
更特别的是,绝缘膜图样110以如下述的步骤形成。首先,一绝缘膜是使用一低介电常数的材料等而被沉积于半导体基板100上。接着,以一低介电常数的材料所作成的该层通过一光学制程(photo-process)被选择性地去除,以形成通孔A与沟槽B,然后,绝缘膜图样110与半导体基板100的表面通过氩高频等离子体处理法(Argon Radio-Frequency PlasmaProcessing)或氩(Ar)/氢(H2)高频等离子体处理法等清洁。
同时,虽然并未表示于图中,但利用一离子化物理气相沉积法在清洁制程以后沉积一铜阻挡层(barrier)与一种子(seed)层。此方法比传统的喷溅法(sputtering method)有一很大改进的步骤范围(step coverage),钽(Ta)或氮化钽(TaN)等,可使用为铜阻挡层。
其后,如图2B所示,通孔A与沟槽B利用电镀法等以铜填充,其次,通过去除一部份的铜,填充通孔和沟槽,且利用执行一化学/机械研磨(polish)制程而使绝缘膜图样110露出。因此形成一铜线120。
其次,如图2C所示,形成于铜线120上的自然氧化膜(未图示)被还原。然后,顺序地形成一覆盖层130与一保护层140于铜线120与绝缘膜110之上。
前述自然氧化膜在氮/氢气氛(atmoshere)下,进行快速热处理或等离子体处理而被还原。
提供覆盖层130用来防止在铜线120中的铜原子扩散进入上部层中,并且它是使用等离子体促进的化学气相沉积法(Plasma-Enhanced ChemicalVapor Deposition method),通过沉积例如氮化硅而使之未曝露于空气中而形成。铜原子如果扩散进入上部层中会引起配线间电流的泄漏。
保护层140则通过沉积一氧化硅、氮化硅或其它这种材料至大约3,000埃-10,000埃的厚度而形成的。当覆盖层130由氮化硅膜形成时,保护层优选由氧化硅膜形成。如果覆盖层130与保护层140都是由氮化硅膜形成时,会产生过度的应力(stress)。结果是,保护层140会有缺陷形成。
其次,如图2D所示,覆盖层130与保护层140利用曝露于光之中与一蚀刻制程等选择性的除去。如此即在一覆盖层图样130a与一保护层图样140a之间曝露出铜线。另外,通过使用一5%-10%HF的洗净溶液去除在曝露出来的铜线120上的自然氧化膜(未示)的步骤。
其后,如图2E所示,一氧化防止层150通过一化学气相沉积法形成在已曝露的铜线上,以防止铜的氧化。氧化防止层150通过使用例如二甲基氢化铝(dimethylaluminum hydride)作为前体(precursor)来沉积铝而形成。特别地,通过将二甲基氢化铝与氢反应,铝在230℃至350℃的温度时被选择地沉积在铜线120的表面上至仅为5,000埃-10,000埃厚度。
甚者,也可在200℃至400℃之间的温度进行热处理的步骤,以稳定所沉积的铝层150的结构。
如上述所述,依照本发明的在半导体组件上形成铜线的方法具有下列优点:
铜的自然氧化可通过在铜线脚位上选择性的沉积铝而得到避免,因此在高温中测试其可靠度时,可得到稳定的评价结果。
而且,因为铝比铜的接触阻抗(contact resistance)低,所以在其电气特性的测试中,可得到令人信赖的测试结果(dependable test result)。
本发明上述优选的具体实施例仅是用来说明本发明而已,本领域普通技术人员将会认识到可以对这些方案进行修正、增加或取代而未离开本发明的精神时,还落在本发明的权利权利要求保护的范围内。本发明的权利要求书并不仅限于上述公开的内容,并且包括落在本发明范围内的所有可授予专利的新内容以及所有本领域普通技术人员根据该公开内容可认识到的相当的特征。

Claims (7)

1.一种在半导体组件上形成铜线的方法,包括下列步骤:
于半导体基板上形成具有通孔与沟槽的绝缘膜图样;
通过用铜填充通孔与沟槽而形成铜线;
顺序地在铜线与绝缘膜图样上形成覆盖层与保护层;
通过选择性地去除覆盖层与保护层而露出铜线;
在铜线上形成氧化防止层;以及
去除在铜线上的自然氧化层。
2.如权利要求1所述的方法,其中在去除自然氧化层的步骤过程中,使用5%-10%的HF溶液。
3.如权利要求1所述的方法,其中氧化防止层是铝层。
4.如权利要求3所述的方法,其中铝层是使用二甲基氢化铝作为前体而利用化学气相沉积法形成的。
5.如权利要求4所述的方法,其中铝层是在230℃至350℃的温度被沉积并形成5,000埃至10,000埃的厚度。
6.如权利要求1所述的方法,其还包括在形成氧化防止层的步骤以后,进行热处理以稳定氧化防止层的结构的步骤。
7.如权利要求6所述的方法,其中热处理是在200℃至400℃的温度下进行10至30分钟。
CN03101493A 2002-05-16 2003-01-22 在半导体组件上形成铜线的方法 Pending CN1458681A (zh)

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