TW200307341A - Method of forming copper wire on semiconductor device - Google Patents
Method of forming copper wire on semiconductor device Download PDFInfo
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- TW200307341A TW200307341A TW091137968A TW91137968A TW200307341A TW 200307341 A TW200307341 A TW 200307341A TW 091137968 A TW091137968 A TW 091137968A TW 91137968 A TW91137968 A TW 91137968A TW 200307341 A TW200307341 A TW 200307341A
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- copper
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- copper wiring
- copper wire
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229910052802 copper Inorganic materials 0.000 claims abstract description 54
- 239000010949 copper Substances 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims abstract description 33
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 239000011241 protective layer Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000002265 prevention Effects 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000011156 evaluation Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910000831 Steel Inorganic materials 0.000 description 8
- 239000010959 steel Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- MOWCJHPOKDCGGT-UHFFFAOYSA-N CCCCCC.[Cu] Chemical compound CCCCCC.[Cu] MOWCJHPOKDCGGT-UHFFFAOYSA-N 0.000 description 1
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000796 flavoring agent Substances 0.000 description 1
- 235000019634 flavors Nutrition 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
200307340 五、發明說明(1) 【本發明所屬之技術領域】 本發明是有關一種在半導體元件上形成銅配線的方法, 特別是有關一種銅的自然氧化可予以防止之在半導體元件上 形成銅配線的方法。 、【先前技術】 隶近’半導體元件乃變為更積體化,且其製程技藝也相 對的有所改進,因此,一使用銅(C u ),而取代了傳統技藝之 I呂(A 1)’以形成一配線的技藝已被提出,以改進元件的特 性’例如操作速度、電阻、元件金屬之間的寄生電容 (parasitic capacitance)等。甚且,傳統技藝中所使用的幻 一氧化物所製成的絕緣膜,也以一低介電常數(1 〇w dielectric constant)的物質來取代,而此並被視為下一代 半導體元件之配線形成製程的重要事件。 然而’使用銅與低介電常數材料的配線製造方法會發生 因為銅的不良蝕刻特性所導致的問題。因此,取代傳統的製 程’在美國專利第5, 63 5, 423號所揭示的一鑲嵌方法 (Damascene)即被認為可適合於製造銅配線。 傳統在在半導體元件上形成銅配線的方法,茲參照第工A 圖至第1E圖說明於下。 首先,如第1 A圖所示,一第一絕緣膜1 2、一姓刻停止層 1 4、與一第二絕緣層1 6乃順序地形成在一半導體基板1 〇上。 其次’如第1B圖所示,一寬度為dl之第一感光圖樣18乃 被形成在第二絕緣膜1 6上。然後,使用第一感光圖樣1 8作為 光罩而進行姓刻以選擇性地去除第二絕緣膜丨6直到蝕刻停止
200307340 五、、發明說明(2) 層1 4被曝露出來。如此,形成一第二絕緣膜圖樣1 6a。 接著,如第1C圖所示,第一感光圖樣18乃被去除而一寬 度為d2(大於dl )之第二感光圖樣20乃被形成在第二絕緣膜圖 樣1 6 a之上。 然後,如第1 D圖所示,使用第二感光圖樣2 0作為光罩, 進行蝕刻程序,以選擇性地去除蝕刻停止層1 4與第一絕緣膜 12,通過此製程,亦即,二重鑲嵌製程(Double Damascene Process),一寬度為dl之通孔22,以及一寬度為d2之槽溝孔 2 4乃形成於基板1 〇之上。 最後,如 也有一缺點: 有會導致銅配 特性(bondi ng 以避免具有鋼 而發生銅的自 、【本發明之内 第1E圖所示,通孔22與槽溝孔24以鋼填充 芩成一銅配線2 6 主發明要鼓j失的課題 然而,上 的方法,有以 一銅配線 優點,其代表 述依照傳統技藝的在半導體元件上形成銅配線 下之問題: 較諸傳統的鋁合金(A1 _05%Cu)配線有許多 性的例子有電阻低與可靠度高。然而,銅配線 =,銅的自然氧化’此一鋼的自然氧化現象 線的可靠度降低,其至於在包t期間會使結合 yoperty)劣化的問題點。因此 然氧化實為必^間溫或—高溫使用 容】 本發明即旨冰#、& 的上述問題, 上形成銅配線
第7頁 故本發明之:Ϊ進上述發生於傳統技 月之—目的乃在提供一種在半導體 200307340 五、發明說明(3) 的方法,其藉由選擇性的沈積鋁於銅配線腳位(pad)而可防 鋼自然氧化的發生。 為了達成上述之目的,本發明所提供之在半導體元件上 形成銅配線的方法包括了下列步驟:於一半導體基板上形成 一具有通孔與溝槽之絕緣膜圖樣;藉由以銅填充通孔與溝槽 而形成一銅導線;順序地在銅導線與絕緣膜圖樣上形成一覆 蓋層(capping layer)與一保護層;藉由選擇性地去除覆蓋i 與保護層而露出銅配線;以及,在銅配線上形成一氧化防止 層。 依照本發明,其藉由選擇性地沈積銘於銅配線上,可防· 止鋼的自然氧化。 本發明上述之目的以及其他特徵,參照下列依附圖所作 之較佳具體實施例的說明將更為明白。 【本發明之實施方式】 • 第2A圖至第2E圖係說明本發明之在半導體元件上形成銅 配線的方法的各個製程的截面圖。 士 ★本發明之在半導體元件上形成銅配線的方法係,首先, 如第2A圖所示,在半導體基板1〇〇上形成包括通孔a與溝槽b 、是、、彖膜圖樣1 1 〇 (亦即,二重鑲後圖樣)。在此,一另外的 、5配線可形成於半導體基板丨〇 〇與絕緣膜圖樣丨丨〇之間,然 2 φ ί發明之實施例中僅對於沒有此另外之下部銅銅配線者 ,、更特別的是,絕緣膜圖樣丨丨0係以如下述之步驟被形成 ,百先,一絕緣膜乃使用一低介電常數之材料等被沈積於半
第8頁 200307340 五、發明說明(4) ' 導體基板1 0 〇上。接著,以一低介電常數之材料所作成之該 層絕緣膜乃通過一光學製程被選擇性地去除,以形成通孔A 與溝槽β,然後,絕緣膜圖樣11()與半導體基板1〇〇乃通過一 氬(Ar)/氫(HO高週波電漿處理法等洗淨。 同時’雖然並未表示於圖中,一銅阻擋層與一種子 (Seed)層乃利用一離子化物理氣相沈積法在洗淨製程以後被 /尤積、。此方法比較傳統的喷濺法(Sputtering 有一很 Π:::乾圍(SteP C〇Urage),鈕(Ta)或氮化鈕(TaN) 4 ’可使用為鋼阻擋層。 銅填ί後其Ϊ第二通孔A與溝槽β係利用電鍵法等以 、 a由去除一部份的銅而使絕緣膜圖樣11 0露 12。。仃-化學/機械研磨製程,而形成-銅配線 八人如第2C圖所示,形成於銅配線1 20上之自妷氣化 膜(未圖示)乃被還原。妙 上之自然軋化 保破f 140於銅導線12〇與絕緣膜1Η之上。 兴 前述自然氧化膜将夺丨田 ^ . 、击舳老细々 、^利用於一氮/氫之氣壓下,進行一快 速熱處理或一電浆處理而被還原。 進灯味 入上ΪΪΓ,30其係是提:用來:止在銅配線12。中的鋼原子擴散進 沈積法’氮化矽而使之=二例如’使用電漿促進化學氣相 散進入上部層中备引路於空氣中而形成,銅原子的擴 保護層1二Λ 間,流… 糧材料至大約3,。00入〜“二匕:屋二化矽、或其他之此 ,0 0 0 Α的厚度。當覆蓋層1 3 0係以
第9頁 200307340 五、發明說明(5) 5 # ι5ίΓ::成時,保護層較佳的是以氧化矽膜形成。如果覆 層140係以氮化石夕膜形成時,會產生過度的應 w^tress),其結果,保護層14〇即有缺陷之形成。 •π 由t1第2D圖所示,覆蓋層130與保護層140係利用曝 ^衣先之中與—蝕刻製程等選擇性的形成。如此即在一 層圖樣13〇&與—保護層圖樣140a之間曝露出銅導線。進者, n使用—5%〜10%HF的洗淨溶液去除在曝露出來的銅 -己、、泉〇上的自然氧化膜(未示)之步驟可被執行。 其後,如第2E圖所示,一氧化防止層丨5〇係藉由一化學 氣相沈積法形成在已曝露的銅導線上,以防止銅的氧化。氧U 化防止層150係藉由例如使用二曱基氫化鋁(dimethylaiuminiim hydride)作為前驅物(precursor)沈積鋁來形成。特別地,藉 由將二曱基氫化鋁與氫反應,鋁在溫度為23〇 〇c至35〇它時乃 被選擇地沈積在銅線120的表面上至僅為5,〇〇〇 a〜1〇, 〇〇〇 a 的厚度。 ’ 甚者,也可在2 0 0它至40 0。(:之間的溫度進行一熱處理的 步驟,以穩定所沈積的鋁層1 5 〇的構造。 如上述之說明,依照本發明之半導體元件上形成鋼配線 的方法,有下列優點: 銅的自然氧化可藉著在銅配線腳位上選擇性的沈積鋁而 得到避免,因此在高溫中測試其可靠度時,可得到穩定的評 價結果。 而且,因為鋁比銅的接觸阻抗為低,在其電氣特性的測 試中,可得到令人信賴的測試結果。
第10頁 200307340 五、發明說明(6) 本發明上述之較佳具體實施例乃僅用來說明本發明而 已,對於熟悉此項技藝之人士而言,其所作可能的修正、增 加或取代而未離開本發明之精神時,應該在本發明之權利範 圍之内。
第11頁 200307340 圖式簡單說明 第1 A圖至1 E圖係傳統半導體元件上形成銅配線的方法技 術之製程截面圖。 第2A圖至第2E圖係說明本發明之在半導體元件上形成銅 配線的方法的各個製程的截面圖。 【圖中元件編號與名稱對照表】 10 半導體基 板 12 絕緣膜 14 停止層 16 第二絕緣 膜 16a :第二緣緣膜圖 18 第一感光 圖樣 20 第二感光 圖樣 22 通孔 24 槽溝孔 26 銅配線 100 :半導體基板 110 :絕緣膜圖樣 120 :銅配線 130 :覆蓋層 130 a :覆蓋層 圖樣 140 :保護層 140 a :保護層 圖樣 150 :氧化防止層
第12頁
Claims (1)
- 200307340 六、申請專利範圍 1 · 一種在半導體元件上形成銅配線的方法,其特徵在 於·是種在半導體元件上形成銅配線的方法包含下列步驟: 於一半導體基板上形成一具有通孔與溝槽之絕緣膜圖 樣; 藉由以銅填充通孔與溝槽而形成一銅導線; 順序地在銅k線與絕緣膜圖樣上形成一覆蓋層(c a p p i n & 1 ay er )與一保護層; 藉由逑擇性地去除覆蓋層與保護層而露出銅配線; 在銅配線上形成一氧化防止層;以及 去除在銅配線上的自然氧化層。 2 ·如申請專利範圍第丨項之在半導體元件上形成銅配線 的方法,其中在去除自然氧化層之步驟中,使用一 5 %〜i 〇 %的!^溶液。 3.如申請專利範圍n 1 + + &播 :⑴靶国弟丨項之在+導體元件上形成銅配線 的方法’其中氧化防止層係鋁層者。 4·如申請專利範圍第3項在本 的方法,其中铭層係使用二頁甲之//化導招體;^上形成銅配線 化學氣相沈積法形成。甲基…作為前驅物而利用- 5.如申請專利範圍第4項 的方法,其中铭層係在23。二,J牛上形成銅配線 5,。。“至1。,。0。1之厚】?至35°。的溫度被沈積並形成- 的方^ = ϊί ί Ϊ Ϊ ΐ =^方在止半/體+元件上形成銅配線 處理以穩定氧化防止層之構造的步;之步驟以後’進打-熱第13頁 200307340第14頁
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KR10-2002-0027010A KR100480891B1 (ko) | 2002-05-16 | 2002-05-16 | 반도체 소자의 구리배선 형성방법 |
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TW091137968A TW200307341A (en) | 2002-05-16 | 2002-12-31 | Method of forming copper wire on semiconductor device |
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US (1) | US6878617B2 (zh) |
KR (1) | KR100480891B1 (zh) |
CN (1) | CN1458681A (zh) |
TW (1) | TW200307341A (zh) |
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KR100691019B1 (ko) | 2006-04-24 | 2007-03-09 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
CN102005397B (zh) * | 2009-08-31 | 2012-09-26 | 中芯国际集成电路制造(上海)有限公司 | 提高芯片键合块抗腐蚀性的方法 |
JP2012124452A (ja) * | 2010-12-06 | 2012-06-28 | Samsung Electro-Mechanics Co Ltd | プリント基板およびその製造方法 |
US20190326112A1 (en) * | 2018-04-19 | 2019-10-24 | Globalfoundries Inc. | DEFECT FREE SILICON GERMANIUM (SiGe) EPITAXY GROWTH IN A LOW-K SPACER CAVITY AND METHOD FOR PRODUCING THE SAME |
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JPS598663A (ja) * | 1982-07-06 | 1984-01-17 | 株式会社クラレ | 繊維強化された水硬性成型品 |
US4902347A (en) * | 1988-03-28 | 1990-02-20 | Board Of Trustees Operating Michigan State University | Polyamide fibers, microsilica and Portland cement composites and method for production |
KR940001261A (ko) * | 1992-06-10 | 1994-01-11 | 문정환 | 자연산화막 제거방법 |
KR0147682B1 (ko) * | 1994-05-24 | 1998-11-02 | 구본준 | 반도체 소자의 금속배선 제조방법 |
US5677244A (en) * | 1996-05-20 | 1997-10-14 | Motorola, Inc. | Method of alloying an interconnect structure with copper |
JP3647631B2 (ja) * | 1997-07-31 | 2005-05-18 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
TW392325B (en) * | 1998-05-01 | 2000-06-01 | United Microelectronics Corp | Structure of metallization and process thereof |
US6372633B1 (en) * | 1998-07-08 | 2002-04-16 | Applied Materials, Inc. | Method and apparatus for forming metal interconnects |
US6100195A (en) * | 1998-12-28 | 2000-08-08 | Chartered Semiconductor Manu. Ltd. | Passivation of copper interconnect surfaces with a passivating metal layer |
US6103624A (en) * | 1999-04-15 | 2000-08-15 | Advanced Micro Devices, Inc. | Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish |
JP2001144092A (ja) * | 1999-11-15 | 2001-05-25 | Toshiba Corp | 半導体装置の製造方法 |
US6191023B1 (en) * | 1999-11-18 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of improving copper pad adhesion |
US6373137B1 (en) * | 2000-03-21 | 2002-04-16 | Micron Technology, Inc. | Copper interconnect for an integrated circuit and methods for its fabrication |
US6452251B1 (en) * | 2000-03-31 | 2002-09-17 | International Business Machines Corporation | Damascene metal capacitor |
US6376353B1 (en) * | 2000-07-03 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects |
US6977224B2 (en) * | 2000-12-28 | 2005-12-20 | Intel Corporation | Method of electroless introduction of interconnect structures |
US6521523B2 (en) * | 2001-06-15 | 2003-02-18 | Silicon Integrated Systems Corp. | Method for forming selective protection layers on copper interconnects |
US6338999B1 (en) * | 2001-06-15 | 2002-01-15 | Silicon Integrated Systems Corp. | Method for forming metal capacitors with a damascene process |
US6664187B1 (en) * | 2002-04-03 | 2003-12-16 | Advanced Micro Devices, Inc. | Laser thermal annealing for Cu seedlayer enhancement |
US6562711B1 (en) * | 2002-06-28 | 2003-05-13 | Intel Corporation | Method of reducing capacitance of interconnect |
US6777318B2 (en) * | 2002-08-16 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company | Aluminum/copper clad interconnect layer for VLSI applications |
-
2002
- 2002-05-16 KR KR10-2002-0027010A patent/KR100480891B1/ko active IP Right Grant
- 2002-12-30 US US10/331,428 patent/US6878617B2/en not_active Expired - Lifetime
- 2002-12-31 TW TW091137968A patent/TW200307341A/zh unknown
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2003
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KR20030089567A (ko) | 2003-11-22 |
US6878617B2 (en) | 2005-04-12 |
US20030216040A1 (en) | 2003-11-20 |
CN1458681A (zh) | 2003-11-26 |
KR100480891B1 (ko) | 2005-04-07 |
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