CN1430249A - 避免尖峰现象的方法 - Google Patents

避免尖峰现象的方法 Download PDF

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CN1430249A
CN1430249A CN02155241.XA CN02155241A CN1430249A CN 1430249 A CN1430249 A CN 1430249A CN 02155241 A CN02155241 A CN 02155241A CN 1430249 A CN1430249 A CN 1430249A
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layer
processing procedure
metal silicide
barrier layer
rapid thermal
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林文正
蓝仁宏
林永昌
李宗翰
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United Microelectronics Corp
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Abstract

一种避免尖峰现象的方法，先于一半导体基底表面形成一多晶硅层，接着进行一准直管物理气相沉积制程，以于该多晶硅层表面形成一氮化钛层，随后再进行一快速高温氮化制程，以致密化该氮化钛层；最后于该氮化钛层表面形成一金属硅化物层；其中，该氮化钛层可有效抑制该金属硅化物层与该多晶硅层发生尖峰现象；相较于习知制作导线结构中阻障层的方法，本发明于阻障层的溅镀制程中使用准直管作为辅助，而且在溅镀制程之后更进行一快速高温氮化制程，因此可以有效改善阻障层的均匀性以及致密性，进而避免金属硅化物层发生尖峰现象，降低导线的接触电阻，并且提升产品的可靠度。

Description

避免尖峰现象的方法
技术领域
本发明涉及半导体制造技术，尤其是一种避免金属硅化物层发生尖峰(spike)现象的方法，该方法可避免嵌入式动态随机存取存储器(embeddeddynamic random access memory，EDRAM)栅极中的金属硅化物层发生尖峰现象的方法，以改善嵌入式存储器的电性表现。
背景技术
动态随机存取存储器(dynamic random access memory，DRAM)主要由一包含有数以万计存储单元(memory cell)的存储区以及一逻辑控制电路(logic circuit)所构成。而随着制程积集度的不断提升，现今制作半导体集成电路的趋势是将存储元阵列(memory cell array)与高速逻辑电路元件(high-speed logic circuit elements)进行整合，同时制作在一个晶片(chip)上，形成一种同时结合了存储器阵列以及逻辑电路(logic circuits)的嵌入式动态随机存取存储器(embedded DRAM)，以大幅节省面积并加快信号的处理速度。
在整合存储阵列区与周边电路区的栅极制程时，为了提高周边电路区的元件电性表现，习知技术多是在栅极结构中的多晶硅层表面形成一金属硅化物层，藉以降低栅极的接触电阻。然而由于硅具有溶解钛(titanium，Ti)、铝(aluminum，Al)等金属的特性，致使形成于多晶硅层上方的金属会从金属-硅的介面(interface)穿透到多晶硅层中，进而形成一尖峰形状，影响栅极的电性表现。目前消除此一尖峰形状的方法先于多晶硅层表面形成一阻障层，之后再于阻障层表面形成该金属硅化物层，如此一来即可通过阻障层遏制金属向下扩散而产生尖峰现象。
请参考图1与图2，图1与图2为习知于一半导体基底10上制作一嵌入式动态随机存取存储器(未显示)的栅极20的方法示意图。如图1所示，制作栅极20的方法依序于半导体基底10表面形成一硅氧层12、一多晶硅层14、一阻障层16以及一金属硅化物层18。其中，阻障层16为一氮化钛(titanium nitride，TiN)层，金属硅化物层18为一钛金属硅化物(titaniumsilicide，TiSi2)层。习知形成阻障层16的方法多是利用一物理气相沉积，例如反应性溅镀，通过反应室中的氩气与氮气作为反应气体，将金属靶中的钛轰击出来，接着再使钛与经等离子解离的氮原子反应形成氮化钛沉积于多晶硅层14表面。一般而言，利用反应性溅镀所形成的阻障层16其结构致密性并不理想，因此在后续的热制程中，并无法抑制金属硅化物层18中的金属向下扩散，进而使金属硅化物层18产生一侵入阻障层16中，甚至直接侵入多晶硅层14中的尖峰结构19。
之后如图2所示，进行一黄光暨蚀刻制程，先于半导体基底10表面涂布一光阻层，并于光阻层中定义出栅极的图案，接着依照光阻层的图案去除部份的金属硅化物层18、阻障层16、多晶硅层14以及硅氧层12，直至半导体基底10表面，以形成栅极20。而欲完成嵌入式动态随机存取存储器的MOS晶体管，还须形成源极与漏极等结构，然此并非习知技术所探讨的重点，故在此不多赘述。
由于习知的物理气相沉积方式无法提供阻障层16良好的结构致密性，因此可能导致金属硅化物层18的尖峰结构19的发生，形成漏电或其他影响电性表现的不良后果，而且由于部分穿透阻障层16的尖峰结构19会影响整个阻障层16的应力性质，因此亦使得栅极20的可靠度大为降低。
发明内容
因此，本发明的目的即在避免习知技术中金属硅化物的尖峰现象。
本发明的另一目的是提供一种改善嵌入式动态随机存取存储器的环形震荡周期(ring oscillator period)的方法，以提升产品的可靠度。
在本发明的最佳实施例中，首先于一半导体基底表面形成一多晶硅层，接着进行一准直管物理气相沉积制程(collimator physical vapordeposition)，以于该多晶硅层表面形成一阻障层，随后再进行一快速热制程(rapid thermal process，RTP)，以使该阻障层致密化。最后于该阻障层表面形成一金属硅化物层。
由于本发明于形成阻障层的过程中使用准直管作为辅助，而且在沉积阻障层之后更进行一快速高温热制程，因此可以有效改善阻障层的均匀性以及致密性，进而避免金属硅化物层发生尖峰现象，降低多晶硅层的接触电阻，并且提升产品的可靠度。此外，当本发明的制作阻障层的方法应用于嵌入式动态随机存取存储器，特别是逻辑电路区内的MOS晶体管的栅极结构时，随着栅极电阻值的降低可以减少逻辑电路区的环形震荡周期，亦即减少逻辑电路区的延迟反应时间，进而可以提高逻辑运算能力，改善元件的电性表现。
附图说明
图1与图2为习知制作一导线的方法示意图；
图3与图4为本发明制作一导线的方法示意图。
图示的符号说明：
10、30半导体基底      12、32硅氧层
14、34多晶硅层        16、36阻障层
18、38金属硅化物层    19尖峰结构
20栅极                40导线
具体实施方式
请参考图3与图4，图3与图4为本发明于一半导体基底30上制作一嵌入式动态随机存取存储器(未显示)的导线40的方法示意图。导线40主要用来形成一字元线、一位元线或一栅极结构。如图3所示，制作导线40的方法包括先于半导体基底30表面进行一高温热氧化制程，以于半导体基底30表面均匀形成一硅氧层32。随后进行一薄膜沉积制程，通常一低压气相化学沉积法，以于硅氧层32上形成一多晶硅层34。此外，为了降低多晶硅层34的电阻，尚须再进行一掺杂制程，以掺杂至少一掺质于多晶硅层34之内。掺杂制程通常有两种方式，第一种是在形成多晶硅层34时，便直接通过同时(in-situ)生成的方式将掺质趋入多晶硅层34，第二种则是在多晶硅层34形成之后，再通过高温扩散(diffusion)或植入(implantation)的方式，将掺质植入于多晶硅层34。
在形成多晶硅层34后，接下来即进行一物理气相沉积制程，以于多晶硅层34表面形成一由氮化钛所构成的阻障层36。为了避免阻障层36产生如习知技术的结构致密性不足的问题，本发明的物理气相沉积制程利用准直管来降低阻障层36的沉积速度以及溅镀的角度，以使阻障层36得以均匀沉积并获得一致密结构。之后，再进行一快速热制程，例如一快速高温氮化制程(rapid thermal nitridation，RTN)，控制温度约介于600至850℃之间，以再次地致密化并固化阻障层36的结构。而为了减少因使用准直管所增加的制程时间，在本发明的最佳实施例中，上述物理气相沉积为一高功率溅镀制程，亦即使等离子功率调整至约介于10千瓦(kilowatt，KW)至20千瓦之间，以加速等离子解离速率。随后，于阻障层36表面形成一金属硅化物层38，例如一钛金属硅化物层。
之后如图4所示，进行一黄光暨蚀刻制程，先于半导体基底30表面涂布一光阻层(未显示)，并于光阻层中定义出导线的图案，接着依照光阻层的图案去除部份的金属硅化物层38、阻障层36、多晶硅层34以及硅氧层32，直至半导体基底30表面，以形成导线40。当然欲完成嵌入式动态随机存取存储器的MOS晶体管以及其他结构，犹须形成轻掺杂漏极(LDD)、侧壁子(spacer)、源极与漏极等等，然此亦非本发明的重点，故不再赘述。
本发明的特征是利用一准直管来进行高功率溅镀制程，以使阻障层36具有较为致密的结构，此外，本发明于溅镀制程之后更进行一快速高温氮化制程，以再次强化阻障层36的结构，因此可以有效避免金属硅化物层38发生尖峰现象，避免发生漏电流，同时更可以改善阻障层36的应力性质，以及降低导线40的接触电阻。而当本发明的制作导线40的方法应用于嵌入式动态随机存取存储器，特别是逻辑电路区内的MOS晶体管的栅极结构时，随着栅极电阻值的降低可以减少逻辑电路区的环形震荡周期，亦即减少逻辑电路区的延迟反应时间，因此可以提高逻辑运算能力，以有效改善元件的电性表现。
相较于习知制作导线结构中阻障层的方法，本发明于阻障层的溅镀制程中使用准直管作为辅助，而且在溅镀制程之后更进行一快速高温氮化制程，因此可以有效改善阻障层的均匀性以及致密性，进而避免金属硅化物层发生尖峰现象，降低导线的接触电阻，并且提升产品的可靠度。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明专利的涵盖范围。

Claims (13)

1.一种避免一金属硅化物层发生尖峰现象的方法，其特征是：该方法包含有下列步骤：
提供一半导体基底；
于该半导体基底表面形成一多晶硅层；
进行一准直管物理气相沉积制程，以于该多晶硅层表面形成一氮化钛层，以及进行一快速热制程，以使该氮化钛层致密化；以及
于该氮化钛层表面形成该金属硅化物层。
2.如权利要求1所述的方法，其特征是：该物理气相沉积制程为一高功率溅镀制程。
3.如权利要求2所述的方法，其特征是：该高功率溅镀制程的功率约介于10千瓦至20千瓦之间。
4.如权利要求1所述的方法，其特征是：该快速热制程为一快速高温氮化制程，且该快速热制程的温度约介于600至850℃之间。
5.如权利要求1所述的方法，其特征是：该金属硅化物层由钛金属硅化物所构成。
6.如权利要求1所述的方法，其特征是：该多晶硅层用来形成一字元线、一位元线或一栅极结构，且该金属硅化物层用来降低该字元线、该位元线或该栅极结构的接触电阻。
7.一种改善嵌入式动态随机存取存储器的环形震荡周期的方法，该嵌入式动态随机存取存储器包含有一多晶硅层设于一半导体基底上，其特征是：该方法包含有下列步骤：
利用一准直管进行一高功率溅镀制程，以于该多晶硅层表面形成一均匀阻障层；
进行一快速热制程，以致密化该阻障层；以及
于该阻障层表面形成一金属硅化物层；
其中该阻障层可以避免该金属硅化物发生尖峰现象，以提供该嵌入式动态随机存取存储器一低接触电阻，并降低该嵌入式动态随机存取存储器的环形震荡周期。
8.如权利要求7所述的方法，其特征是：于形成该金属硅化物层后，该方法另包含一黄光暨蚀刻制程，该黄光暨蚀刻制程去除部份的该金属硅化物层、该阻障层、以及该多晶硅层，以形成一导线，其中该阻障层可用来降低该导线的环形震荡周期。
9.如权利要求8所述的方法，其特征是：该导线包含一字元线、一位元线或一栅极结构。
10.如权利要求7所述的方法，其特征是：该阻障层由氮化钛所构成。
11.如权利要求10所述的方法，其特征是：该快速热制程为一快速高温氮化制程，且该快速热制程的温度约介于600至850℃之间。
12.如权利要求7所述的方法，其特征是：该金属硅化物层由钛金属硅化物所构成。
13.如权利要求7所述的方法，其特征是：该高功率溅镀制程的功率约介于10千瓦至20千瓦之间。
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CN103137672A (zh) * 2011-11-25 2013-06-05 上海华虹Nec电子有限公司 兼容自对准孔和表面沟道的金-氧-半场效应管的栅极膜结构及其制造方法

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